Lines Matching refs:tqspi
232 static inline u32 tegra_qspi_readl(struct tegra_qspi *tqspi, unsigned long offset) in tegra_qspi_readl() argument
234 return readl(tqspi->base + offset); in tegra_qspi_readl()
237 static inline void tegra_qspi_writel(struct tegra_qspi *tqspi, u32 value, unsigned long offset) in tegra_qspi_writel() argument
239 writel(value, tqspi->base + offset); in tegra_qspi_writel()
243 readl(tqspi->base + QSPI_COMMAND1); in tegra_qspi_writel()
246 static void tegra_qspi_mask_clear_irq(struct tegra_qspi *tqspi) in tegra_qspi_mask_clear_irq() argument
251 value = tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS); in tegra_qspi_mask_clear_irq()
252 tegra_qspi_writel(tqspi, value, QSPI_TRANS_STATUS); in tegra_qspi_mask_clear_irq()
254 value = tegra_qspi_readl(tqspi, QSPI_INTR_MASK); in tegra_qspi_mask_clear_irq()
257 tegra_qspi_writel(tqspi, value, QSPI_INTR_MASK); in tegra_qspi_mask_clear_irq()
261 value = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_mask_clear_irq()
263 tegra_qspi_writel(tqspi, QSPI_ERR | QSPI_FIFO_ERROR, QSPI_FIFO_STATUS); in tegra_qspi_mask_clear_irq()
267 tegra_qspi_calculate_curr_xfer_param(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_calculate_curr_xfer_param() argument
270 unsigned int remain_len = t->len - tqspi->cur_pos; in tegra_qspi_calculate_curr_xfer_param()
273 tqspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_qspi_calculate_curr_xfer_param()
284 tqspi->is_packed = true; in tegra_qspi_calculate_curr_xfer_param()
285 tqspi->words_per_32bit = 32 / bits_per_word; in tegra_qspi_calculate_curr_xfer_param()
287 tqspi->is_packed = false; in tegra_qspi_calculate_curr_xfer_param()
288 tqspi->words_per_32bit = 1; in tegra_qspi_calculate_curr_xfer_param()
291 if (tqspi->is_packed) { in tegra_qspi_calculate_curr_xfer_param()
292 max_len = min(remain_len, tqspi->max_buf_size); in tegra_qspi_calculate_curr_xfer_param()
293 tqspi->curr_dma_words = max_len / tqspi->bytes_per_word; in tegra_qspi_calculate_curr_xfer_param()
296 max_word = (remain_len - 1) / tqspi->bytes_per_word + 1; in tegra_qspi_calculate_curr_xfer_param()
297 max_word = min(max_word, tqspi->max_buf_size / 4); in tegra_qspi_calculate_curr_xfer_param()
298 tqspi->curr_dma_words = max_word; in tegra_qspi_calculate_curr_xfer_param()
306 tegra_qspi_fill_tx_fifo_from_client_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_fill_tx_fifo_from_client_txbuf() argument
310 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
313 fifo_status = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
316 if (tqspi->is_packed) { in tegra_qspi_fill_tx_fifo_from_client_txbuf()
317 fifo_words_left = tx_empty_count * tqspi->words_per_32bit; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
318 written_words = min(fifo_words_left, tqspi->curr_dma_words); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
319 len = written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
326 tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
329 tqspi->cur_tx_pos += written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
332 u8 bytes_per_word = tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
334 max_n_32bit = min(tqspi->curr_dma_words, tx_empty_count); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
336 len = written_words * tqspi->bytes_per_word; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
337 if (len > t->len - tqspi->cur_pos) in tegra_qspi_fill_tx_fifo_from_client_txbuf()
338 len = t->len - tqspi->cur_pos; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
345 tegra_qspi_writel(tqspi, x, QSPI_TX_FIFO); in tegra_qspi_fill_tx_fifo_from_client_txbuf()
348 tqspi->cur_tx_pos += write_bytes; in tegra_qspi_fill_tx_fifo_from_client_txbuf()
355 tegra_qspi_read_rx_fifo_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_read_rx_fifo_to_client_rxbuf() argument
357 u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
362 fifo_status = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_read_rx_fifo_to_client_rxbuf()
364 if (tqspi->is_packed) { in tegra_qspi_read_rx_fifo_to_client_rxbuf()
365 len = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
367 x = tegra_qspi_readl(tqspi, QSPI_RX_FIFO); in tegra_qspi_read_rx_fifo_to_client_rxbuf()
373 read_words += tqspi->curr_dma_words; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
374 tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
377 u8 bytes_per_word = tqspi->bytes_per_word; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
381 if (len > t->len - tqspi->cur_pos) in tegra_qspi_read_rx_fifo_to_client_rxbuf()
382 len = t->len - tqspi->cur_pos; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
385 x = tegra_qspi_readl(tqspi, QSPI_RX_FIFO) & rx_mask; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
392 tqspi->cur_rx_pos += read_bytes; in tegra_qspi_read_rx_fifo_to_client_rxbuf()
399 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_copy_client_txbuf_to_qspi_txbuf() argument
401 dma_sync_single_for_cpu(tqspi->dev, tqspi->tx_dma_phys, in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
402 tqspi->dma_buf_size, DMA_TO_DEVICE); in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
412 if (tqspi->is_packed) { in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
413 tqspi->cur_tx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
415 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
422 consume = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
423 if (consume > t->len - tqspi->cur_pos) in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
424 consume = t->len - tqspi->cur_pos; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
426 for (count = 0; count < tqspi->curr_dma_words; count++) { in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
429 for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--) in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
431 tqspi->tx_dma_buf[count] = x; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
434 tqspi->cur_tx_pos += write_bytes; in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
437 dma_sync_single_for_device(tqspi->dev, tqspi->tx_dma_phys, in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
438 tqspi->dma_buf_size, DMA_TO_DEVICE); in tegra_qspi_copy_client_txbuf_to_qspi_txbuf()
442 tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf() argument
444 dma_sync_single_for_cpu(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
445 tqspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
447 if (tqspi->is_packed) { in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
448 tqspi->cur_rx_pos += tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
450 unsigned char *rx_buf = t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
459 consume = tqspi->curr_dma_words * tqspi->bytes_per_word; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
460 if (consume > t->len - tqspi->cur_pos) in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
461 consume = t->len - tqspi->cur_pos; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
463 for (count = 0; count < tqspi->curr_dma_words; count++) { in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
464 u32 x = tqspi->rx_dma_buf[count] & rx_mask; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
466 for (i = 0; consume && (i < tqspi->bytes_per_word); i++, consume--) in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
470 tqspi->cur_rx_pos += read_bytes; in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
473 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
474 tqspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf()
484 static int tegra_qspi_start_tx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len) in tegra_qspi_start_tx_dma() argument
488 reinit_completion(&tqspi->tx_dma_complete); in tegra_qspi_start_tx_dma()
490 if (tqspi->is_packed) in tegra_qspi_start_tx_dma()
493 tx_dma_phys = tqspi->tx_dma_phys; in tegra_qspi_start_tx_dma()
495 tqspi->tx_dma_desc = dmaengine_prep_slave_single(tqspi->tx_dma_chan, tx_dma_phys, in tegra_qspi_start_tx_dma()
499 if (!tqspi->tx_dma_desc) { in tegra_qspi_start_tx_dma()
500 dev_err(tqspi->dev, "Unable to get TX descriptor\n"); in tegra_qspi_start_tx_dma()
504 tqspi->tx_dma_desc->callback = tegra_qspi_dma_complete; in tegra_qspi_start_tx_dma()
505 tqspi->tx_dma_desc->callback_param = &tqspi->tx_dma_complete; in tegra_qspi_start_tx_dma()
506 dmaengine_submit(tqspi->tx_dma_desc); in tegra_qspi_start_tx_dma()
507 dma_async_issue_pending(tqspi->tx_dma_chan); in tegra_qspi_start_tx_dma()
512 static int tegra_qspi_start_rx_dma(struct tegra_qspi *tqspi, struct spi_transfer *t, int len) in tegra_qspi_start_rx_dma() argument
516 reinit_completion(&tqspi->rx_dma_complete); in tegra_qspi_start_rx_dma()
518 if (tqspi->is_packed) in tegra_qspi_start_rx_dma()
521 rx_dma_phys = tqspi->rx_dma_phys; in tegra_qspi_start_rx_dma()
523 tqspi->rx_dma_desc = dmaengine_prep_slave_single(tqspi->rx_dma_chan, rx_dma_phys, in tegra_qspi_start_rx_dma()
527 if (!tqspi->rx_dma_desc) { in tegra_qspi_start_rx_dma()
528 dev_err(tqspi->dev, "Unable to get RX descriptor\n"); in tegra_qspi_start_rx_dma()
532 tqspi->rx_dma_desc->callback = tegra_qspi_dma_complete; in tegra_qspi_start_rx_dma()
533 tqspi->rx_dma_desc->callback_param = &tqspi->rx_dma_complete; in tegra_qspi_start_rx_dma()
534 dmaengine_submit(tqspi->rx_dma_desc); in tegra_qspi_start_rx_dma()
535 dma_async_issue_pending(tqspi->rx_dma_chan); in tegra_qspi_start_rx_dma()
540 static int tegra_qspi_flush_fifos(struct tegra_qspi *tqspi, bool atomic) in tegra_qspi_flush_fifos() argument
542 void __iomem *addr = tqspi->base + QSPI_FIFO_STATUS; in tegra_qspi_flush_fifos()
545 val = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_flush_fifos()
550 tegra_qspi_writel(tqspi, val, QSPI_FIFO_STATUS); in tegra_qspi_flush_fifos()
562 static void tegra_qspi_unmask_irq(struct tegra_qspi *tqspi) in tegra_qspi_unmask_irq() argument
566 intr_mask = tegra_qspi_readl(tqspi, QSPI_INTR_MASK); in tegra_qspi_unmask_irq()
568 tegra_qspi_writel(tqspi, intr_mask, QSPI_INTR_MASK); in tegra_qspi_unmask_irq()
571 static int tegra_qspi_dma_map_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_dma_map_xfer() argument
573 u8 *tx_buf = (u8 *)t->tx_buf + tqspi->cur_tx_pos; in tegra_qspi_dma_map_xfer()
574 u8 *rx_buf = (u8 *)t->rx_buf + tqspi->cur_rx_pos; in tegra_qspi_dma_map_xfer()
577 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_dma_map_xfer()
580 t->tx_dma = dma_map_single(tqspi->dev, (void *)tx_buf, len, DMA_TO_DEVICE); in tegra_qspi_dma_map_xfer()
581 if (dma_mapping_error(tqspi->dev, t->tx_dma)) in tegra_qspi_dma_map_xfer()
586 t->rx_dma = dma_map_single(tqspi->dev, (void *)rx_buf, len, DMA_FROM_DEVICE); in tegra_qspi_dma_map_xfer()
587 if (dma_mapping_error(tqspi->dev, t->rx_dma)) { in tegra_qspi_dma_map_xfer()
588 dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); in tegra_qspi_dma_map_xfer()
596 static void tegra_qspi_dma_unmap_xfer(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_dma_unmap_xfer() argument
600 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_dma_unmap_xfer()
602 dma_unmap_single(tqspi->dev, t->tx_dma, len, DMA_TO_DEVICE); in tegra_qspi_dma_unmap_xfer()
603 dma_unmap_single(tqspi->dev, t->rx_dma, len, DMA_FROM_DEVICE); in tegra_qspi_dma_unmap_xfer()
606 static int tegra_qspi_start_dma_based_transfer(struct tegra_qspi *tqspi, struct spi_transfer *t) in tegra_qspi_start_dma_based_transfer() argument
614 if (tqspi->is_packed) { in tegra_qspi_start_dma_based_transfer()
615 ret = tegra_qspi_dma_map_xfer(tqspi, t); in tegra_qspi_start_dma_based_transfer()
620 val = QSPI_DMA_BLK_SET(tqspi->curr_dma_words - 1); in tegra_qspi_start_dma_based_transfer()
621 tegra_qspi_writel(tqspi, val, QSPI_DMA_BLK); in tegra_qspi_start_dma_based_transfer()
623 tegra_qspi_unmask_irq(tqspi); in tegra_qspi_start_dma_based_transfer()
625 if (tqspi->is_packed) in tegra_qspi_start_dma_based_transfer()
626 len = DIV_ROUND_UP(tqspi->curr_dma_words * tqspi->bytes_per_word, 4) * 4; in tegra_qspi_start_dma_based_transfer()
628 len = tqspi->curr_dma_words * 4; in tegra_qspi_start_dma_based_transfer()
643 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); in tegra_qspi_start_dma_based_transfer()
644 tqspi->dma_control_reg = val; in tegra_qspi_start_dma_based_transfer()
647 if (tqspi->cur_direction & DATA_DIR_TX) { in tegra_qspi_start_dma_based_transfer()
648 dma_sconfig.dst_addr = tqspi->phys + QSPI_TX_FIFO; in tegra_qspi_start_dma_based_transfer()
651 ret = dmaengine_slave_config(tqspi->tx_dma_chan, &dma_sconfig); in tegra_qspi_start_dma_based_transfer()
653 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
657 tegra_qspi_copy_client_txbuf_to_qspi_txbuf(tqspi, t); in tegra_qspi_start_dma_based_transfer()
658 ret = tegra_qspi_start_tx_dma(tqspi, t, len); in tegra_qspi_start_dma_based_transfer()
660 dev_err(tqspi->dev, "failed to starting TX DMA: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
665 if (tqspi->cur_direction & DATA_DIR_RX) { in tegra_qspi_start_dma_based_transfer()
666 dma_sconfig.src_addr = tqspi->phys + QSPI_RX_FIFO; in tegra_qspi_start_dma_based_transfer()
669 ret = dmaengine_slave_config(tqspi->rx_dma_chan, &dma_sconfig); in tegra_qspi_start_dma_based_transfer()
671 dev_err(tqspi->dev, "failed DMA slave config: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
675 dma_sync_single_for_device(tqspi->dev, tqspi->rx_dma_phys, in tegra_qspi_start_dma_based_transfer()
676 tqspi->dma_buf_size, in tegra_qspi_start_dma_based_transfer()
679 ret = tegra_qspi_start_rx_dma(tqspi, t, len); in tegra_qspi_start_dma_based_transfer()
681 dev_err(tqspi->dev, "failed to start RX DMA: %d\n", ret); in tegra_qspi_start_dma_based_transfer()
682 if (tqspi->cur_direction & DATA_DIR_TX) in tegra_qspi_start_dma_based_transfer()
683 dmaengine_terminate_all(tqspi->tx_dma_chan); in tegra_qspi_start_dma_based_transfer()
688 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_start_dma_based_transfer()
690 tqspi->is_curr_dma_xfer = true; in tegra_qspi_start_dma_based_transfer()
691 tqspi->dma_control_reg = val; in tegra_qspi_start_dma_based_transfer()
693 tegra_qspi_writel(tqspi, val, QSPI_DMA_CTL); in tegra_qspi_start_dma_based_transfer()
721 static void tegra_qspi_deinit_dma(struct tegra_qspi *tqspi) in tegra_qspi_deinit_dma() argument
723 if (!tqspi->soc_data->has_dma) in tegra_qspi_deinit_dma()
726 if (tqspi->tx_dma_buf) { in tegra_qspi_deinit_dma()
727 dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, in tegra_qspi_deinit_dma()
728 tqspi->tx_dma_buf, tqspi->tx_dma_phys); in tegra_qspi_deinit_dma()
729 tqspi->tx_dma_buf = NULL; in tegra_qspi_deinit_dma()
732 if (tqspi->tx_dma_chan) { in tegra_qspi_deinit_dma()
733 dma_release_channel(tqspi->tx_dma_chan); in tegra_qspi_deinit_dma()
734 tqspi->tx_dma_chan = NULL; in tegra_qspi_deinit_dma()
737 if (tqspi->rx_dma_buf) { in tegra_qspi_deinit_dma()
738 dma_free_coherent(tqspi->dev, tqspi->dma_buf_size, in tegra_qspi_deinit_dma()
739 tqspi->rx_dma_buf, tqspi->rx_dma_phys); in tegra_qspi_deinit_dma()
740 tqspi->rx_dma_buf = NULL; in tegra_qspi_deinit_dma()
743 if (tqspi->rx_dma_chan) { in tegra_qspi_deinit_dma()
744 dma_release_channel(tqspi->rx_dma_chan); in tegra_qspi_deinit_dma()
745 tqspi->rx_dma_chan = NULL; in tegra_qspi_deinit_dma()
749 static int tegra_qspi_init_dma(struct tegra_qspi *tqspi) in tegra_qspi_init_dma() argument
756 if (!tqspi->soc_data->has_dma) in tegra_qspi_init_dma()
759 dma_chan = dma_request_chan(tqspi->dev, "rx"); in tegra_qspi_init_dma()
765 tqspi->rx_dma_chan = dma_chan; in tegra_qspi_init_dma()
767 dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); in tegra_qspi_init_dma()
773 tqspi->rx_dma_buf = dma_buf; in tegra_qspi_init_dma()
774 tqspi->rx_dma_phys = dma_phys; in tegra_qspi_init_dma()
776 dma_chan = dma_request_chan(tqspi->dev, "tx"); in tegra_qspi_init_dma()
782 tqspi->tx_dma_chan = dma_chan; in tegra_qspi_init_dma()
784 dma_buf = dma_alloc_coherent(tqspi->dev, tqspi->dma_buf_size, &dma_phys, GFP_KERNEL); in tegra_qspi_init_dma()
790 tqspi->tx_dma_buf = dma_buf; in tegra_qspi_init_dma()
791 tqspi->tx_dma_phys = dma_phys; in tegra_qspi_init_dma()
792 tqspi->use_dma = true; in tegra_qspi_init_dma()
797 tegra_qspi_deinit_dma(tqspi); in tegra_qspi_init_dma()
800 dev_err(tqspi->dev, "cannot use DMA: %d\n", err); in tegra_qspi_init_dma()
801 dev_err(tqspi->dev, "falling back to PIO\n"); in tegra_qspi_init_dma()
811 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_setup_transfer_one() local
818 if (!has_acpi_companion(tqspi->dev) && speed != tqspi->cur_speed) { in tegra_qspi_setup_transfer_one()
819 clk_set_rate(tqspi->clk, speed); in tegra_qspi_setup_transfer_one()
820 tqspi->cur_speed = speed; in tegra_qspi_setup_transfer_one()
823 tqspi->cur_pos = 0; in tegra_qspi_setup_transfer_one()
824 tqspi->cur_rx_pos = 0; in tegra_qspi_setup_transfer_one()
825 tqspi->cur_tx_pos = 0; in tegra_qspi_setup_transfer_one()
826 tqspi->curr_xfer = t; in tegra_qspi_setup_transfer_one()
829 tegra_qspi_mask_clear_irq(tqspi); in tegra_qspi_setup_transfer_one()
831 command1 = tqspi->def_command1_reg; in tegra_qspi_setup_transfer_one()
846 tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1); in tegra_qspi_setup_transfer_one()
855 if (command2 != tqspi->def_command2_reg) in tegra_qspi_setup_transfer_one()
856 tegra_qspi_writel(tqspi, command2, QSPI_COMMAND2); in tegra_qspi_setup_transfer_one()
859 command1 = tqspi->command1_reg; in tegra_qspi_setup_transfer_one()
872 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_start_transfer_one() local
877 total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t); in tegra_qspi_start_transfer_one()
880 if (tqspi->is_packed) in tegra_qspi_start_transfer_one()
882 tegra_qspi_writel(tqspi, command1, QSPI_COMMAND1); in tegra_qspi_start_transfer_one()
884 tqspi->cur_direction = 0; in tegra_qspi_start_transfer_one()
889 tqspi->cur_direction |= DATA_DIR_RX; in tegra_qspi_start_transfer_one()
895 tqspi->cur_direction |= DATA_DIR_TX; in tegra_qspi_start_transfer_one()
908 tqspi->command1_reg = command1; in tegra_qspi_start_transfer_one()
910 tegra_qspi_writel(tqspi, QSPI_NUM_DUMMY_CYCLE(tqspi->dummy_cycles), QSPI_MISC_REG); in tegra_qspi_start_transfer_one()
912 ret = tegra_qspi_flush_fifos(tqspi, false); in tegra_qspi_start_transfer_one()
916 if (tqspi->use_dma && total_fifo_words > QSPI_FIFO_DEPTH) in tegra_qspi_start_transfer_one()
917 ret = tegra_qspi_start_dma_based_transfer(tqspi, t); in tegra_qspi_start_transfer_one()
919 ret = tegra_qspi_start_cpu_based_transfer(tqspi, t); in tegra_qspi_start_transfer_one()
927 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_parse_cdata_dt() local
929 cdata = devm_kzalloc(tqspi->dev, sizeof(*cdata), GFP_KERNEL); in tegra_qspi_parse_cdata_dt()
943 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_setup() local
949 ret = pm_runtime_resume_and_get(tqspi->dev); in tegra_qspi_setup()
951 dev_err(tqspi->dev, "failed to get runtime PM: %d\n", ret); in tegra_qspi_setup()
959 spin_lock_irqsave(&tqspi->lock, flags); in tegra_qspi_setup()
962 val = tqspi->def_command1_reg; in tegra_qspi_setup()
969 tqspi->def_command1_reg = val; in tegra_qspi_setup()
970 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_setup()
972 spin_unlock_irqrestore(&tqspi->lock, flags); in tegra_qspi_setup()
974 pm_runtime_put(tqspi->dev); in tegra_qspi_setup()
979 static void tegra_qspi_dump_regs(struct tegra_qspi *tqspi) in tegra_qspi_dump_regs() argument
981 dev_dbg(tqspi->dev, "============ QSPI REGISTER DUMP ============\n"); in tegra_qspi_dump_regs()
982 dev_dbg(tqspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n", in tegra_qspi_dump_regs()
983 tegra_qspi_readl(tqspi, QSPI_COMMAND1), in tegra_qspi_dump_regs()
984 tegra_qspi_readl(tqspi, QSPI_COMMAND2)); in tegra_qspi_dump_regs()
985 dev_dbg(tqspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n", in tegra_qspi_dump_regs()
986 tegra_qspi_readl(tqspi, QSPI_DMA_CTL), in tegra_qspi_dump_regs()
987 tegra_qspi_readl(tqspi, QSPI_DMA_BLK)); in tegra_qspi_dump_regs()
988 dev_dbg(tqspi->dev, "INTR_MASK: 0x%08x | MISC: 0x%08x\n", in tegra_qspi_dump_regs()
989 tegra_qspi_readl(tqspi, QSPI_INTR_MASK), in tegra_qspi_dump_regs()
990 tegra_qspi_readl(tqspi, QSPI_MISC_REG)); in tegra_qspi_dump_regs()
991 dev_dbg(tqspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", in tegra_qspi_dump_regs()
992 tegra_qspi_readl(tqspi, QSPI_TRANS_STATUS), in tegra_qspi_dump_regs()
993 tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS)); in tegra_qspi_dump_regs()
996 static void tegra_qspi_handle_error(struct tegra_qspi *tqspi) in tegra_qspi_handle_error() argument
998 dev_err(tqspi->dev, "error in transfer, fifo status 0x%08x\n", tqspi->status_reg); in tegra_qspi_handle_error()
999 tegra_qspi_dump_regs(tqspi); in tegra_qspi_handle_error()
1000 tegra_qspi_flush_fifos(tqspi, true); in tegra_qspi_handle_error()
1001 if (device_reset(tqspi->dev) < 0) in tegra_qspi_handle_error()
1002 dev_warn_once(tqspi->dev, "device reset failed\n"); in tegra_qspi_handle_error()
1007 struct tegra_qspi *tqspi = spi_master_get_devdata(spi->master); in tegra_qspi_transfer_end() local
1011 tqspi->command1_reg |= QSPI_CS_SW_VAL; in tegra_qspi_transfer_end()
1013 tqspi->command1_reg &= ~QSPI_CS_SW_VAL; in tegra_qspi_transfer_end()
1014 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_transfer_end()
1015 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_transfer_end()
1053 static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, in tegra_qspi_combined_seq_xfer() argument
1067 val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); in tegra_qspi_combined_seq_xfer()
1069 tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); in tegra_qspi_combined_seq_xfer()
1087 tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD); in tegra_qspi_combined_seq_xfer()
1088 tegra_qspi_writel(tqspi, address_value, in tegra_qspi_combined_seq_xfer()
1091 tegra_qspi_writel(tqspi, cmd_config, in tegra_qspi_combined_seq_xfer()
1093 tegra_qspi_writel(tqspi, addr_config, in tegra_qspi_combined_seq_xfer()
1096 reinit_completion(&tqspi->xfer_completion); in tegra_qspi_combined_seq_xfer()
1103 dev_err(tqspi->dev, "Failed to start transfer-one: %d\n", in tegra_qspi_combined_seq_xfer()
1110 (&tqspi->xfer_completion, in tegra_qspi_combined_seq_xfer()
1114 dev_err(tqspi->dev, "QSPI Transfer failed with timeout: %d\n", in tegra_qspi_combined_seq_xfer()
1116 if (tqspi->is_curr_dma_xfer && in tegra_qspi_combined_seq_xfer()
1117 (tqspi->cur_direction & DATA_DIR_TX)) in tegra_qspi_combined_seq_xfer()
1119 (tqspi->tx_dma_chan); in tegra_qspi_combined_seq_xfer()
1121 if (tqspi->is_curr_dma_xfer && in tegra_qspi_combined_seq_xfer()
1122 (tqspi->cur_direction & DATA_DIR_RX)) in tegra_qspi_combined_seq_xfer()
1124 (tqspi->rx_dma_chan); in tegra_qspi_combined_seq_xfer()
1127 if (!tqspi->is_curr_dma_xfer) { in tegra_qspi_combined_seq_xfer()
1129 (tqspi, in tegra_qspi_combined_seq_xfer()
1133 (tqspi, cmd1, in tegra_qspi_combined_seq_xfer()
1137 (tqspi, in tegra_qspi_combined_seq_xfer()
1140 tegra_qspi_writel(tqspi, dma_ctl, in tegra_qspi_combined_seq_xfer()
1145 if (device_reset(tqspi->dev) < 0) in tegra_qspi_combined_seq_xfer()
1146 dev_warn_once(tqspi->dev, in tegra_qspi_combined_seq_xfer()
1152 if (tqspi->tx_status || tqspi->rx_status) { in tegra_qspi_combined_seq_xfer()
1153 dev_err(tqspi->dev, "QSPI Transfer failed\n"); in tegra_qspi_combined_seq_xfer()
1154 tqspi->tx_status = 0; in tegra_qspi_combined_seq_xfer()
1155 tqspi->rx_status = 0; in tegra_qspi_combined_seq_xfer()
1179 static int tegra_qspi_non_combined_seq_xfer(struct tegra_qspi *tqspi, in tegra_qspi_non_combined_seq_xfer() argument
1189 tqspi->tx_status = 0; in tegra_qspi_non_combined_seq_xfer()
1190 tqspi->rx_status = 0; in tegra_qspi_non_combined_seq_xfer()
1193 val = tegra_qspi_readl(tqspi, QSPI_GLOBAL_CONFIG); in tegra_qspi_non_combined_seq_xfer()
1195 tegra_qspi_writel(tqspi, val, QSPI_GLOBAL_CONFIG); in tegra_qspi_non_combined_seq_xfer()
1201 tqspi->dummy_cycles = 0; in tegra_qspi_non_combined_seq_xfer()
1216 tqspi->dummy_cycles = dummy_cycles; in tegra_qspi_non_combined_seq_xfer()
1223 reinit_completion(&tqspi->xfer_completion); in tegra_qspi_non_combined_seq_xfer()
1229 dev_err(tqspi->dev, "failed to start transfer: %d\n", ret); in tegra_qspi_non_combined_seq_xfer()
1233 ret = wait_for_completion_timeout(&tqspi->xfer_completion, in tegra_qspi_non_combined_seq_xfer()
1236 dev_err(tqspi->dev, "transfer timeout\n"); in tegra_qspi_non_combined_seq_xfer()
1237 if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_TX)) in tegra_qspi_non_combined_seq_xfer()
1238 dmaengine_terminate_all(tqspi->tx_dma_chan); in tegra_qspi_non_combined_seq_xfer()
1239 if (tqspi->is_curr_dma_xfer && (tqspi->cur_direction & DATA_DIR_RX)) in tegra_qspi_non_combined_seq_xfer()
1240 dmaengine_terminate_all(tqspi->rx_dma_chan); in tegra_qspi_non_combined_seq_xfer()
1241 tegra_qspi_handle_error(tqspi); in tegra_qspi_non_combined_seq_xfer()
1246 if (tqspi->tx_status || tqspi->rx_status) { in tegra_qspi_non_combined_seq_xfer()
1247 tegra_qspi_handle_error(tqspi); in tegra_qspi_non_combined_seq_xfer()
1281 static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, in tegra_qspi_validate_cmb_seq() argument
1290 if (!tqspi->soc_data->cmb_xfer_capable || transfer_count != 3) in tegra_qspi_validate_cmb_seq()
1300 if (!tqspi->soc_data->has_dma || xfer->len > (QSPI_FIFO_DEPTH << 2)) in tegra_qspi_validate_cmb_seq()
1309 struct tegra_qspi *tqspi = spi_master_get_devdata(master); in tegra_qspi_transfer_one_message() local
1312 if (tegra_qspi_validate_cmb_seq(tqspi, msg)) in tegra_qspi_transfer_one_message()
1313 ret = tegra_qspi_combined_seq_xfer(tqspi, msg); in tegra_qspi_transfer_one_message()
1315 ret = tegra_qspi_non_combined_seq_xfer(tqspi, msg); in tegra_qspi_transfer_one_message()
1322 static irqreturn_t handle_cpu_based_xfer(struct tegra_qspi *tqspi) in handle_cpu_based_xfer() argument
1324 struct spi_transfer *t = tqspi->curr_xfer; in handle_cpu_based_xfer()
1327 spin_lock_irqsave(&tqspi->lock, flags); in handle_cpu_based_xfer()
1329 if (tqspi->tx_status || tqspi->rx_status) { in handle_cpu_based_xfer()
1330 tegra_qspi_handle_error(tqspi); in handle_cpu_based_xfer()
1331 complete(&tqspi->xfer_completion); in handle_cpu_based_xfer()
1335 if (tqspi->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
1336 tegra_qspi_read_rx_fifo_to_client_rxbuf(tqspi, t); in handle_cpu_based_xfer()
1338 if (tqspi->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
1339 tqspi->cur_pos = tqspi->cur_tx_pos; in handle_cpu_based_xfer()
1341 tqspi->cur_pos = tqspi->cur_rx_pos; in handle_cpu_based_xfer()
1343 if (tqspi->cur_pos == t->len) { in handle_cpu_based_xfer()
1344 complete(&tqspi->xfer_completion); in handle_cpu_based_xfer()
1348 tegra_qspi_calculate_curr_xfer_param(tqspi, t); in handle_cpu_based_xfer()
1349 tegra_qspi_start_cpu_based_transfer(tqspi, t); in handle_cpu_based_xfer()
1351 spin_unlock_irqrestore(&tqspi->lock, flags); in handle_cpu_based_xfer()
1355 static irqreturn_t handle_dma_based_xfer(struct tegra_qspi *tqspi) in handle_dma_based_xfer() argument
1357 struct spi_transfer *t = tqspi->curr_xfer; in handle_dma_based_xfer()
1363 if (tqspi->cur_direction & DATA_DIR_TX) { in handle_dma_based_xfer()
1364 if (tqspi->tx_status) { in handle_dma_based_xfer()
1365 dmaengine_terminate_all(tqspi->tx_dma_chan); in handle_dma_based_xfer()
1369 &tqspi->tx_dma_complete, QSPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1371 dmaengine_terminate_all(tqspi->tx_dma_chan); in handle_dma_based_xfer()
1372 dev_err(tqspi->dev, "failed TX DMA transfer\n"); in handle_dma_based_xfer()
1378 if (tqspi->cur_direction & DATA_DIR_RX) { in handle_dma_based_xfer()
1379 if (tqspi->rx_status) { in handle_dma_based_xfer()
1380 dmaengine_terminate_all(tqspi->rx_dma_chan); in handle_dma_based_xfer()
1384 &tqspi->rx_dma_complete, QSPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1386 dmaengine_terminate_all(tqspi->rx_dma_chan); in handle_dma_based_xfer()
1387 dev_err(tqspi->dev, "failed RX DMA transfer\n"); in handle_dma_based_xfer()
1393 spin_lock_irqsave(&tqspi->lock, flags); in handle_dma_based_xfer()
1396 tegra_qspi_dma_unmap_xfer(tqspi, t); in handle_dma_based_xfer()
1397 tegra_qspi_handle_error(tqspi); in handle_dma_based_xfer()
1398 complete(&tqspi->xfer_completion); in handle_dma_based_xfer()
1402 if (tqspi->cur_direction & DATA_DIR_RX) in handle_dma_based_xfer()
1403 tegra_qspi_copy_qspi_rxbuf_to_client_rxbuf(tqspi, t); in handle_dma_based_xfer()
1405 if (tqspi->cur_direction & DATA_DIR_TX) in handle_dma_based_xfer()
1406 tqspi->cur_pos = tqspi->cur_tx_pos; in handle_dma_based_xfer()
1408 tqspi->cur_pos = tqspi->cur_rx_pos; in handle_dma_based_xfer()
1410 if (tqspi->cur_pos == t->len) { in handle_dma_based_xfer()
1411 tegra_qspi_dma_unmap_xfer(tqspi, t); in handle_dma_based_xfer()
1412 complete(&tqspi->xfer_completion); in handle_dma_based_xfer()
1416 tegra_qspi_dma_unmap_xfer(tqspi, t); in handle_dma_based_xfer()
1419 total_fifo_words = tegra_qspi_calculate_curr_xfer_param(tqspi, t); in handle_dma_based_xfer()
1421 err = tegra_qspi_start_dma_based_transfer(tqspi, t); in handle_dma_based_xfer()
1423 err = tegra_qspi_start_cpu_based_transfer(tqspi, t); in handle_dma_based_xfer()
1426 spin_unlock_irqrestore(&tqspi->lock, flags); in handle_dma_based_xfer()
1432 struct tegra_qspi *tqspi = context_data; in tegra_qspi_isr_thread() local
1434 tqspi->status_reg = tegra_qspi_readl(tqspi, QSPI_FIFO_STATUS); in tegra_qspi_isr_thread()
1436 if (tqspi->cur_direction & DATA_DIR_TX) in tegra_qspi_isr_thread()
1437 tqspi->tx_status = tqspi->status_reg & (QSPI_TX_FIFO_UNF | QSPI_TX_FIFO_OVF); in tegra_qspi_isr_thread()
1439 if (tqspi->cur_direction & DATA_DIR_RX) in tegra_qspi_isr_thread()
1440 tqspi->rx_status = tqspi->status_reg & (QSPI_RX_FIFO_OVF | QSPI_RX_FIFO_UNF); in tegra_qspi_isr_thread()
1442 tegra_qspi_mask_clear_irq(tqspi); in tegra_qspi_isr_thread()
1444 if (!tqspi->is_curr_dma_xfer) in tegra_qspi_isr_thread()
1445 return handle_cpu_based_xfer(tqspi); in tegra_qspi_isr_thread()
1447 return handle_dma_based_xfer(tqspi); in tegra_qspi_isr_thread()
1520 struct tegra_qspi *tqspi; in tegra_qspi_probe() local
1525 master = devm_spi_alloc_master(&pdev->dev, sizeof(*tqspi)); in tegra_qspi_probe()
1530 tqspi = spi_master_get_devdata(master); in tegra_qspi_probe()
1544 tqspi->master = master; in tegra_qspi_probe()
1545 tqspi->dev = &pdev->dev; in tegra_qspi_probe()
1546 spin_lock_init(&tqspi->lock); in tegra_qspi_probe()
1548 tqspi->soc_data = device_get_match_data(&pdev->dev); in tegra_qspi_probe()
1549 master->num_chipselect = tqspi->soc_data->cs_count; in tegra_qspi_probe()
1551 tqspi->base = devm_ioremap_resource(&pdev->dev, r); in tegra_qspi_probe()
1552 if (IS_ERR(tqspi->base)) in tegra_qspi_probe()
1553 return PTR_ERR(tqspi->base); in tegra_qspi_probe()
1555 tqspi->phys = r->start; in tegra_qspi_probe()
1559 tqspi->irq = qspi_irq; in tegra_qspi_probe()
1561 if (!has_acpi_companion(tqspi->dev)) { in tegra_qspi_probe()
1562 tqspi->clk = devm_clk_get(&pdev->dev, "qspi"); in tegra_qspi_probe()
1563 if (IS_ERR(tqspi->clk)) { in tegra_qspi_probe()
1564 ret = PTR_ERR(tqspi->clk); in tegra_qspi_probe()
1571 tqspi->max_buf_size = QSPI_FIFO_DEPTH << 2; in tegra_qspi_probe()
1572 tqspi->dma_buf_size = DEFAULT_QSPI_DMA_BUF_LEN; in tegra_qspi_probe()
1574 ret = tegra_qspi_init_dma(tqspi); in tegra_qspi_probe()
1578 if (tqspi->use_dma) in tegra_qspi_probe()
1579 tqspi->max_buf_size = tqspi->dma_buf_size; in tegra_qspi_probe()
1581 init_completion(&tqspi->tx_dma_complete); in tegra_qspi_probe()
1582 init_completion(&tqspi->rx_dma_complete); in tegra_qspi_probe()
1583 init_completion(&tqspi->xfer_completion); in tegra_qspi_probe()
1592 if (device_reset(tqspi->dev) < 0) in tegra_qspi_probe()
1593 dev_warn_once(tqspi->dev, "device reset failed\n"); in tegra_qspi_probe()
1595 tqspi->def_command1_reg = QSPI_M_S | QSPI_CS_SW_HW | QSPI_CS_SW_VAL; in tegra_qspi_probe()
1596 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); in tegra_qspi_probe()
1597 tqspi->spi_cs_timing1 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING1); in tegra_qspi_probe()
1598 tqspi->spi_cs_timing2 = tegra_qspi_readl(tqspi, QSPI_CS_TIMING2); in tegra_qspi_probe()
1599 tqspi->def_command2_reg = tegra_qspi_readl(tqspi, QSPI_COMMAND2); in tegra_qspi_probe()
1603 ret = request_threaded_irq(tqspi->irq, NULL, in tegra_qspi_probe()
1605 dev_name(&pdev->dev), tqspi); in tegra_qspi_probe()
1607 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", tqspi->irq, ret); in tegra_qspi_probe()
1621 free_irq(qspi_irq, tqspi); in tegra_qspi_probe()
1624 tegra_qspi_deinit_dma(tqspi); in tegra_qspi_probe()
1631 struct tegra_qspi *tqspi = spi_master_get_devdata(master); in tegra_qspi_remove() local
1634 free_irq(tqspi->irq, tqspi); in tegra_qspi_remove()
1636 tegra_qspi_deinit_dma(tqspi); in tegra_qspi_remove()
1651 struct tegra_qspi *tqspi = spi_master_get_devdata(master); in tegra_qspi_resume() local
1660 tegra_qspi_writel(tqspi, tqspi->command1_reg, QSPI_COMMAND1); in tegra_qspi_resume()
1661 tegra_qspi_writel(tqspi, tqspi->def_command2_reg, QSPI_COMMAND2); in tegra_qspi_resume()
1670 struct tegra_qspi *tqspi = spi_master_get_devdata(master); in tegra_qspi_runtime_suspend() local
1673 if (has_acpi_companion(tqspi->dev)) in tegra_qspi_runtime_suspend()
1676 tegra_qspi_readl(tqspi, QSPI_COMMAND1); in tegra_qspi_runtime_suspend()
1678 clk_disable_unprepare(tqspi->clk); in tegra_qspi_runtime_suspend()
1686 struct tegra_qspi *tqspi = spi_master_get_devdata(master); in tegra_qspi_runtime_resume() local
1690 if (has_acpi_companion(tqspi->dev)) in tegra_qspi_runtime_resume()
1692 ret = clk_prepare_enable(tqspi->clk); in tegra_qspi_runtime_resume()
1694 dev_err(tqspi->dev, "failed to enable clock: %d\n", ret); in tegra_qspi_runtime_resume()