Lines Matching +full:rx +full:- +full:clk +full:- +full:tap +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk.h>
10 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
171 struct clk *clk; member
230 return readl(tspi->base + reg); in tegra_spi_readl()
236 writel(val, tspi->base + reg); in tegra_spi_writel()
240 readl(tspi->base + SPI_COMMAND1); in tegra_spi_writel()
262 unsigned remain_len = t->len - tspi->cur_pos; in tegra_spi_calculate_curr_xfer_param()
264 unsigned bits_per_word = t->bits_per_word; in tegra_spi_calculate_curr_xfer_param()
268 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); in tegra_spi_calculate_curr_xfer_param()
271 bits_per_word == 32) && t->len > 3) { in tegra_spi_calculate_curr_xfer_param()
272 tspi->is_packed = true; in tegra_spi_calculate_curr_xfer_param()
273 tspi->words_per_32bit = 32/bits_per_word; in tegra_spi_calculate_curr_xfer_param()
275 tspi->is_packed = false; in tegra_spi_calculate_curr_xfer_param()
276 tspi->words_per_32bit = 1; in tegra_spi_calculate_curr_xfer_param()
279 if (tspi->is_packed) { in tegra_spi_calculate_curr_xfer_param()
280 max_len = min(remain_len, tspi->max_buf_size); in tegra_spi_calculate_curr_xfer_param()
281 tspi->curr_dma_words = max_len/tspi->bytes_per_word; in tegra_spi_calculate_curr_xfer_param()
284 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; in tegra_spi_calculate_curr_xfer_param()
285 max_word = min(max_word, tspi->max_buf_size/4); in tegra_spi_calculate_curr_xfer_param()
286 tspi->curr_dma_words = max_word; in tegra_spi_calculate_curr_xfer_param()
302 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_spi_fill_tx_fifo_from_client_txbuf()
307 if (tspi->is_packed) { in tegra_spi_fill_tx_fifo_from_client_txbuf()
308 fifo_words_left = tx_empty_count * tspi->words_per_32bit; in tegra_spi_fill_tx_fifo_from_client_txbuf()
309 written_words = min(fifo_words_left, tspi->curr_dma_words); in tegra_spi_fill_tx_fifo_from_client_txbuf()
310 nbytes = written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
315 for (i = 0; (i < 4) && nbytes; i++, nbytes--) in tegra_spi_fill_tx_fifo_from_client_txbuf()
320 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
323 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); in tegra_spi_fill_tx_fifo_from_client_txbuf()
325 nbytes = written_words * tspi->bytes_per_word; in tegra_spi_fill_tx_fifo_from_client_txbuf()
326 if (nbytes > t->len - tspi->cur_pos) in tegra_spi_fill_tx_fifo_from_client_txbuf()
327 nbytes = t->len - tspi->cur_pos; in tegra_spi_fill_tx_fifo_from_client_txbuf()
332 for (i = 0; nbytes && (i < tspi->bytes_per_word); in tegra_spi_fill_tx_fifo_from_client_txbuf()
333 i++, nbytes--) in tegra_spi_fill_tx_fifo_from_client_txbuf()
338 tspi->cur_tx_pos += write_bytes; in tegra_spi_fill_tx_fifo_from_client_txbuf()
352 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; in tegra_spi_read_rx_fifo_to_client_rxbuf()
356 if (tspi->is_packed) { in tegra_spi_read_rx_fifo_to_client_rxbuf()
357 len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
361 for (i = 0; len && (i < 4); i++, len--) in tegra_spi_read_rx_fifo_to_client_rxbuf()
364 read_words += tspi->curr_dma_words; in tegra_spi_read_rx_fifo_to_client_rxbuf()
365 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
367 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; in tegra_spi_read_rx_fifo_to_client_rxbuf()
368 u8 bytes_per_word = tspi->bytes_per_word; in tegra_spi_read_rx_fifo_to_client_rxbuf()
372 if (len > t->len - tspi->cur_pos) in tegra_spi_read_rx_fifo_to_client_rxbuf()
373 len = t->len - tspi->cur_pos; in tegra_spi_read_rx_fifo_to_client_rxbuf()
378 for (i = 0; len && (i < bytes_per_word); i++, len--) in tegra_spi_read_rx_fifo_to_client_rxbuf()
382 tspi->cur_rx_pos += read_bytes; in tegra_spi_read_rx_fifo_to_client_rxbuf()
392 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, in tegra_spi_copy_client_txbuf_to_spi_txbuf()
393 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
395 if (tspi->is_packed) { in tegra_spi_copy_client_txbuf_to_spi_txbuf()
396 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
398 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
399 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
403 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
404 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
407 if (consume > t->len - tspi->cur_pos) in tegra_spi_copy_client_txbuf_to_spi_txbuf()
408 consume = t->len - tspi->cur_pos; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
410 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_spi_copy_client_txbuf_to_spi_txbuf()
413 for (i = 0; consume && (i < tspi->bytes_per_word); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
414 i++, consume--) in tegra_spi_copy_client_txbuf_to_spi_txbuf()
416 tspi->tx_dma_buf[count] = x; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
419 tspi->cur_tx_pos += write_bytes; in tegra_spi_copy_client_txbuf_to_spi_txbuf()
423 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, in tegra_spi_copy_client_txbuf_to_spi_txbuf()
424 tspi->dma_buf_size, DMA_TO_DEVICE); in tegra_spi_copy_client_txbuf_to_spi_txbuf()
431 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
432 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
434 if (tspi->is_packed) { in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
435 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
437 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
438 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
442 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
443 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
444 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
447 if (consume > t->len - tspi->cur_pos) in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
448 consume = t->len - tspi->cur_pos; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
450 for (count = 0; count < tspi->curr_dma_words; count++) { in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
451 u32 x = tspi->rx_dma_buf[count] & rx_mask; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
453 for (i = 0; consume && (i < tspi->bytes_per_word); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
454 i++, consume--) in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
458 tspi->cur_rx_pos += read_bytes; in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
462 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
463 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_copy_spi_rxbuf_to_client_rxbuf()
475 reinit_completion(&tspi->tx_dma_complete); in tegra_spi_start_tx_dma()
476 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, in tegra_spi_start_tx_dma()
477 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, in tegra_spi_start_tx_dma()
479 if (!tspi->tx_dma_desc) { in tegra_spi_start_tx_dma()
480 dev_err(tspi->dev, "Not able to get desc for Tx\n"); in tegra_spi_start_tx_dma()
481 return -EIO; in tegra_spi_start_tx_dma()
484 tspi->tx_dma_desc->callback = tegra_spi_dma_complete; in tegra_spi_start_tx_dma()
485 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; in tegra_spi_start_tx_dma()
487 dmaengine_submit(tspi->tx_dma_desc); in tegra_spi_start_tx_dma()
488 dma_async_issue_pending(tspi->tx_dma_chan); in tegra_spi_start_tx_dma()
494 reinit_completion(&tspi->rx_dma_complete); in tegra_spi_start_rx_dma()
495 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, in tegra_spi_start_rx_dma()
496 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, in tegra_spi_start_rx_dma()
498 if (!tspi->rx_dma_desc) { in tegra_spi_start_rx_dma()
499 dev_err(tspi->dev, "Not able to get desc for Rx\n"); in tegra_spi_start_rx_dma()
500 return -EIO; in tegra_spi_start_rx_dma()
503 tspi->rx_dma_desc->callback = tegra_spi_dma_complete; in tegra_spi_start_rx_dma()
504 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; in tegra_spi_start_rx_dma()
506 dmaengine_submit(tspi->rx_dma_desc); in tegra_spi_start_rx_dma()
507 dma_async_issue_pending(tspi->rx_dma_chan); in tegra_spi_start_rx_dma()
523 dev_err(tspi->dev, in tegra_spi_flush_fifos()
525 return -EIO; in tegra_spi_flush_fifos()
544 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1); in tegra_spi_start_dma_based_transfer()
547 if (tspi->is_packed) in tegra_spi_start_dma_based_transfer()
548 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, in tegra_spi_start_dma_based_transfer()
551 len = tspi->curr_dma_words * 4; in tegra_spi_start_dma_based_transfer()
565 if (!tspi->soc_data->has_intr_mask_reg) { in tegra_spi_start_dma_based_transfer()
566 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_dma_based_transfer()
569 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_start_dma_based_transfer()
574 tspi->dma_control_reg = val; in tegra_spi_start_dma_based_transfer()
577 if (tspi->cur_direction & DATA_DIR_TX) { in tegra_spi_start_dma_based_transfer()
578 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO; in tegra_spi_start_dma_based_transfer()
581 ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig); in tegra_spi_start_dma_based_transfer()
583 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
591 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
597 if (tspi->cur_direction & DATA_DIR_RX) { in tegra_spi_start_dma_based_transfer()
598 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO; in tegra_spi_start_dma_based_transfer()
601 ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig); in tegra_spi_start_dma_based_transfer()
603 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
609 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, in tegra_spi_start_dma_based_transfer()
610 tspi->dma_buf_size, DMA_FROM_DEVICE); in tegra_spi_start_dma_based_transfer()
614 dev_err(tspi->dev, in tegra_spi_start_dma_based_transfer()
615 "Starting rx dma failed, err %d\n", ret); in tegra_spi_start_dma_based_transfer()
616 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_dma_based_transfer()
617 dmaengine_terminate_all(tspi->tx_dma_chan); in tegra_spi_start_dma_based_transfer()
621 tspi->is_curr_dma_xfer = true; in tegra_spi_start_dma_based_transfer()
622 tspi->dma_control_reg = val; in tegra_spi_start_dma_based_transfer()
635 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_cpu_based_transfer()
638 cur_words = tspi->curr_dma_words; in tegra_spi_start_cpu_based_transfer()
640 val = SPI_DMA_BLK_SET(cur_words - 1); in tegra_spi_start_cpu_based_transfer()
644 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_start_cpu_based_transfer()
647 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_start_cpu_based_transfer()
651 tspi->dma_control_reg = val; in tegra_spi_start_cpu_based_transfer()
653 tspi->is_curr_dma_xfer = false; in tegra_spi_start_cpu_based_transfer()
655 val = tspi->command1_reg; in tegra_spi_start_cpu_based_transfer()
668 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); in tegra_spi_init_dma_param()
670 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), in tegra_spi_init_dma_param()
673 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, in tegra_spi_init_dma_param()
676 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); in tegra_spi_init_dma_param()
678 return -ENOMEM; in tegra_spi_init_dma_param()
682 tspi->rx_dma_chan = dma_chan; in tegra_spi_init_dma_param()
683 tspi->rx_dma_buf = dma_buf; in tegra_spi_init_dma_param()
684 tspi->rx_dma_phys = dma_phys; in tegra_spi_init_dma_param()
686 tspi->tx_dma_chan = dma_chan; in tegra_spi_init_dma_param()
687 tspi->tx_dma_buf = dma_buf; in tegra_spi_init_dma_param()
688 tspi->tx_dma_phys = dma_phys; in tegra_spi_init_dma_param()
701 dma_buf = tspi->rx_dma_buf; in tegra_spi_deinit_dma_param()
702 dma_chan = tspi->rx_dma_chan; in tegra_spi_deinit_dma_param()
703 dma_phys = tspi->rx_dma_phys; in tegra_spi_deinit_dma_param()
704 tspi->rx_dma_chan = NULL; in tegra_spi_deinit_dma_param()
705 tspi->rx_dma_buf = NULL; in tegra_spi_deinit_dma_param()
707 dma_buf = tspi->tx_dma_buf; in tegra_spi_deinit_dma_param()
708 dma_chan = tspi->tx_dma_chan; in tegra_spi_deinit_dma_param()
709 dma_phys = tspi->tx_dma_phys; in tegra_spi_deinit_dma_param()
710 tspi->tx_dma_buf = NULL; in tegra_spi_deinit_dma_param()
711 tspi->tx_dma_chan = NULL; in tegra_spi_deinit_dma_param()
716 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); in tegra_spi_deinit_dma_param()
722 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_set_hw_cs_timing()
723 struct spi_delay *setup = &spi->cs_setup; in tegra_spi_set_hw_cs_timing()
724 struct spi_delay *hold = &spi->cs_hold; in tegra_spi_set_hw_cs_timing()
725 struct spi_delay *inactive = &spi->cs_inactive; in tegra_spi_set_hw_cs_timing()
732 if ((setup && setup->unit != SPI_DELAY_UNIT_SCK) || in tegra_spi_set_hw_cs_timing()
733 (hold && hold->unit != SPI_DELAY_UNIT_SCK) || in tegra_spi_set_hw_cs_timing()
734 (inactive && inactive->unit != SPI_DELAY_UNIT_SCK)) { in tegra_spi_set_hw_cs_timing()
735 dev_err(&spi->dev, in tegra_spi_set_hw_cs_timing()
736 "Invalid delay unit %d, should be SPI_DELAY_UNIT_SCK\n", in tegra_spi_set_hw_cs_timing()
738 return -EINVAL; in tegra_spi_set_hw_cs_timing()
741 setup_dly = setup ? setup->value : 0; in tegra_spi_set_hw_cs_timing()
742 hold_dly = hold ? hold->value : 0; in tegra_spi_set_hw_cs_timing()
743 inactive_dly = inactive ? inactive->value : 0; in tegra_spi_set_hw_cs_timing()
748 setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1); in tegra_spi_set_hw_cs_timing()
749 spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1, in tegra_spi_set_hw_cs_timing()
750 spi->chip_select, in tegra_spi_set_hw_cs_timing()
752 if (tspi->spi_cs_timing1 != spi_cs_timing) { in tegra_spi_set_hw_cs_timing()
753 tspi->spi_cs_timing1 = spi_cs_timing; in tegra_spi_set_hw_cs_timing()
760 inactive_cycles--; in tegra_spi_set_hw_cs_timing()
762 spi_cs_timing = tspi->spi_cs_timing2; in tegra_spi_set_hw_cs_timing()
763 SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select, in tegra_spi_set_hw_cs_timing()
765 SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select, in tegra_spi_set_hw_cs_timing()
767 if (tspi->spi_cs_timing2 != spi_cs_timing) { in tegra_spi_set_hw_cs_timing()
768 tspi->spi_cs_timing2 = spi_cs_timing; in tegra_spi_set_hw_cs_timing()
780 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_setup_transfer_one()
781 struct tegra_spi_client_data *cdata = spi->controller_data; in tegra_spi_setup_transfer_one()
782 u32 speed = t->speed_hz; in tegra_spi_setup_transfer_one()
783 u8 bits_per_word = t->bits_per_word; in tegra_spi_setup_transfer_one()
788 if (speed != tspi->cur_speed) { in tegra_spi_setup_transfer_one()
789 clk_set_rate(tspi->clk, speed); in tegra_spi_setup_transfer_one()
790 tspi->cur_speed = speed; in tegra_spi_setup_transfer_one()
793 tspi->cur_spi = spi; in tegra_spi_setup_transfer_one()
794 tspi->cur_pos = 0; in tegra_spi_setup_transfer_one()
795 tspi->cur_rx_pos = 0; in tegra_spi_setup_transfer_one()
796 tspi->cur_tx_pos = 0; in tegra_spi_setup_transfer_one()
797 tspi->curr_xfer = t; in tegra_spi_setup_transfer_one()
802 command1 = tspi->def_command1_reg; in tegra_spi_setup_transfer_one()
803 command1 |= SPI_BIT_LENGTH(bits_per_word - 1); in tegra_spi_setup_transfer_one()
806 req_mode = spi->mode & 0x3; in tegra_spi_setup_transfer_one()
816 if (spi->mode & SPI_LSB_FIRST) in tegra_spi_setup_transfer_one()
821 if (spi->mode & SPI_3WIRE) in tegra_spi_setup_transfer_one()
826 if (tspi->cs_control) { in tegra_spi_setup_transfer_one()
827 if (tspi->cs_control != spi) in tegra_spi_setup_transfer_one()
829 tspi->cs_control = NULL; in tegra_spi_setup_transfer_one()
834 if (spi->cs_gpiod) in tegra_spi_setup_transfer_one()
835 gpiod_set_value(spi->cs_gpiod, 1); in tegra_spi_setup_transfer_one()
837 if (is_single_xfer && !(t->cs_change)) { in tegra_spi_setup_transfer_one()
838 tspi->use_hw_based_cs = true; in tegra_spi_setup_transfer_one()
841 tspi->use_hw_based_cs = false; in tegra_spi_setup_transfer_one()
843 if (spi->mode & SPI_CS_HIGH) in tegra_spi_setup_transfer_one()
849 if (tspi->last_used_cs != spi->chip_select) { in tegra_spi_setup_transfer_one()
850 if (cdata && cdata->tx_clk_tap_delay) in tegra_spi_setup_transfer_one()
851 tx_tap = cdata->tx_clk_tap_delay; in tegra_spi_setup_transfer_one()
852 if (cdata && cdata->rx_clk_tap_delay) in tegra_spi_setup_transfer_one()
853 rx_tap = cdata->rx_clk_tap_delay; in tegra_spi_setup_transfer_one()
856 if (command2 != tspi->def_command2_reg) in tegra_spi_setup_transfer_one()
858 tspi->last_used_cs = spi->chip_select; in tegra_spi_setup_transfer_one()
862 command1 = tspi->command1_reg; in tegra_spi_setup_transfer_one()
864 command1 |= SPI_BIT_LENGTH(bits_per_word - 1); in tegra_spi_setup_transfer_one()
873 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_start_transfer_one()
879 if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL) in tegra_spi_start_transfer_one()
884 if (tspi->is_packed) in tegra_spi_start_transfer_one()
890 tspi->cur_direction = 0; in tegra_spi_start_transfer_one()
891 if (t->rx_buf) { in tegra_spi_start_transfer_one()
893 tspi->cur_direction |= DATA_DIR_RX; in tegra_spi_start_transfer_one()
895 if (t->tx_buf) { in tegra_spi_start_transfer_one()
897 tspi->cur_direction |= DATA_DIR_TX; in tegra_spi_start_transfer_one()
899 command1 |= SPI_CS_SEL(spi->chip_select); in tegra_spi_start_transfer_one()
901 tspi->command1_reg = command1; in tegra_spi_start_transfer_one()
903 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n", in tegra_spi_start_transfer_one()
904 tspi->def_command1_reg, (unsigned)command1); in tegra_spi_start_transfer_one()
922 slave_np = spi->dev.of_node; in tegra_spi_parse_cdata_dt()
924 dev_dbg(&spi->dev, "device node not found\n"); in tegra_spi_parse_cdata_dt()
932 of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay", in tegra_spi_parse_cdata_dt()
933 &cdata->tx_clk_tap_delay); in tegra_spi_parse_cdata_dt()
934 of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay", in tegra_spi_parse_cdata_dt()
935 &cdata->rx_clk_tap_delay); in tegra_spi_parse_cdata_dt()
941 struct tegra_spi_client_data *cdata = spi->controller_data; in tegra_spi_cleanup()
943 spi->controller_data = NULL; in tegra_spi_cleanup()
944 if (spi->dev.of_node) in tegra_spi_cleanup()
950 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_setup()
951 struct tegra_spi_client_data *cdata = spi->controller_data; in tegra_spi_setup()
956 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", in tegra_spi_setup()
957 spi->bits_per_word, in tegra_spi_setup()
958 spi->mode & SPI_CPOL ? "" : "~", in tegra_spi_setup()
959 spi->mode & SPI_CPHA ? "" : "~", in tegra_spi_setup()
960 spi->max_speed_hz); in tegra_spi_setup()
964 spi->controller_data = cdata; in tegra_spi_setup()
967 ret = pm_runtime_resume_and_get(tspi->dev); in tegra_spi_setup()
969 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); in tegra_spi_setup()
975 if (tspi->soc_data->has_intr_mask_reg) { in tegra_spi_setup()
981 spin_lock_irqsave(&tspi->lock, flags); in tegra_spi_setup()
983 if (spi->cs_gpiod) in tegra_spi_setup()
984 gpiod_set_value(spi->cs_gpiod, 0); in tegra_spi_setup()
986 val = tspi->def_command1_reg; in tegra_spi_setup()
987 if (spi->mode & SPI_CS_HIGH) in tegra_spi_setup()
988 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select); in tegra_spi_setup()
990 val |= SPI_CS_POL_INACTIVE(spi->chip_select); in tegra_spi_setup()
991 tspi->def_command1_reg = val; in tegra_spi_setup()
992 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_setup()
993 spin_unlock_irqrestore(&tspi->lock, flags); in tegra_spi_setup()
995 pm_runtime_put(tspi->dev); in tegra_spi_setup()
1001 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); in tegra_spi_transfer_end()
1002 int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1; in tegra_spi_transfer_end()
1005 if (spi->cs_gpiod) in tegra_spi_transfer_end()
1006 gpiod_set_value(spi->cs_gpiod, 0); in tegra_spi_transfer_end()
1008 if (!tspi->use_hw_based_cs) { in tegra_spi_transfer_end()
1010 tspi->command1_reg |= SPI_CS_SW_VAL; in tegra_spi_transfer_end()
1012 tspi->command1_reg &= ~SPI_CS_SW_VAL; in tegra_spi_transfer_end()
1013 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); in tegra_spi_transfer_end()
1016 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_transfer_end()
1021 dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n"); in tegra_spi_dump_regs()
1022 dev_dbg(tspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n", in tegra_spi_dump_regs()
1025 dev_dbg(tspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n", in tegra_spi_dump_regs()
1028 dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", in tegra_spi_dump_regs()
1039 struct spi_device *spi = msg->spi; in tegra_spi_transfer_one_message()
1044 msg->status = 0; in tegra_spi_transfer_one_message()
1045 msg->actual_length = 0; in tegra_spi_transfer_one_message()
1047 single_xfer = list_is_singular(&msg->transfers); in tegra_spi_transfer_one_message()
1048 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in tegra_spi_transfer_one_message()
1051 reinit_completion(&tspi->xfer_completion); in tegra_spi_transfer_one_message()
1056 if (!xfer->len) { in tegra_spi_transfer_one_message()
1064 dev_err(tspi->dev, in tegra_spi_transfer_one_message()
1070 ret = wait_for_completion_timeout(&tspi->xfer_completion, in tegra_spi_transfer_one_message()
1073 dev_err(tspi->dev, "spi transfer timeout\n"); in tegra_spi_transfer_one_message()
1074 if (tspi->is_curr_dma_xfer && in tegra_spi_transfer_one_message()
1075 (tspi->cur_direction & DATA_DIR_TX)) in tegra_spi_transfer_one_message()
1076 dmaengine_terminate_all(tspi->tx_dma_chan); in tegra_spi_transfer_one_message()
1077 if (tspi->is_curr_dma_xfer && in tegra_spi_transfer_one_message()
1078 (tspi->cur_direction & DATA_DIR_RX)) in tegra_spi_transfer_one_message()
1079 dmaengine_terminate_all(tspi->rx_dma_chan); in tegra_spi_transfer_one_message()
1080 ret = -EIO; in tegra_spi_transfer_one_message()
1083 reset_control_assert(tspi->rst); in tegra_spi_transfer_one_message()
1085 reset_control_deassert(tspi->rst); in tegra_spi_transfer_one_message()
1086 tspi->last_used_cs = master->num_chipselect + 1; in tegra_spi_transfer_one_message()
1090 if (tspi->tx_status || tspi->rx_status) { in tegra_spi_transfer_one_message()
1091 dev_err(tspi->dev, "Error in Transfer\n"); in tegra_spi_transfer_one_message()
1092 ret = -EIO; in tegra_spi_transfer_one_message()
1096 msg->actual_length += xfer->len; in tegra_spi_transfer_one_message()
1103 } else if (list_is_last(&xfer->transfer_list, in tegra_spi_transfer_one_message()
1104 &msg->transfers)) { in tegra_spi_transfer_one_message()
1105 if (xfer->cs_change) in tegra_spi_transfer_one_message()
1106 tspi->cs_control = spi; in tegra_spi_transfer_one_message()
1111 } else if (xfer->cs_change) { in tegra_spi_transfer_one_message()
1119 msg->status = ret; in tegra_spi_transfer_one_message()
1126 struct spi_transfer *t = tspi->curr_xfer; in handle_cpu_based_xfer()
1129 spin_lock_irqsave(&tspi->lock, flags); in handle_cpu_based_xfer()
1130 if (tspi->tx_status || tspi->rx_status) { in handle_cpu_based_xfer()
1131 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n", in handle_cpu_based_xfer()
1132 tspi->status_reg); in handle_cpu_based_xfer()
1133 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", in handle_cpu_based_xfer()
1134 tspi->command1_reg, tspi->dma_control_reg); in handle_cpu_based_xfer()
1137 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
1138 spin_unlock_irqrestore(&tspi->lock, flags); in handle_cpu_based_xfer()
1139 reset_control_assert(tspi->rst); in handle_cpu_based_xfer()
1141 reset_control_deassert(tspi->rst); in handle_cpu_based_xfer()
1145 if (tspi->cur_direction & DATA_DIR_RX) in handle_cpu_based_xfer()
1148 if (tspi->cur_direction & DATA_DIR_TX) in handle_cpu_based_xfer()
1149 tspi->cur_pos = tspi->cur_tx_pos; in handle_cpu_based_xfer()
1151 tspi->cur_pos = tspi->cur_rx_pos; in handle_cpu_based_xfer()
1153 if (tspi->cur_pos == t->len) { in handle_cpu_based_xfer()
1154 complete(&tspi->xfer_completion); in handle_cpu_based_xfer()
1158 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); in handle_cpu_based_xfer()
1161 spin_unlock_irqrestore(&tspi->lock, flags); in handle_cpu_based_xfer()
1167 struct spi_transfer *t = tspi->curr_xfer; in handle_dma_based_xfer()
1174 if (tspi->cur_direction & DATA_DIR_TX) { in handle_dma_based_xfer()
1175 if (tspi->tx_status) { in handle_dma_based_xfer()
1176 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
1180 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1182 dmaengine_terminate_all(tspi->tx_dma_chan); in handle_dma_based_xfer()
1183 dev_err(tspi->dev, "TxDma Xfer failed\n"); in handle_dma_based_xfer()
1189 if (tspi->cur_direction & DATA_DIR_RX) { in handle_dma_based_xfer()
1190 if (tspi->rx_status) { in handle_dma_based_xfer()
1191 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
1195 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT); in handle_dma_based_xfer()
1197 dmaengine_terminate_all(tspi->rx_dma_chan); in handle_dma_based_xfer()
1198 dev_err(tspi->dev, "RxDma Xfer failed\n"); in handle_dma_based_xfer()
1204 spin_lock_irqsave(&tspi->lock, flags); in handle_dma_based_xfer()
1206 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n", in handle_dma_based_xfer()
1207 tspi->status_reg); in handle_dma_based_xfer()
1208 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", in handle_dma_based_xfer()
1209 tspi->command1_reg, tspi->dma_control_reg); in handle_dma_based_xfer()
1212 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
1213 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
1214 reset_control_assert(tspi->rst); in handle_dma_based_xfer()
1216 reset_control_deassert(tspi->rst); in handle_dma_based_xfer()
1220 if (tspi->cur_direction & DATA_DIR_RX) in handle_dma_based_xfer()
1223 if (tspi->cur_direction & DATA_DIR_TX) in handle_dma_based_xfer()
1224 tspi->cur_pos = tspi->cur_tx_pos; in handle_dma_based_xfer()
1226 tspi->cur_pos = tspi->cur_rx_pos; in handle_dma_based_xfer()
1228 if (tspi->cur_pos == t->len) { in handle_dma_based_xfer()
1229 complete(&tspi->xfer_completion); in handle_dma_based_xfer()
1234 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, in handle_dma_based_xfer()
1242 spin_unlock_irqrestore(&tspi->lock, flags); in handle_dma_based_xfer()
1250 if (!tspi->is_curr_dma_xfer) in tegra_spi_isr_thread()
1259 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS); in tegra_spi_isr()
1260 if (tspi->cur_direction & DATA_DIR_TX) in tegra_spi_isr()
1261 tspi->tx_status = tspi->status_reg & in tegra_spi_isr()
1264 if (tspi->cur_direction & DATA_DIR_RX) in tegra_spi_isr()
1265 tspi->rx_status = tspi->status_reg & in tegra_spi_isr()
1286 .compatible = "nvidia,tegra114-spi",
1289 .compatible = "nvidia,tegra124-spi",
1292 .compatible = "nvidia,tegra210-spi",
1307 master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); in tegra_spi_probe()
1309 dev_err(&pdev->dev, "master allocation failed\n"); in tegra_spi_probe()
1310 return -ENOMEM; in tegra_spi_probe()
1315 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency", in tegra_spi_probe()
1316 &master->max_speed_hz)) in tegra_spi_probe()
1317 master->max_speed_hz = 25000000; /* 25MHz */ in tegra_spi_probe()
1319 /* the spi->mode bits understood by this driver: */ in tegra_spi_probe()
1320 master->use_gpio_descriptors = true; in tegra_spi_probe()
1321 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | in tegra_spi_probe()
1323 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in tegra_spi_probe()
1324 master->setup = tegra_spi_setup; in tegra_spi_probe()
1325 master->cleanup = tegra_spi_cleanup; in tegra_spi_probe()
1326 master->transfer_one_message = tegra_spi_transfer_one_message; in tegra_spi_probe()
1327 master->set_cs_timing = tegra_spi_set_hw_cs_timing; in tegra_spi_probe()
1328 master->num_chipselect = MAX_CHIP_SELECT; in tegra_spi_probe()
1329 master->auto_runtime_pm = true; in tegra_spi_probe()
1330 bus_num = of_alias_get_id(pdev->dev.of_node, "spi"); in tegra_spi_probe()
1332 master->bus_num = bus_num; in tegra_spi_probe()
1334 tspi->master = master; in tegra_spi_probe()
1335 tspi->dev = &pdev->dev; in tegra_spi_probe()
1336 spin_lock_init(&tspi->lock); in tegra_spi_probe()
1338 tspi->soc_data = of_device_get_match_data(&pdev->dev); in tegra_spi_probe()
1339 if (!tspi->soc_data) { in tegra_spi_probe()
1340 dev_err(&pdev->dev, "unsupported tegra\n"); in tegra_spi_probe()
1341 ret = -ENODEV; in tegra_spi_probe()
1346 tspi->base = devm_ioremap_resource(&pdev->dev, r); in tegra_spi_probe()
1347 if (IS_ERR(tspi->base)) { in tegra_spi_probe()
1348 ret = PTR_ERR(tspi->base); in tegra_spi_probe()
1351 tspi->phys = r->start; in tegra_spi_probe()
1358 tspi->irq = spi_irq; in tegra_spi_probe()
1360 tspi->clk = devm_clk_get(&pdev->dev, "spi"); in tegra_spi_probe()
1361 if (IS_ERR(tspi->clk)) { in tegra_spi_probe()
1362 dev_err(&pdev->dev, "can not get clock\n"); in tegra_spi_probe()
1363 ret = PTR_ERR(tspi->clk); in tegra_spi_probe()
1367 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); in tegra_spi_probe()
1368 if (IS_ERR(tspi->rst)) { in tegra_spi_probe()
1369 dev_err(&pdev->dev, "can not get reset\n"); in tegra_spi_probe()
1370 ret = PTR_ERR(tspi->rst); in tegra_spi_probe()
1374 tspi->max_buf_size = SPI_FIFO_DEPTH << 2; in tegra_spi_probe()
1375 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; in tegra_spi_probe()
1383 tspi->max_buf_size = tspi->dma_buf_size; in tegra_spi_probe()
1384 init_completion(&tspi->tx_dma_complete); in tegra_spi_probe()
1385 init_completion(&tspi->rx_dma_complete); in tegra_spi_probe()
1387 init_completion(&tspi->xfer_completion); in tegra_spi_probe()
1389 pm_runtime_enable(&pdev->dev); in tegra_spi_probe()
1390 if (!pm_runtime_enabled(&pdev->dev)) { in tegra_spi_probe()
1391 ret = tegra_spi_runtime_resume(&pdev->dev); in tegra_spi_probe()
1396 ret = pm_runtime_resume_and_get(&pdev->dev); in tegra_spi_probe()
1398 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); in tegra_spi_probe()
1402 reset_control_assert(tspi->rst); in tegra_spi_probe()
1404 reset_control_deassert(tspi->rst); in tegra_spi_probe()
1405 tspi->def_command1_reg = SPI_M_S; in tegra_spi_probe()
1406 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); in tegra_spi_probe()
1407 tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1); in tegra_spi_probe()
1408 tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2); in tegra_spi_probe()
1409 tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2); in tegra_spi_probe()
1410 tspi->last_used_cs = master->num_chipselect + 1; in tegra_spi_probe()
1411 pm_runtime_put(&pdev->dev); in tegra_spi_probe()
1412 ret = request_threaded_irq(tspi->irq, tegra_spi_isr, in tegra_spi_probe()
1414 dev_name(&pdev->dev), tspi); in tegra_spi_probe()
1416 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", in tegra_spi_probe()
1417 tspi->irq); in tegra_spi_probe()
1421 master->dev.of_node = pdev->dev.of_node; in tegra_spi_probe()
1422 ret = devm_spi_register_master(&pdev->dev, master); in tegra_spi_probe()
1424 dev_err(&pdev->dev, "can not register to master err %d\n", ret); in tegra_spi_probe()
1432 pm_runtime_disable(&pdev->dev); in tegra_spi_probe()
1433 if (!pm_runtime_status_suspended(&pdev->dev)) in tegra_spi_probe()
1434 tegra_spi_runtime_suspend(&pdev->dev); in tegra_spi_probe()
1448 free_irq(tspi->irq, tspi); in tegra_spi_remove()
1450 if (tspi->tx_dma_chan) in tegra_spi_remove()
1453 if (tspi->rx_dma_chan) in tegra_spi_remove()
1456 pm_runtime_disable(&pdev->dev); in tegra_spi_remove()
1457 if (!pm_runtime_status_suspended(&pdev->dev)) in tegra_spi_remove()
1458 tegra_spi_runtime_suspend(&pdev->dev); in tegra_spi_remove()
1482 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); in tegra_spi_resume()
1483 tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2); in tegra_spi_resume()
1484 tspi->last_used_cs = master->num_chipselect + 1; in tegra_spi_resume()
1499 clk_disable_unprepare(tspi->clk); in tegra_spi_runtime_suspend()
1509 ret = clk_prepare_enable(tspi->clk); in tegra_spi_runtime_resume()
1511 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); in tegra_spi_runtime_resume()
1524 .name = "spi-tegra114",
1533 MODULE_ALIAS("platform:spi-tegra114");