Lines Matching +full:clock +full:- +full:master
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012 - 2014 Allwinner Tech
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
89 struct spi_master *master; member
107 return readl(sspi->base_addr + reg); in sun6i_spi_read()
112 writel(value, sspi->base_addr + reg); in sun6i_spi_write()
145 while (len--) { in sun6i_spi_drain_fifo()
146 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); in sun6i_spi_drain_fifo()
147 if (sspi->rx_buf) in sun6i_spi_drain_fifo()
148 *sspi->rx_buf++ = byte; in sun6i_spi_drain_fifo()
159 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); in sun6i_spi_fill_fifo()
161 len = min((int)cnt, sspi->len); in sun6i_spi_fill_fifo()
163 while (len--) { in sun6i_spi_fill_fifo()
164 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; in sun6i_spi_fill_fifo()
165 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); in sun6i_spi_fill_fifo()
166 sspi->len--; in sun6i_spi_fill_fifo()
172 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); in sun6i_spi_set_cs()
177 reg |= SUN6I_TFR_CTL_CS(spi->chip_select); in sun6i_spi_set_cs()
189 return SUN6I_MAX_XFER_SIZE - 1; in sun6i_spi_max_transfer_size()
196 struct spi_master *master = sspi->master; in sun6i_spi_prepare_dma() local
199 if (tfr->rx_buf) { in sun6i_spi_prepare_dma()
202 .src_addr = sspi->dma_addr_rx, in sun6i_spi_prepare_dma()
207 dmaengine_slave_config(master->dma_rx, &rxconf); in sun6i_spi_prepare_dma()
209 rxdesc = dmaengine_prep_slave_sg(master->dma_rx, in sun6i_spi_prepare_dma()
210 tfr->rx_sg.sgl, in sun6i_spi_prepare_dma()
211 tfr->rx_sg.nents, in sun6i_spi_prepare_dma()
215 return -EINVAL; in sun6i_spi_prepare_dma()
219 if (tfr->tx_buf) { in sun6i_spi_prepare_dma()
222 .dst_addr = sspi->dma_addr_tx, in sun6i_spi_prepare_dma()
227 dmaengine_slave_config(master->dma_tx, &txconf); in sun6i_spi_prepare_dma()
229 txdesc = dmaengine_prep_slave_sg(master->dma_tx, in sun6i_spi_prepare_dma()
230 tfr->tx_sg.sgl, in sun6i_spi_prepare_dma()
231 tfr->tx_sg.nents, in sun6i_spi_prepare_dma()
236 dmaengine_terminate_sync(master->dma_rx); in sun6i_spi_prepare_dma()
237 return -EINVAL; in sun6i_spi_prepare_dma()
241 if (tfr->rx_buf) { in sun6i_spi_prepare_dma()
243 dma_async_issue_pending(master->dma_rx); in sun6i_spi_prepare_dma()
246 if (tfr->tx_buf) { in sun6i_spi_prepare_dma()
248 dma_async_issue_pending(master->dma_tx); in sun6i_spi_prepare_dma()
254 static int sun6i_spi_transfer_one(struct spi_master *master, in sun6i_spi_transfer_one() argument
258 struct sun6i_spi *sspi = spi_master_get_devdata(master); in sun6i_spi_transfer_one()
267 if (tfr->len > SUN6I_MAX_XFER_SIZE) in sun6i_spi_transfer_one()
268 return -EINVAL; in sun6i_spi_transfer_one()
270 reinit_completion(&sspi->done); in sun6i_spi_transfer_one()
271 sspi->tx_buf = tfr->tx_buf; in sun6i_spi_transfer_one()
272 sspi->rx_buf = tfr->rx_buf; in sun6i_spi_transfer_one()
273 sspi->len = tfr->len; in sun6i_spi_transfer_one()
274 use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false; in sun6i_spi_transfer_one()
290 * SPI controller. (See spi-sun4i.c) in sun6i_spi_transfer_one()
292 trig_level = sspi->fifo_depth / 4 * 3; in sun6i_spi_transfer_one()
299 trig_level = sspi->fifo_depth / 2; in sun6i_spi_transfer_one()
301 if (tfr->tx_buf) in sun6i_spi_transfer_one()
303 if (tfr->rx_buf) in sun6i_spi_transfer_one()
318 if (spi->mode & SPI_CPOL) in sun6i_spi_transfer_one()
323 if (spi->mode & SPI_CPHA) in sun6i_spi_transfer_one()
328 if (spi->mode & SPI_LSB_FIRST) in sun6i_spi_transfer_one()
337 if (sspi->rx_buf) { in sun6i_spi_transfer_one()
339 rx_len = tfr->len; in sun6i_spi_transfer_one()
349 /* Ensure that we have a parent clock fast enough */ in sun6i_spi_transfer_one()
350 mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
351 if (mclk_rate < (2 * tfr->speed_hz)) { in sun6i_spi_transfer_one()
352 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); in sun6i_spi_transfer_one()
353 mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
357 * Setup clock divider. in sun6i_spi_transfer_one()
359 * We have two choices there. Either we can use the clock in sun6i_spi_transfer_one()
370 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); in sun6i_spi_transfer_one()
373 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; in sun6i_spi_transfer_one()
374 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); in sun6i_spi_transfer_one()
378 tfr->effective_speed_hz = mclk_rate / (1 << div); in sun6i_spi_transfer_one()
382 /* Finally enable the bus - doing so before might raise SCK to HIGH */ in sun6i_spi_transfer_one()
388 if (sspi->tx_buf) in sun6i_spi_transfer_one()
389 tx_len = tfr->len; in sun6i_spi_transfer_one()
392 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); in sun6i_spi_transfer_one()
402 dev_warn(&master->dev, in sun6i_spi_transfer_one()
404 dev_name(&spi->dev), ret); in sun6i_spi_transfer_one()
413 if (rx_len > sspi->fifo_depth) in sun6i_spi_transfer_one()
415 if (tx_len > sspi->fifo_depth) in sun6i_spi_transfer_one()
425 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); in sun6i_spi_transfer_one()
427 timeout = wait_for_completion_timeout(&sspi->done, in sun6i_spi_transfer_one()
431 dev_warn(&master->dev, in sun6i_spi_transfer_one()
433 dev_name(&spi->dev), tfr->len, tfr->speed_hz, in sun6i_spi_transfer_one()
434 jiffies_to_msecs(end - start), tx_time); in sun6i_spi_transfer_one()
435 ret = -ETIMEDOUT; in sun6i_spi_transfer_one()
441 dmaengine_terminate_sync(master->dma_rx); in sun6i_spi_transfer_one()
442 dmaengine_terminate_sync(master->dma_tx); in sun6i_spi_transfer_one()
457 complete(&sspi->done); in sun6i_spi_handler()
473 if (!sspi->len) in sun6i_spi_handler()
477 /* Only clear the interrupt _after_ re-seeding the FIFO */ in sun6i_spi_handler()
488 struct spi_master *master = dev_get_drvdata(dev); in sun6i_spi_runtime_resume() local
489 struct sun6i_spi *sspi = spi_master_get_devdata(master); in sun6i_spi_runtime_resume()
492 ret = clk_prepare_enable(sspi->hclk); in sun6i_spi_runtime_resume()
494 dev_err(dev, "Couldn't enable AHB clock\n"); in sun6i_spi_runtime_resume()
498 ret = clk_prepare_enable(sspi->mclk); in sun6i_spi_runtime_resume()
500 dev_err(dev, "Couldn't enable module clock\n"); in sun6i_spi_runtime_resume()
504 ret = reset_control_deassert(sspi->rstc); in sun6i_spi_runtime_resume()
516 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_resume()
518 clk_disable_unprepare(sspi->hclk); in sun6i_spi_runtime_resume()
525 struct spi_master *master = dev_get_drvdata(dev); in sun6i_spi_runtime_suspend() local
526 struct sun6i_spi *sspi = spi_master_get_devdata(master); in sun6i_spi_runtime_suspend()
528 reset_control_assert(sspi->rstc); in sun6i_spi_runtime_suspend()
529 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_suspend()
530 clk_disable_unprepare(sspi->hclk); in sun6i_spi_runtime_suspend()
535 static bool sun6i_spi_can_dma(struct spi_master *master, in sun6i_spi_can_dma() argument
539 struct sun6i_spi *sspi = spi_master_get_devdata(master); in sun6i_spi_can_dma()
546 return xfer->len > sspi->fifo_depth; in sun6i_spi_can_dma()
551 struct spi_master *master; in sun6i_spi_probe() local
556 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); in sun6i_spi_probe()
557 if (!master) { in sun6i_spi_probe()
558 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); in sun6i_spi_probe()
559 return -ENOMEM; in sun6i_spi_probe()
562 platform_set_drvdata(pdev, master); in sun6i_spi_probe()
563 sspi = spi_master_get_devdata(master); in sun6i_spi_probe()
565 sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); in sun6i_spi_probe()
566 if (IS_ERR(sspi->base_addr)) { in sun6i_spi_probe()
567 ret = PTR_ERR(sspi->base_addr); in sun6i_spi_probe()
573 ret = -ENXIO; in sun6i_spi_probe()
577 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, in sun6i_spi_probe()
578 0, "sun6i-spi", sspi); in sun6i_spi_probe()
580 dev_err(&pdev->dev, "Cannot request IRQ\n"); in sun6i_spi_probe()
584 sspi->master = master; in sun6i_spi_probe()
585 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); in sun6i_spi_probe()
587 master->max_speed_hz = 100 * 1000 * 1000; in sun6i_spi_probe()
588 master->min_speed_hz = 3 * 1000; in sun6i_spi_probe()
589 master->use_gpio_descriptors = true; in sun6i_spi_probe()
590 master->set_cs = sun6i_spi_set_cs; in sun6i_spi_probe()
591 master->transfer_one = sun6i_spi_transfer_one; in sun6i_spi_probe()
592 master->num_chipselect = 4; in sun6i_spi_probe()
593 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; in sun6i_spi_probe()
594 master->bits_per_word_mask = SPI_BPW_MASK(8); in sun6i_spi_probe()
595 master->dev.of_node = pdev->dev.of_node; in sun6i_spi_probe()
596 master->auto_runtime_pm = true; in sun6i_spi_probe()
597 master->max_transfer_size = sun6i_spi_max_transfer_size; in sun6i_spi_probe()
599 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); in sun6i_spi_probe()
600 if (IS_ERR(sspi->hclk)) { in sun6i_spi_probe()
601 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); in sun6i_spi_probe()
602 ret = PTR_ERR(sspi->hclk); in sun6i_spi_probe()
606 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); in sun6i_spi_probe()
607 if (IS_ERR(sspi->mclk)) { in sun6i_spi_probe()
608 dev_err(&pdev->dev, "Unable to acquire module clock\n"); in sun6i_spi_probe()
609 ret = PTR_ERR(sspi->mclk); in sun6i_spi_probe()
613 init_completion(&sspi->done); in sun6i_spi_probe()
615 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); in sun6i_spi_probe()
616 if (IS_ERR(sspi->rstc)) { in sun6i_spi_probe()
617 dev_err(&pdev->dev, "Couldn't get reset controller\n"); in sun6i_spi_probe()
618 ret = PTR_ERR(sspi->rstc); in sun6i_spi_probe()
622 master->dma_tx = dma_request_chan(&pdev->dev, "tx"); in sun6i_spi_probe()
623 if (IS_ERR(master->dma_tx)) { in sun6i_spi_probe()
625 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) { in sun6i_spi_probe()
626 ret = -EPROBE_DEFER; in sun6i_spi_probe()
629 dev_warn(&pdev->dev, "Failed to request TX DMA channel\n"); in sun6i_spi_probe()
630 master->dma_tx = NULL; in sun6i_spi_probe()
633 master->dma_rx = dma_request_chan(&pdev->dev, "rx"); in sun6i_spi_probe()
634 if (IS_ERR(master->dma_rx)) { in sun6i_spi_probe()
635 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) { in sun6i_spi_probe()
636 ret = -EPROBE_DEFER; in sun6i_spi_probe()
639 dev_warn(&pdev->dev, "Failed to request RX DMA channel\n"); in sun6i_spi_probe()
640 master->dma_rx = NULL; in sun6i_spi_probe()
643 if (master->dma_tx && master->dma_rx) { in sun6i_spi_probe()
644 sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG; in sun6i_spi_probe()
645 sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG; in sun6i_spi_probe()
646 master->can_dma = sun6i_spi_can_dma; in sun6i_spi_probe()
650 * This wake-up/shutdown pattern is to be able to have the in sun6i_spi_probe()
653 ret = sun6i_spi_runtime_resume(&pdev->dev); in sun6i_spi_probe()
655 dev_err(&pdev->dev, "Couldn't resume the device\n"); in sun6i_spi_probe()
659 pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT); in sun6i_spi_probe()
660 pm_runtime_use_autosuspend(&pdev->dev); in sun6i_spi_probe()
661 pm_runtime_set_active(&pdev->dev); in sun6i_spi_probe()
662 pm_runtime_enable(&pdev->dev); in sun6i_spi_probe()
664 ret = devm_spi_register_master(&pdev->dev, master); in sun6i_spi_probe()
666 dev_err(&pdev->dev, "cannot register SPI master\n"); in sun6i_spi_probe()
673 pm_runtime_disable(&pdev->dev); in sun6i_spi_probe()
674 sun6i_spi_runtime_suspend(&pdev->dev); in sun6i_spi_probe()
676 if (master->dma_rx) in sun6i_spi_probe()
677 dma_release_channel(master->dma_rx); in sun6i_spi_probe()
679 if (master->dma_tx) in sun6i_spi_probe()
680 dma_release_channel(master->dma_tx); in sun6i_spi_probe()
682 spi_master_put(master); in sun6i_spi_probe()
688 struct spi_master *master = platform_get_drvdata(pdev); in sun6i_spi_remove() local
690 pm_runtime_force_suspend(&pdev->dev); in sun6i_spi_remove()
692 if (master->dma_tx) in sun6i_spi_remove()
693 dma_release_channel(master->dma_tx); in sun6i_spi_remove()
694 if (master->dma_rx) in sun6i_spi_remove()
695 dma_release_channel(master->dma_rx); in sun6i_spi_remove()
700 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
701 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
715 .name = "sun6i-spi",
723 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");