Lines Matching full:spi
3 // STMicroelectronics STM32 SPI Controller driver (master mode only)
20 #include <linux/spi/spi.h>
24 /* STM32F4 SPI registers */
73 /* STM32F4 SPI Baud Rate min/max divisor */
77 /* STM32H7 SPI registers */
148 /* STM32H7 SPI Master Baud Rate min/max divisor */
152 /* STM32H7 SPI Communication mode */
158 /* SPI Communication type */
174 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
187 * @en: enable register and SPI enable bit
188 * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
189 * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
194 * @rx: SPI RX data register
195 * @tx: SPI TX data register
217 * @config: routine to configure controller as SPI Master
229 * @irq_handler_event: Interrupt handler for SPI controller events
230 * @irq_handler_thread: thread of interrupt handler for SPI controller
234 * @flags: compatible specific SPI controller flags used at registration time
238 int (*get_fifo_size)(struct stm32_spi *spi);
239 int (*get_bpw_mask)(struct stm32_spi *spi);
240 void (*disable)(struct stm32_spi *spi);
241 int (*config)(struct stm32_spi *spi);
242 void (*set_bpw)(struct stm32_spi *spi);
243 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
244 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
245 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
246 void (*transfer_one_dma_start)(struct stm32_spi *spi);
249 int (*transfer_one_irq)(struct stm32_spi *spi);
259 * struct stm32_spi - private data of the SPI controller
264 * @clk: hw kernel clock feeding the SPI clock generator
265 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
267 * @irq: SPI controller interrupt line
271 * @cur_bpw: number of bits in a single SPI data frame
273 * @cur_comm: SPI communication mode
282 * @phys_addr: SPI registers physical base address
328 /* SPI data transfer is enabled but spi_ker_ck is idle.
346 static inline void stm32_spi_set_bits(struct stm32_spi *spi, in stm32_spi_set_bits() argument
349 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
350 spi->base + offset); in stm32_spi_set_bits()
353 static inline void stm32_spi_clr_bits(struct stm32_spi *spi, in stm32_spi_clr_bits() argument
356 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
357 spi->base + offset); in stm32_spi_clr_bits()
362 * @spi: pointer to the spi controller data structure
364 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) in stm32h7_spi_get_fifo_size() argument
369 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
371 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
373 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
374 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
376 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_get_fifo_size()
378 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
380 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32h7_spi_get_fifo_size()
387 * @spi: pointer to the spi controller data structure
389 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi) in stm32f4_spi_get_bpw_mask() argument
391 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32f4_spi_get_bpw_mask()
397 * @spi: pointer to the spi controller data structure
399 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) in stm32h7_spi_get_bpw_mask() argument
404 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
410 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); in stm32h7_spi_get_bpw_mask()
412 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_get_bpw_mask()
415 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
417 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32h7_spi_get_bpw_mask()
424 * @spi: pointer to the spi controller data structure
431 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, in stm32_spi_prepare_mbr() argument
436 /* Ensure spi->clk_rate is even */ in stm32_spi_prepare_mbr()
437 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz); in stm32_spi_prepare_mbr()
440 * SPI framework set xfer->speed_hz to master->max_speed_hz if in stm32_spi_prepare_mbr()
455 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
462 * @spi: pointer to the spi controller data structure
465 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len) in stm32h7_spi_prepare_fthlv() argument
470 packet = clamp(xfer_len, 1U, spi->fifo_size / 2); in stm32h7_spi_prepare_fthlv()
473 bpw = DIV_ROUND_UP(spi->cur_bpw, 8); in stm32h7_spi_prepare_fthlv()
479 * @spi: pointer to the spi controller data structure
484 static void stm32f4_spi_write_tx(struct stm32_spi *spi) in stm32f4_spi_write_tx() argument
486 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_write_tx()
488 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f4_spi_write_tx()
490 if (spi->cur_bpw == 16) { in stm32f4_spi_write_tx()
491 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
493 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
494 spi->tx_len -= sizeof(u16); in stm32f4_spi_write_tx()
496 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
498 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
499 spi->tx_len -= sizeof(u8); in stm32f4_spi_write_tx()
503 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f4_spi_write_tx()
508 * @spi: pointer to the spi controller data structure
513 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi) in stm32h7_spi_write_txfifo() argument
515 while ((spi->tx_len > 0) && in stm32h7_spi_write_txfifo()
516 (readl_relaxed(spi->base + STM32H7_SPI_SR) & in stm32h7_spi_write_txfifo()
518 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32h7_spi_write_txfifo()
520 if (spi->tx_len >= sizeof(u32)) { in stm32h7_spi_write_txfifo()
521 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
523 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
524 spi->tx_len -= sizeof(u32); in stm32h7_spi_write_txfifo()
525 } else if (spi->tx_len >= sizeof(u16)) { in stm32h7_spi_write_txfifo()
526 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
528 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
529 spi->tx_len -= sizeof(u16); in stm32h7_spi_write_txfifo()
531 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
533 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
534 spi->tx_len -= sizeof(u8); in stm32h7_spi_write_txfifo()
538 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32h7_spi_write_txfifo()
543 * @spi: pointer to the spi controller data structure
548 static void stm32f4_spi_read_rx(struct stm32_spi *spi) in stm32f4_spi_read_rx() argument
550 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_read_rx()
552 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f4_spi_read_rx()
554 if (spi->cur_bpw == 16) { in stm32f4_spi_read_rx()
555 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
557 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
558 spi->rx_len -= sizeof(u16); in stm32f4_spi_read_rx()
560 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
562 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
563 spi->rx_len -= sizeof(u8); in stm32f4_spi_read_rx()
567 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); in stm32f4_spi_read_rx()
572 * @spi: pointer to the spi controller data structure
577 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi) in stm32h7_spi_read_rxfifo() argument
579 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
582 while ((spi->rx_len > 0) && in stm32h7_spi_read_rxfifo()
586 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32h7_spi_read_rxfifo()
588 if ((spi->rx_len >= sizeof(u32)) || in stm32h7_spi_read_rxfifo()
590 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
592 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
593 spi->rx_len -= sizeof(u32); in stm32h7_spi_read_rxfifo()
594 } else if ((spi->rx_len >= sizeof(u16)) || in stm32h7_spi_read_rxfifo()
596 (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32h7_spi_read_rxfifo()
597 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
599 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
600 spi->rx_len -= sizeof(u16); in stm32h7_spi_read_rxfifo()
602 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
604 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
605 spi->rx_len -= sizeof(u8); in stm32h7_spi_read_rxfifo()
608 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
612 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n", in stm32h7_spi_read_rxfifo()
613 __func__, spi->rx_len, sr); in stm32h7_spi_read_rxfifo()
617 * stm32_spi_enable - Enable SPI controller
618 * @spi: pointer to the spi controller data structure
620 static void stm32_spi_enable(struct stm32_spi *spi) in stm32_spi_enable() argument
622 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
624 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, in stm32_spi_enable()
625 spi->cfg->regs->en.mask); in stm32_spi_enable()
629 * stm32f4_spi_disable - Disable SPI controller
630 * @spi: pointer to the spi controller data structure
632 static void stm32f4_spi_disable(struct stm32_spi *spi) in stm32f4_spi_disable() argument
637 dev_dbg(spi->dev, "disable controller\n"); in stm32f4_spi_disable()
639 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_disable()
641 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & in stm32f4_spi_disable()
643 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
648 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE | in stm32f4_spi_disable()
653 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, in stm32f4_spi_disable()
656 dev_warn(spi->dev, "disabling condition timeout\n"); in stm32f4_spi_disable()
659 if (spi->cur_usedma && spi->dma_tx) in stm32f4_spi_disable()
660 dmaengine_terminate_all(spi->dma_tx); in stm32f4_spi_disable()
661 if (spi->cur_usedma && spi->dma_rx) in stm32f4_spi_disable()
662 dmaengine_terminate_all(spi->dma_rx); in stm32f4_spi_disable()
664 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE); in stm32f4_spi_disable()
666 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN | in stm32f4_spi_disable()
670 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_disable()
671 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_disable()
673 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
677 * stm32h7_spi_disable - Disable SPI controller
678 * @spi: pointer to the spi controller data structure
680 * RX-Fifo is flushed when SPI controller is disabled.
682 static void stm32h7_spi_disable(struct stm32_spi *spi) in stm32h7_spi_disable() argument
687 dev_dbg(spi->dev, "disable controller\n"); in stm32h7_spi_disable()
689 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_disable()
691 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
694 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
698 if (spi->cur_usedma && spi->dma_tx) in stm32h7_spi_disable()
699 dmaengine_terminate_all(spi->dma_tx); in stm32h7_spi_disable()
700 if (spi->cur_usedma && spi->dma_rx) in stm32h7_spi_disable()
701 dmaengine_terminate_all(spi->dma_rx); in stm32h7_spi_disable()
703 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); in stm32h7_spi_disable()
705 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | in stm32h7_spi_disable()
709 writel_relaxed(0, spi->base + STM32H7_SPI_IER); in stm32h7_spi_disable()
710 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_disable()
712 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
718 * @spi_dev: pointer to the spi device
719 * @transfer: pointer to spi transfer
729 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_can_dma() local
731 if (spi->cfg->has_fifo) in stm32_spi_can_dma()
732 dma_size = spi->fifo_size; in stm32_spi_can_dma()
736 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
743 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
745 * @dev_id: SPI controller master interface
750 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32f4_spi_irq_event() local
754 spin_lock(&spi->lock); in stm32f4_spi_irq_event()
756 sr = readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
763 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || in stm32f4_spi_irq_event()
764 spi->cur_comm == SPI_3WIRE_TX)) { in stm32f4_spi_irq_event()
770 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_irq_event()
771 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_irq_event()
772 spi->cur_comm == SPI_3WIRE_RX)) { in stm32f4_spi_irq_event()
779 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); in stm32f4_spi_irq_event()
780 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
785 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32f4_spi_irq_event()
788 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_irq_event()
789 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
801 if (spi->tx_buf) in stm32f4_spi_irq_event()
802 stm32f4_spi_write_tx(spi); in stm32f4_spi_irq_event()
803 if (spi->tx_len == 0) in stm32f4_spi_irq_event()
808 stm32f4_spi_read_rx(spi); in stm32f4_spi_irq_event()
809 if (spi->rx_len == 0) in stm32f4_spi_irq_event()
811 else if (spi->tx_buf)/* Load data for discontinuous mode */ in stm32f4_spi_irq_event()
812 stm32f4_spi_write_tx(spi); in stm32f4_spi_irq_event()
818 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, in stm32f4_spi_irq_event()
822 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
826 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
831 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
833 * @dev_id: SPI controller master interface
838 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32f4_spi_irq_thread() local
841 stm32f4_spi_disable(spi); in stm32f4_spi_irq_thread()
847 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
849 * @dev_id: SPI controller master interface
854 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32h7_spi_irq_thread() local
859 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_irq_thread()
861 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_irq_thread()
862 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); in stm32h7_spi_irq_thread()
875 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma) in stm32h7_spi_irq_thread()
879 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32h7_spi_irq_thread()
881 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
891 dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); in stm32h7_spi_irq_thread()
892 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
893 stm32h7_spi_read_rxfifo(spi); in stm32h7_spi_irq_thread()
898 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
903 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32h7_spi_irq_thread()
908 dev_err(spi->dev, "Overrun: RX data lost\n"); in stm32h7_spi_irq_thread()
913 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
914 stm32h7_spi_read_rxfifo(spi); in stm32h7_spi_irq_thread()
915 if (!spi->cur_usedma || in stm32h7_spi_irq_thread()
916 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)) in stm32h7_spi_irq_thread()
921 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32h7_spi_irq_thread()
922 stm32h7_spi_write_txfifo(spi); in stm32h7_spi_irq_thread()
925 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
926 stm32h7_spi_read_rxfifo(spi); in stm32h7_spi_irq_thread()
928 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_irq_thread()
930 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
933 stm32h7_spi_disable(spi); in stm32h7_spi_irq_thread()
943 * @msg: pointer to spi message
948 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_prepare_msg() local
949 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
954 /* SPI slave device may need time between data frames */ in stm32_spi_prepare_msg()
955 spi->cur_midi = 0; in stm32_spi_prepare_msg()
956 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
957 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
960 setb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
962 clrb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
965 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
967 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
970 setb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
972 clrb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
974 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
984 if (spi->cfg->set_number_of_data) { in stm32_spi_prepare_msg()
994 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
999 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & in stm32_spi_prepare_msg()
1001 spi->base + spi->cfg->regs->cpol.reg); in stm32_spi_prepare_msg()
1003 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
1010 * @data: pointer to the spi controller data structure
1016 struct stm32_spi *spi = data; in stm32f4_spi_dma_tx_cb() local
1018 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_dma_tx_cb()
1019 spi_finalize_current_transfer(spi->master); in stm32f4_spi_dma_tx_cb()
1020 stm32f4_spi_disable(spi); in stm32f4_spi_dma_tx_cb()
1026 * @data: pointer to the spi controller data structure
1032 struct stm32_spi *spi = data; in stm32_spi_dma_rx_cb() local
1034 spi_finalize_current_transfer(spi->master); in stm32_spi_dma_rx_cb()
1035 spi->cfg->disable(spi); in stm32_spi_dma_rx_cb()
1041 * @spi: pointer to the spi controller data structure
1045 static void stm32_spi_dma_config(struct stm32_spi *spi, in stm32_spi_dma_config() argument
1052 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
1054 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
1059 if (spi->cfg->has_fifo) { in stm32_spi_dma_config()
1061 if (spi->cur_fthlv == 2) in stm32_spi_dma_config()
1064 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
1072 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; in stm32_spi_dma_config()
1076 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1079 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; in stm32_spi_dma_config()
1083 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1091 * @spi: pointer to the spi controller data structure
1096 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) in stm32f4_spi_transfer_one_irq() argument
1102 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_transfer_one_irq()
1104 } else if (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_transfer_one_irq()
1105 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_transfer_one_irq()
1106 spi->cur_comm == SPI_3WIRE_RX) { in stm32f4_spi_transfer_one_irq()
1116 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1118 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2); in stm32f4_spi_transfer_one_irq()
1120 stm32_spi_enable(spi); in stm32f4_spi_transfer_one_irq()
1123 if (spi->tx_buf) in stm32f4_spi_transfer_one_irq()
1124 stm32f4_spi_write_tx(spi); in stm32f4_spi_transfer_one_irq()
1126 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1134 * @spi: pointer to the spi controller data structure
1139 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) in stm32h7_spi_transfer_one_irq() argument
1145 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32h7_spi_transfer_one_irq()
1147 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32h7_spi_transfer_one_irq()
1149 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32h7_spi_transfer_one_irq()
1156 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1158 stm32_spi_enable(spi); in stm32h7_spi_transfer_one_irq()
1161 if (spi->tx_buf) in stm32h7_spi_transfer_one_irq()
1162 stm32h7_spi_write_txfifo(spi); in stm32h7_spi_transfer_one_irq()
1164 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_irq()
1166 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); in stm32h7_spi_transfer_one_irq()
1168 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1174 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1176 * @spi: pointer to the spi controller data structure
1178 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32f4_spi_transfer_one_dma_start() argument
1181 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || in stm32f4_spi_transfer_one_dma_start()
1182 spi->cur_comm == SPI_FULL_DUPLEX) { in stm32f4_spi_transfer_one_dma_start()
1188 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE); in stm32f4_spi_transfer_one_dma_start()
1191 stm32_spi_enable(spi); in stm32f4_spi_transfer_one_dma_start()
1195 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1197 * @spi: pointer to the spi controller data structure
1199 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) in stm32h7_spi_transfer_one_dma_start() argument
1204 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) in stm32h7_spi_transfer_one_dma_start()
1207 stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier); in stm32h7_spi_transfer_one_dma_start()
1209 stm32_spi_enable(spi); in stm32h7_spi_transfer_one_dma_start()
1211 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); in stm32h7_spi_transfer_one_dma_start()
1216 * @spi: pointer to the spi controller data structure
1222 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, in stm32_spi_transfer_one_dma() argument
1229 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1232 if (spi->rx_buf && spi->dma_rx) { in stm32_spi_transfer_one_dma()
1233 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); in stm32_spi_transfer_one_dma()
1234 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1237 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1238 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1241 spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
1248 if (spi->tx_buf && spi->dma_tx) { in stm32_spi_transfer_one_dma()
1249 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); in stm32_spi_transfer_one_dma()
1250 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
1253 spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
1259 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
1260 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1263 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1267 rx_dma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1268 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1271 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1275 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
1279 if (spi->cur_comm == SPI_SIMPLEX_TX || in stm32_spi_transfer_one_dma()
1280 spi->cur_comm == SPI_3WIRE_TX) { in stm32_spi_transfer_one_dma()
1281 tx_dma_desc->callback = spi->cfg->dma_tx_cb; in stm32_spi_transfer_one_dma()
1282 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1286 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1290 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
1293 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, in stm32_spi_transfer_one_dma()
1294 spi->cfg->regs->dma_tx_en.mask); in stm32_spi_transfer_one_dma()
1297 spi->cfg->transfer_one_dma_start(spi); in stm32_spi_transfer_one_dma()
1299 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1304 if (spi->dma_rx) in stm32_spi_transfer_one_dma()
1305 dmaengine_terminate_all(spi->dma_rx); in stm32_spi_transfer_one_dma()
1308 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1309 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1311 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1313 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
1315 spi->cur_usedma = false; in stm32_spi_transfer_one_dma()
1316 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
1321 * @spi: pointer to the spi controller data structure
1323 static void stm32f4_spi_set_bpw(struct stm32_spi *spi) in stm32f4_spi_set_bpw() argument
1325 if (spi->cur_bpw == 16) in stm32f4_spi_set_bpw()
1326 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); in stm32f4_spi_set_bpw()
1328 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); in stm32f4_spi_set_bpw()
1333 * @spi: pointer to the spi controller data structure
1335 static void stm32h7_spi_set_bpw(struct stm32_spi *spi) in stm32h7_spi_set_bpw() argument
1340 bpw = spi->cur_bpw - 1; in stm32h7_spi_set_bpw()
1345 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); in stm32h7_spi_set_bpw()
1346 fthlv = spi->cur_fthlv - 1; in stm32h7_spi_set_bpw()
1352 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & in stm32h7_spi_set_bpw()
1354 spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_set_bpw()
1359 * @spi: pointer to the spi controller data structure
1362 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) in stm32_spi_set_mbr() argument
1366 clrb |= spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1367 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1369 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & in stm32_spi_set_mbr()
1371 spi->base + spi->cfg->regs->br.reg); in stm32_spi_set_mbr()
1376 * @spi_dev: pointer to the spi device
1377 * @transfer: pointer to spi transfer
1387 * is forbidden and unvalidated by SPI subsystem so depending in stm32_spi_communication_type()
1407 * @spi: pointer to the spi controller data structure
1410 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) in stm32f4_spi_set_mode() argument
1413 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1418 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1422 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1424 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, in stm32f4_spi_set_mode()
1435 * @spi: pointer to the spi controller data structure
1438 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) in stm32h7_spi_set_mode() argument
1445 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1448 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); in stm32h7_spi_set_mode()
1461 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_set_mode()
1463 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_set_mode()
1471 * @spi: pointer to the spi controller data structure
1474 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) in stm32h7_spi_data_idleness() argument
1479 if ((len > 1) && (spi->cur_midi > 0)) { in stm32h7_spi_data_idleness()
1480 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed); in stm32h7_spi_data_idleness()
1482 DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32h7_spi_data_idleness()
1487 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32h7_spi_data_idleness()
1492 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_data_idleness()
1494 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_data_idleness()
1499 * @spi: pointer to the spi controller data structure
1502 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) in stm32h7_spi_number_of_data() argument
1506 spi->base + STM32H7_SPI_CR2); in stm32h7_spi_number_of_data()
1518 * @spi: pointer to the spi controller data structure
1519 * @spi_dev: pointer to the spi device
1520 * @transfer: pointer to spi transfer
1522 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, in stm32_spi_transfer_one_setup() argument
1531 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1533 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
1535 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
1536 spi->cfg->set_bpw(spi); in stm32_spi_transfer_one_setup()
1538 /* Update spi->cur_speed with real clock speed */ in stm32_spi_transfer_one_setup()
1539 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, in stm32_spi_transfer_one_setup()
1540 spi->cfg->baud_rate_div_min, in stm32_spi_transfer_one_setup()
1541 spi->cfg->baud_rate_div_max); in stm32_spi_transfer_one_setup()
1547 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
1548 stm32_spi_set_mbr(spi, mbr); in stm32_spi_transfer_one_setup()
1551 ret = spi->cfg->set_mode(spi, comm_type); in stm32_spi_transfer_one_setup()
1555 spi->cur_comm = comm_type; in stm32_spi_transfer_one_setup()
1557 if (spi->cfg->set_data_idleness) in stm32_spi_transfer_one_setup()
1558 spi->cfg->set_data_idleness(spi, transfer->len); in stm32_spi_transfer_one_setup()
1560 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
1562 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
1567 if (spi->cfg->set_number_of_data) { in stm32_spi_transfer_one_setup()
1568 ret = spi->cfg->set_number_of_data(spi, nb_words); in stm32_spi_transfer_one_setup()
1573 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
1574 spi->cur_comm); in stm32_spi_transfer_one_setup()
1575 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
1577 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
1578 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
1579 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
1580 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
1581 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
1582 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
1585 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1593 * @spi_dev: pointer to the spi device
1594 * @transfer: pointer to spi transfer
1603 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_transfer_one() local
1606 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
1607 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
1608 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1609 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1611 spi->cur_usedma = (master->can_dma && in stm32_spi_transfer_one()
1614 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); in stm32_spi_transfer_one()
1616 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
1620 if (spi->cur_usedma) in stm32_spi_transfer_one()
1621 return stm32_spi_transfer_one_dma(spi, transfer); in stm32_spi_transfer_one()
1623 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one()
1629 * @msg: pointer to the spi message
1634 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_unprepare_msg() local
1636 spi->cfg->disable(spi); in stm32_spi_unprepare_msg()
1642 * stm32f4_spi_config - Configure SPI controller as SPI master
1643 * @spi: pointer to the spi controller data structure
1645 static int stm32f4_spi_config(struct stm32_spi *spi) in stm32f4_spi_config() argument
1649 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_config()
1652 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR, in stm32f4_spi_config()
1662 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI | in stm32f4_spi_config()
1667 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_config()
1673 * stm32h7_spi_config - Configure SPI controller as SPI master
1674 * @spi: pointer to the spi controller data structure
1676 static int stm32h7_spi_config(struct stm32_spi *spi) in stm32h7_spi_config() argument
1680 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_config()
1683 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, in stm32h7_spi_config()
1691 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI | in stm32h7_spi_config()
1701 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER | in stm32h7_spi_config()
1705 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_config()
1743 * SPI access hence handling is performed within the SPI interrupt
1753 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1754 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1762 struct stm32_spi *spi; in stm32_spi_probe() local
1769 dev_err(&pdev->dev, "spi master allocation failed\n"); in stm32_spi_probe()
1774 spi = spi_master_get_devdata(master); in stm32_spi_probe()
1775 spi->dev = &pdev->dev; in stm32_spi_probe()
1776 spi->master = master; in stm32_spi_probe()
1777 spin_lock_init(&spi->lock); in stm32_spi_probe()
1779 spi->cfg = (const struct stm32_spi_cfg *) in stm32_spi_probe()
1784 spi->base = devm_ioremap_resource(&pdev->dev, res); in stm32_spi_probe()
1785 if (IS_ERR(spi->base)) in stm32_spi_probe()
1786 return PTR_ERR(spi->base); in stm32_spi_probe()
1788 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
1790 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
1791 if (spi->irq <= 0) in stm32_spi_probe()
1792 return dev_err_probe(&pdev->dev, spi->irq, in stm32_spi_probe()
1795 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, in stm32_spi_probe()
1796 spi->cfg->irq_handler_event, in stm32_spi_probe()
1797 spi->cfg->irq_handler_thread, in stm32_spi_probe()
1800 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
1805 spi->clk = devm_clk_get(&pdev->dev, NULL); in stm32_spi_probe()
1806 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
1807 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
1812 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
1817 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
1818 if (!spi->clk_rate) { in stm32_spi_probe()
1837 if (spi->cfg->has_fifo) in stm32_spi_probe()
1838 spi->fifo_size = spi->cfg->get_fifo_size(spi); in stm32_spi_probe()
1840 ret = spi->cfg->config(spi); in stm32_spi_probe()
1852 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); in stm32_spi_probe()
1853 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; in stm32_spi_probe()
1854 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; in stm32_spi_probe()
1859 master->flags = spi->cfg->flags; in stm32_spi_probe()
1861 spi->dma_tx = dma_request_chan(spi->dev, "tx"); in stm32_spi_probe()
1862 if (IS_ERR(spi->dma_tx)) { in stm32_spi_probe()
1863 ret = PTR_ERR(spi->dma_tx); in stm32_spi_probe()
1864 spi->dma_tx = NULL; in stm32_spi_probe()
1870 master->dma_tx = spi->dma_tx; in stm32_spi_probe()
1873 spi->dma_rx = dma_request_chan(spi->dev, "rx"); in stm32_spi_probe()
1874 if (IS_ERR(spi->dma_rx)) { in stm32_spi_probe()
1875 ret = PTR_ERR(spi->dma_rx); in stm32_spi_probe()
1876 spi->dma_rx = NULL; in stm32_spi_probe()
1882 master->dma_rx = spi->dma_rx; in stm32_spi_probe()
1885 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
1897 dev_err(&pdev->dev, "spi master registration failed: %d\n", in stm32_spi_probe()
1915 if (spi->dma_tx) in stm32_spi_probe()
1916 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
1917 if (spi->dma_rx) in stm32_spi_probe()
1918 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
1920 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
1928 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_remove() local
1933 spi->cfg->disable(spi); in stm32_spi_remove()
1945 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
1956 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_runtime_suspend() local
1958 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
1966 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_runtime_resume() local
1973 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
1991 struct stm32_spi *spi = spi_master_get_devdata(master); in stm32_spi_resume() local
2000 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
2010 spi->cfg->config(spi); in stm32_spi_resume()
2037 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");