Lines Matching +full:controller +full:- +full:data
1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver (master mode only)
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
174 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
186 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
194 * @rx: SPI RX data register
195 * @tx: SPI TX data register
212 * struct stm32_spi_cfg - stm32 compatible configuration data
216 * @disable: routine to disable controller
217 * @config: routine to configure controller as SPI Master
223 * number of data (if driver has this functionality)
229 * @irq_handler_event: Interrupt handler for SPI controller events
230 * @irq_handler_thread: thread of interrupt handler for SPI controller
234 * @flags: compatible specific SPI controller flags used at registration time
247 void (*dma_rx_cb)(void *data);
248 void (*dma_tx_cb)(void *data);
259 * struct stm32_spi - private data of the SPI controller
260 * @dev: driver model representation of the controller
261 * @master: controller master interface
262 * @cfg: compatible configuration data
267 * @irq: SPI controller interrupt line
269 * @cur_midi: master inter-data idleness in ns
271 * @cur_bpw: number of bits in a single SPI data frame
272 * @cur_fthlv: fifo threshold level (data frames in a single data packet)
276 * @tx_buf: data to be written, or NULL
277 * @rx_buf: data to be read, or NULL
278 * @tx_len: number of data to be written in bytes
279 * @rx_len: number of data to be read in bytes
328 /* SPI data transfer is enabled but spi_ker_ck is idle.
349 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
350 spi->base + offset); in stm32_spi_set_bits()
356 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
357 spi->base + offset); in stm32_spi_clr_bits()
361 * stm32h7_spi_get_fifo_size - Return fifo size
362 * @spi: pointer to the spi controller data structure
369 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
373 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
374 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
378 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
380 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32h7_spi_get_fifo_size()
386 * stm32f4_spi_get_bpw_mask - Return bits per word mask
387 * @spi: pointer to the spi controller data structure
391 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32f4_spi_get_bpw_mask()
396 * stm32h7_spi_get_bpw_mask - Return bits per word mask
397 * @spi: pointer to the spi controller data structure
404 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
408 * maximum data size of periperal instances is limited to 16-bit in stm32h7_spi_get_bpw_mask()
412 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_get_bpw_mask()
415 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
417 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32h7_spi_get_bpw_mask()
423 * stm32_spi_prepare_mbr - Determine baud rate divisor value
424 * @spi: pointer to the spi controller data structure
429 * Return baud rate divisor value in case of success or -EINVAL
436 /* Ensure spi->clk_rate is even */ in stm32_spi_prepare_mbr()
437 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz); in stm32_spi_prepare_mbr()
440 * SPI framework set xfer->speed_hz to master->max_speed_hz if in stm32_spi_prepare_mbr()
441 * xfer->speed_hz is greater than master->max_speed_hz, and it returns in stm32_spi_prepare_mbr()
442 * an error when xfer->speed_hz is lower than master->min_speed_hz, so in stm32_spi_prepare_mbr()
447 return -EINVAL; in stm32_spi_prepare_mbr()
450 if (div & (div - 1)) in stm32_spi_prepare_mbr()
453 mbrdiv = fls(div) - 1; in stm32_spi_prepare_mbr()
455 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
457 return mbrdiv - 1; in stm32_spi_prepare_mbr()
461 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
462 * @spi: pointer to the spi controller data structure
469 /* data packet should not exceed 1/2 of fifo space */ in stm32h7_spi_prepare_fthlv()
470 packet = clamp(xfer_len, 1U, spi->fifo_size / 2); in stm32h7_spi_prepare_fthlv()
472 /* align packet size with data registers access */ in stm32h7_spi_prepare_fthlv()
473 bpw = DIV_ROUND_UP(spi->cur_bpw, 8); in stm32h7_spi_prepare_fthlv()
478 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
479 * @spi: pointer to the spi controller data structure
486 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_write_tx()
488 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f4_spi_write_tx()
490 if (spi->cur_bpw == 16) { in stm32f4_spi_write_tx()
491 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
493 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
494 spi->tx_len -= sizeof(u16); in stm32f4_spi_write_tx()
496 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
498 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); in stm32f4_spi_write_tx()
499 spi->tx_len -= sizeof(u8); in stm32f4_spi_write_tx()
503 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f4_spi_write_tx()
507 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
508 * @spi: pointer to the spi controller data structure
515 while ((spi->tx_len > 0) && in stm32h7_spi_write_txfifo()
516 (readl_relaxed(spi->base + STM32H7_SPI_SR) & in stm32h7_spi_write_txfifo()
518 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32h7_spi_write_txfifo()
520 if (spi->tx_len >= sizeof(u32)) { in stm32h7_spi_write_txfifo()
521 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
523 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
524 spi->tx_len -= sizeof(u32); in stm32h7_spi_write_txfifo()
525 } else if (spi->tx_len >= sizeof(u16)) { in stm32h7_spi_write_txfifo()
526 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
528 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
529 spi->tx_len -= sizeof(u16); in stm32h7_spi_write_txfifo()
531 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
533 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
534 spi->tx_len -= sizeof(u8); in stm32h7_spi_write_txfifo()
538 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32h7_spi_write_txfifo()
542 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
543 * @spi: pointer to the spi controller data structure
550 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & in stm32f4_spi_read_rx()
552 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f4_spi_read_rx()
554 if (spi->cur_bpw == 16) { in stm32f4_spi_read_rx()
555 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
557 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
558 spi->rx_len -= sizeof(u16); in stm32f4_spi_read_rx()
560 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
562 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_read_rx()
563 spi->rx_len -= sizeof(u8); in stm32f4_spi_read_rx()
567 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); in stm32f4_spi_read_rx()
571 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
572 * @spi: pointer to the spi controller data structure
579 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
582 while ((spi->rx_len > 0) && in stm32h7_spi_read_rxfifo()
586 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32h7_spi_read_rxfifo()
588 if ((spi->rx_len >= sizeof(u32)) || in stm32h7_spi_read_rxfifo()
590 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
592 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
593 spi->rx_len -= sizeof(u32); in stm32h7_spi_read_rxfifo()
594 } else if ((spi->rx_len >= sizeof(u16)) || in stm32h7_spi_read_rxfifo()
596 (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32h7_spi_read_rxfifo()
597 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
599 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
600 spi->rx_len -= sizeof(u16); in stm32h7_spi_read_rxfifo()
602 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
604 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
605 spi->rx_len -= sizeof(u8); in stm32h7_spi_read_rxfifo()
608 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
612 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n", in stm32h7_spi_read_rxfifo()
613 __func__, spi->rx_len, sr); in stm32h7_spi_read_rxfifo()
617 * stm32_spi_enable - Enable SPI controller
618 * @spi: pointer to the spi controller data structure
622 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
624 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, in stm32_spi_enable()
625 spi->cfg->regs->en.mask); in stm32_spi_enable()
629 * stm32f4_spi_disable - Disable SPI controller
630 * @spi: pointer to the spi controller data structure
637 dev_dbg(spi->dev, "disable controller\n"); in stm32f4_spi_disable()
639 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_disable()
641 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & in stm32f4_spi_disable()
643 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
653 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, in stm32f4_spi_disable()
656 dev_warn(spi->dev, "disabling condition timeout\n"); in stm32f4_spi_disable()
659 if (spi->cur_usedma && spi->dma_tx) in stm32f4_spi_disable()
660 dmaengine_terminate_all(spi->dma_tx); in stm32f4_spi_disable()
661 if (spi->cur_usedma && spi->dma_rx) in stm32f4_spi_disable()
662 dmaengine_terminate_all(spi->dma_rx); in stm32f4_spi_disable()
670 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_disable()
671 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_disable()
673 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_disable()
677 * stm32h7_spi_disable - Disable SPI controller
678 * @spi: pointer to the spi controller data structure
680 * RX-Fifo is flushed when SPI controller is disabled.
687 dev_dbg(spi->dev, "disable controller\n"); in stm32h7_spi_disable()
689 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_disable()
691 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
694 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
698 if (spi->cur_usedma && spi->dma_tx) in stm32h7_spi_disable()
699 dmaengine_terminate_all(spi->dma_tx); in stm32h7_spi_disable()
700 if (spi->cur_usedma && spi->dma_rx) in stm32h7_spi_disable()
701 dmaengine_terminate_all(spi->dma_rx); in stm32h7_spi_disable()
709 writel_relaxed(0, spi->base + STM32H7_SPI_IER); in stm32h7_spi_disable()
710 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_disable()
712 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
716 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
717 * @master: controller master interface
731 if (spi->cfg->has_fifo) in stm32_spi_can_dma()
732 dma_size = spi->fifo_size; in stm32_spi_can_dma()
736 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
737 (transfer->len > dma_size) ? "true" : "false"); in stm32_spi_can_dma()
739 return (transfer->len > dma_size); in stm32_spi_can_dma()
743 * stm32f4_spi_irq_event - Interrupt handler for SPI controller events
745 * @dev_id: SPI controller master interface
754 spin_lock(&spi->lock); in stm32f4_spi_irq_event()
756 sr = readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
763 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || in stm32f4_spi_irq_event()
764 spi->cur_comm == SPI_3WIRE_TX)) { in stm32f4_spi_irq_event()
770 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_irq_event()
771 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_irq_event()
772 spi->cur_comm == SPI_3WIRE_RX)) { in stm32f4_spi_irq_event()
779 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); in stm32f4_spi_irq_event()
780 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
785 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32f4_spi_irq_event()
788 readl_relaxed(spi->base + STM32F4_SPI_DR); in stm32f4_spi_irq_event()
789 readl_relaxed(spi->base + STM32F4_SPI_SR); in stm32f4_spi_irq_event()
801 if (spi->tx_buf) in stm32f4_spi_irq_event()
803 if (spi->tx_len == 0) in stm32f4_spi_irq_event()
809 if (spi->rx_len == 0) in stm32f4_spi_irq_event()
811 else if (spi->tx_buf)/* Load data for discontinuous mode */ in stm32f4_spi_irq_event()
822 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
826 spin_unlock(&spi->lock); in stm32f4_spi_irq_event()
831 * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller
833 * @dev_id: SPI controller master interface
847 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
849 * @dev_id: SPI controller master interface
859 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_irq_thread()
861 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_irq_thread()
862 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); in stm32h7_spi_irq_thread()
872 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP in stm32h7_spi_irq_thread()
873 * are set. So in case of Full-Duplex, need to poll TXP and RXP event. in stm32h7_spi_irq_thread()
875 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma) in stm32h7_spi_irq_thread()
879 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32h7_spi_irq_thread()
881 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
891 dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); in stm32h7_spi_irq_thread()
892 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
898 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
903 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32h7_spi_irq_thread()
908 dev_err(spi->dev, "Overrun: RX data lost\n"); in stm32h7_spi_irq_thread()
913 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
915 if (!spi->cur_usedma || in stm32h7_spi_irq_thread()
916 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)) in stm32h7_spi_irq_thread()
921 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32h7_spi_irq_thread()
925 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
928 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_irq_thread()
930 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
941 * stm32_spi_prepare_msg - set up the controller to transfer a single message
942 * @master: controller master interface
949 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
950 struct device_node *np = spi_dev->dev.of_node; in stm32_spi_prepare_msg()
954 /* SPI slave device may need time between data frames */ in stm32_spi_prepare_msg()
955 spi->cur_midi = 0; in stm32_spi_prepare_msg()
956 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
957 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
959 if (spi_dev->mode & SPI_CPOL) in stm32_spi_prepare_msg()
960 setb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
962 clrb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
964 if (spi_dev->mode & SPI_CPHA) in stm32_spi_prepare_msg()
965 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
967 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
969 if (spi_dev->mode & SPI_LSB_FIRST) in stm32_spi_prepare_msg()
970 setb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
972 clrb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
974 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", in stm32_spi_prepare_msg()
975 !!(spi_dev->mode & SPI_CPOL), in stm32_spi_prepare_msg()
976 !!(spi_dev->mode & SPI_CPHA), in stm32_spi_prepare_msg()
977 !!(spi_dev->mode & SPI_LSB_FIRST), in stm32_spi_prepare_msg()
978 !!(spi_dev->mode & SPI_CS_HIGH)); in stm32_spi_prepare_msg()
984 if (spi->cfg->set_number_of_data) { in stm32_spi_prepare_msg()
994 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
999 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & in stm32_spi_prepare_msg()
1001 spi->base + spi->cfg->regs->cpol.reg); in stm32_spi_prepare_msg()
1003 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
1009 * stm32f4_spi_dma_tx_cb - dma callback
1010 * @data: pointer to the spi controller data structure
1014 static void stm32f4_spi_dma_tx_cb(void *data) in stm32f4_spi_dma_tx_cb() argument
1016 struct stm32_spi *spi = data; in stm32f4_spi_dma_tx_cb()
1018 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_dma_tx_cb()
1019 spi_finalize_current_transfer(spi->master); in stm32f4_spi_dma_tx_cb()
1025 * stm32_spi_dma_rx_cb - dma callback
1026 * @data: pointer to the spi controller data structure
1030 static void stm32_spi_dma_rx_cb(void *data) in stm32_spi_dma_rx_cb() argument
1032 struct stm32_spi *spi = data; in stm32_spi_dma_rx_cb()
1034 spi_finalize_current_transfer(spi->master); in stm32_spi_dma_rx_cb()
1035 spi->cfg->disable(spi); in stm32_spi_dma_rx_cb()
1039 * stm32_spi_dma_config - configure dma slave channel depending on current
1041 * @spi: pointer to the spi controller data structure
1052 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
1054 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
1059 if (spi->cfg->has_fifo) { in stm32_spi_dma_config()
1061 if (spi->cur_fthlv == 2) in stm32_spi_dma_config()
1064 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
1070 dma_conf->direction = dir; in stm32_spi_dma_config()
1071 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ in stm32_spi_dma_config()
1072 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; in stm32_spi_dma_config()
1073 dma_conf->src_addr_width = buswidth; in stm32_spi_dma_config()
1074 dma_conf->src_maxburst = maxburst; in stm32_spi_dma_config()
1076 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1078 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ in stm32_spi_dma_config()
1079 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; in stm32_spi_dma_config()
1080 dma_conf->dst_addr_width = buswidth; in stm32_spi_dma_config()
1081 dma_conf->dst_maxburst = maxburst; in stm32_spi_dma_config()
1083 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1089 * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using
1091 * @spi: pointer to the spi controller data structure
1102 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32f4_spi_transfer_one_irq()
1104 } else if (spi->cur_comm == SPI_FULL_DUPLEX || in stm32f4_spi_transfer_one_irq()
1105 spi->cur_comm == SPI_SIMPLEX_RX || in stm32f4_spi_transfer_one_irq()
1106 spi->cur_comm == SPI_3WIRE_RX) { in stm32f4_spi_transfer_one_irq()
1107 /* In transmit-only mode, the OVR flag is set in the SR register in stm32f4_spi_transfer_one_irq()
1108 * since the received data are never read. Therefore set OVR in stm32f4_spi_transfer_one_irq()
1113 return -EINVAL; in stm32f4_spi_transfer_one_irq()
1116 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1122 /* starting data transfer when buffer is loaded */ in stm32f4_spi_transfer_one_irq()
1123 if (spi->tx_buf) in stm32f4_spi_transfer_one_irq()
1126 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_transfer_one_irq()
1132 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1134 * @spi: pointer to the spi controller data structure
1145 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32h7_spi_transfer_one_irq()
1147 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32h7_spi_transfer_one_irq()
1149 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32h7_spi_transfer_one_irq()
1156 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1160 /* Be sure to have data in fifo before starting data transfer */ in stm32h7_spi_transfer_one_irq()
1161 if (spi->tx_buf) in stm32h7_spi_transfer_one_irq()
1166 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); in stm32h7_spi_transfer_one_irq()
1168 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1174 * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start
1176 * @spi: pointer to the spi controller data structure
1181 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || in stm32f4_spi_transfer_one_dma_start()
1182 spi->cur_comm == SPI_FULL_DUPLEX) { in stm32f4_spi_transfer_one_dma_start()
1184 * In transmit-only mode, the OVR flag is set in the SR register in stm32f4_spi_transfer_one_dma_start()
1185 * since the received data are never read. Therefore set OVR in stm32f4_spi_transfer_one_dma_start()
1195 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1197 * @spi: pointer to the spi controller data structure
1204 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) in stm32h7_spi_transfer_one_dma_start()
1215 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1216 * @spi: pointer to the spi controller data structure
1229 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1232 if (spi->rx_buf && spi->dma_rx) { in stm32_spi_transfer_one_dma()
1234 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1237 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1238 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1241 spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
1242 xfer->rx_sg.nents, in stm32_spi_transfer_one_dma()
1248 if (spi->tx_buf && spi->dma_tx) { in stm32_spi_transfer_one_dma()
1250 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
1253 spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
1254 xfer->tx_sg.nents, in stm32_spi_transfer_one_dma()
1259 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
1260 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1263 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1267 rx_dma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1268 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1271 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1275 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
1279 if (spi->cur_comm == SPI_SIMPLEX_TX || in stm32_spi_transfer_one_dma()
1280 spi->cur_comm == SPI_3WIRE_TX) { in stm32_spi_transfer_one_dma()
1281 tx_dma_desc->callback = spi->cfg->dma_tx_cb; in stm32_spi_transfer_one_dma()
1282 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1286 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1290 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
1293 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, in stm32_spi_transfer_one_dma()
1294 spi->cfg->regs->dma_tx_en.mask); in stm32_spi_transfer_one_dma()
1297 spi->cfg->transfer_one_dma_start(spi); in stm32_spi_transfer_one_dma()
1299 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1304 if (spi->dma_rx) in stm32_spi_transfer_one_dma()
1305 dmaengine_terminate_all(spi->dma_rx); in stm32_spi_transfer_one_dma()
1308 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1309 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1311 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1313 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
1315 spi->cur_usedma = false; in stm32_spi_transfer_one_dma()
1316 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
1320 * stm32f4_spi_set_bpw - Configure bits per word
1321 * @spi: pointer to the spi controller data structure
1325 if (spi->cur_bpw == 16) in stm32f4_spi_set_bpw()
1332 * stm32h7_spi_set_bpw - configure bits per word
1333 * @spi: pointer to the spi controller data structure
1340 bpw = spi->cur_bpw - 1; in stm32h7_spi_set_bpw()
1345 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); in stm32h7_spi_set_bpw()
1346 fthlv = spi->cur_fthlv - 1; in stm32h7_spi_set_bpw()
1352 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & in stm32h7_spi_set_bpw()
1354 spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_set_bpw()
1358 * stm32_spi_set_mbr - Configure baud rate divisor in master mode
1359 * @spi: pointer to the spi controller data structure
1366 clrb |= spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1367 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1369 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & in stm32_spi_set_mbr()
1371 spi->base + spi->cfg->regs->br.reg); in stm32_spi_set_mbr()
1375 * stm32_spi_communication_type - return transfer communication type
1384 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ in stm32_spi_communication_type()
1386 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL in stm32_spi_communication_type()
1391 if (!transfer->tx_buf) in stm32_spi_communication_type()
1396 if (!transfer->tx_buf) in stm32_spi_communication_type()
1398 else if (!transfer->rx_buf) in stm32_spi_communication_type()
1406 * stm32f4_spi_set_mode - configure communication mode
1407 * @spi: pointer to the spi controller data structure
1427 return -EINVAL; in stm32f4_spi_set_mode()
1434 * stm32h7_spi_set_mode - configure communication mode
1435 * @spi: pointer to the spi controller data structure
1461 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_set_mode()
1463 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_set_mode()
1469 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1470 * consecutive data frames in master mode
1471 * @spi: pointer to the spi controller data structure
1479 if ((len > 1) && (spi->cur_midi > 0)) { in stm32h7_spi_data_idleness()
1480 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed); in stm32h7_spi_data_idleness()
1482 DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32h7_spi_data_idleness()
1487 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32h7_spi_data_idleness()
1492 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_data_idleness()
1494 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_data_idleness()
1498 * stm32h7_spi_number_of_data - configure number of data at current transfer
1499 * @spi: pointer to the spi controller data structure
1506 spi->base + STM32H7_SPI_CR2); in stm32h7_spi_number_of_data()
1508 return -EMSGSIZE; in stm32h7_spi_number_of_data()
1515 * stm32_spi_transfer_one_setup - common setup to transfer a single
1518 * @spi: pointer to the spi controller data structure
1531 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1533 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
1535 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
1536 spi->cfg->set_bpw(spi); in stm32_spi_transfer_one_setup()
1538 /* Update spi->cur_speed with real clock speed */ in stm32_spi_transfer_one_setup()
1539 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, in stm32_spi_transfer_one_setup()
1540 spi->cfg->baud_rate_div_min, in stm32_spi_transfer_one_setup()
1541 spi->cfg->baud_rate_div_max); in stm32_spi_transfer_one_setup()
1547 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
1551 ret = spi->cfg->set_mode(spi, comm_type); in stm32_spi_transfer_one_setup()
1555 spi->cur_comm = comm_type; in stm32_spi_transfer_one_setup()
1557 if (spi->cfg->set_data_idleness) in stm32_spi_transfer_one_setup()
1558 spi->cfg->set_data_idleness(spi, transfer->len); in stm32_spi_transfer_one_setup()
1560 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
1561 nb_words = transfer->len; in stm32_spi_transfer_one_setup()
1562 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
1563 nb_words = DIV_ROUND_UP(transfer->len * 8, 16); in stm32_spi_transfer_one_setup()
1565 nb_words = DIV_ROUND_UP(transfer->len * 8, 32); in stm32_spi_transfer_one_setup()
1567 if (spi->cfg->set_number_of_data) { in stm32_spi_transfer_one_setup()
1568 ret = spi->cfg->set_number_of_data(spi, nb_words); in stm32_spi_transfer_one_setup()
1573 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
1574 spi->cur_comm); in stm32_spi_transfer_one_setup()
1575 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
1576 "data frame of %d-bit, data packet of %d data frames\n", in stm32_spi_transfer_one_setup()
1577 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
1578 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
1579 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
1580 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
1581 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
1582 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
1585 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1591 * stm32_spi_transfer_one - transfer a single spi_transfer
1592 * @master: controller master interface
1606 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
1607 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
1608 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1609 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
1611 spi->cur_usedma = (master->can_dma && in stm32_spi_transfer_one()
1612 master->can_dma(master, spi_dev, transfer)); in stm32_spi_transfer_one()
1616 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
1620 if (spi->cur_usedma) in stm32_spi_transfer_one()
1623 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one()
1627 * stm32_spi_unprepare_msg - relax the hardware
1628 * @master: controller master interface
1636 spi->cfg->disable(spi); in stm32_spi_unprepare_msg()
1642 * stm32f4_spi_config - Configure SPI controller as SPI master
1643 * @spi: pointer to the spi controller data structure
1649 spin_lock_irqsave(&spi->lock, flags); in stm32f4_spi_config()
1656 * - SS input value high in stm32f4_spi_config()
1657 * - transmitter half duplex direction in stm32f4_spi_config()
1658 * - Set the master mode (default Motorola mode) in stm32f4_spi_config()
1659 * - Consider 1 master/n slaves configuration and in stm32f4_spi_config()
1667 spin_unlock_irqrestore(&spi->lock, flags); in stm32f4_spi_config()
1673 * stm32h7_spi_config - Configure SPI controller as SPI master
1674 * @spi: pointer to the spi controller data structure
1680 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_config()
1687 * - SS input value high in stm32h7_spi_config()
1688 * - transmitter half duplex direction in stm32h7_spi_config()
1689 * - automatic communication suspend when RX-Fifo is full in stm32h7_spi_config()
1696 * - Set the master mode (default Motorola mode) in stm32h7_spi_config()
1697 * - Consider 1 master/n slaves configuration and in stm32h7_spi_config()
1699 * - keep control of all associated GPIOs in stm32h7_spi_config()
1705 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_config()
1753 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1754 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1767 master = devm_spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi)); in stm32_spi_probe()
1769 dev_err(&pdev->dev, "spi master allocation failed\n"); in stm32_spi_probe()
1770 return -ENOMEM; in stm32_spi_probe()
1775 spi->dev = &pdev->dev; in stm32_spi_probe()
1776 spi->master = master; in stm32_spi_probe()
1777 spin_lock_init(&spi->lock); in stm32_spi_probe()
1779 spi->cfg = (const struct stm32_spi_cfg *) in stm32_spi_probe()
1780 of_match_device(pdev->dev.driver->of_match_table, in stm32_spi_probe()
1781 &pdev->dev)->data; in stm32_spi_probe()
1784 spi->base = devm_ioremap_resource(&pdev->dev, res); in stm32_spi_probe()
1785 if (IS_ERR(spi->base)) in stm32_spi_probe()
1786 return PTR_ERR(spi->base); in stm32_spi_probe()
1788 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
1790 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
1791 if (spi->irq <= 0) in stm32_spi_probe()
1792 return dev_err_probe(&pdev->dev, spi->irq, in stm32_spi_probe()
1795 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, in stm32_spi_probe()
1796 spi->cfg->irq_handler_event, in stm32_spi_probe()
1797 spi->cfg->irq_handler_thread, in stm32_spi_probe()
1798 IRQF_ONESHOT, pdev->name, master); in stm32_spi_probe()
1800 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
1805 spi->clk = devm_clk_get(&pdev->dev, NULL); in stm32_spi_probe()
1806 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
1807 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
1808 dev_err(&pdev->dev, "clk get failed: %d\n", ret); in stm32_spi_probe()
1812 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
1814 dev_err(&pdev->dev, "clk enable failed: %d\n", ret); in stm32_spi_probe()
1817 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
1818 if (!spi->clk_rate) { in stm32_spi_probe()
1819 dev_err(&pdev->dev, "clk rate = 0\n"); in stm32_spi_probe()
1820 ret = -EINVAL; in stm32_spi_probe()
1824 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in stm32_spi_probe()
1827 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), in stm32_spi_probe()
1837 if (spi->cfg->has_fifo) in stm32_spi_probe()
1838 spi->fifo_size = spi->cfg->get_fifo_size(spi); in stm32_spi_probe()
1840 ret = spi->cfg->config(spi); in stm32_spi_probe()
1842 dev_err(&pdev->dev, "controller configuration failed: %d\n", in stm32_spi_probe()
1847 master->dev.of_node = pdev->dev.of_node; in stm32_spi_probe()
1848 master->auto_runtime_pm = true; in stm32_spi_probe()
1849 master->bus_num = pdev->id; in stm32_spi_probe()
1850 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | in stm32_spi_probe()
1852 master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); in stm32_spi_probe()
1853 master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; in stm32_spi_probe()
1854 master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; in stm32_spi_probe()
1855 master->use_gpio_descriptors = true; in stm32_spi_probe()
1856 master->prepare_message = stm32_spi_prepare_msg; in stm32_spi_probe()
1857 master->transfer_one = stm32_spi_transfer_one; in stm32_spi_probe()
1858 master->unprepare_message = stm32_spi_unprepare_msg; in stm32_spi_probe()
1859 master->flags = spi->cfg->flags; in stm32_spi_probe()
1861 spi->dma_tx = dma_request_chan(spi->dev, "tx"); in stm32_spi_probe()
1862 if (IS_ERR(spi->dma_tx)) { in stm32_spi_probe()
1863 ret = PTR_ERR(spi->dma_tx); in stm32_spi_probe()
1864 spi->dma_tx = NULL; in stm32_spi_probe()
1865 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
1868 dev_warn(&pdev->dev, "failed to request tx dma channel\n"); in stm32_spi_probe()
1870 master->dma_tx = spi->dma_tx; in stm32_spi_probe()
1873 spi->dma_rx = dma_request_chan(spi->dev, "rx"); in stm32_spi_probe()
1874 if (IS_ERR(spi->dma_rx)) { in stm32_spi_probe()
1875 ret = PTR_ERR(spi->dma_rx); in stm32_spi_probe()
1876 spi->dma_rx = NULL; in stm32_spi_probe()
1877 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
1880 dev_warn(&pdev->dev, "failed to request rx dma channel\n"); in stm32_spi_probe()
1882 master->dma_rx = spi->dma_rx; in stm32_spi_probe()
1885 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
1886 master->can_dma = stm32_spi_can_dma; in stm32_spi_probe()
1888 pm_runtime_set_autosuspend_delay(&pdev->dev, in stm32_spi_probe()
1890 pm_runtime_use_autosuspend(&pdev->dev); in stm32_spi_probe()
1891 pm_runtime_set_active(&pdev->dev); in stm32_spi_probe()
1892 pm_runtime_get_noresume(&pdev->dev); in stm32_spi_probe()
1893 pm_runtime_enable(&pdev->dev); in stm32_spi_probe()
1897 dev_err(&pdev->dev, "spi master registration failed: %d\n", in stm32_spi_probe()
1902 pm_runtime_mark_last_busy(&pdev->dev); in stm32_spi_probe()
1903 pm_runtime_put_autosuspend(&pdev->dev); in stm32_spi_probe()
1905 dev_info(&pdev->dev, "driver initialized\n"); in stm32_spi_probe()
1910 pm_runtime_disable(&pdev->dev); in stm32_spi_probe()
1911 pm_runtime_put_noidle(&pdev->dev); in stm32_spi_probe()
1912 pm_runtime_set_suspended(&pdev->dev); in stm32_spi_probe()
1913 pm_runtime_dont_use_autosuspend(&pdev->dev); in stm32_spi_probe()
1915 if (spi->dma_tx) in stm32_spi_probe()
1916 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
1917 if (spi->dma_rx) in stm32_spi_probe()
1918 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
1920 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
1930 pm_runtime_get_sync(&pdev->dev); in stm32_spi_remove()
1933 spi->cfg->disable(spi); in stm32_spi_remove()
1935 pm_runtime_disable(&pdev->dev); in stm32_spi_remove()
1936 pm_runtime_put_noidle(&pdev->dev); in stm32_spi_remove()
1937 pm_runtime_set_suspended(&pdev->dev); in stm32_spi_remove()
1938 pm_runtime_dont_use_autosuspend(&pdev->dev); in stm32_spi_remove()
1940 if (master->dma_tx) in stm32_spi_remove()
1941 dma_release_channel(master->dma_tx); in stm32_spi_remove()
1942 if (master->dma_rx) in stm32_spi_remove()
1943 dma_release_channel(master->dma_rx); in stm32_spi_remove()
1945 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
1948 pinctrl_pm_select_sleep_state(&pdev->dev); in stm32_spi_remove()
1958 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
1973 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
2000 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
2010 spi->cfg->config(spi); in stm32_spi_resume()
2037 MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver");