Lines Matching +full:clock +full:- +full:master
1 // SPDX-License-Identifier: GPL-2.0
5 // SiFive SPI controller driver (master mode only)
26 #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
27 #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
93 struct clk *clk; /* bus clock */
96 struct completion done; /* wake-up from interrupt */
101 iowrite32(value, spi->regs + offset); in sifive_spi_write()
106 return ioread32(spi->regs + offset); in sifive_spi_read()
126 /* Exit specialized memory-mapped SPI flash mode */ in sifive_spi_init()
131 sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg) in sifive_spi_prepare_message() argument
133 struct sifive_spi *spi = spi_master_get_devdata(master); in sifive_spi_prepare_message()
134 struct spi_device *device = msg->spi; in sifive_spi_prepare_message()
137 if (device->mode & SPI_CS_HIGH) in sifive_spi_prepare_message()
138 spi->cs_inactive &= ~BIT(device->chip_select); in sifive_spi_prepare_message()
140 spi->cs_inactive |= BIT(device->chip_select); in sifive_spi_prepare_message()
141 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive); in sifive_spi_prepare_message()
144 sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, device->chip_select); in sifive_spi_prepare_message()
146 /* Set clock mode */ in sifive_spi_prepare_message()
148 device->mode & SIFIVE_SPI_SCKMODE_MODE_MASK); in sifive_spi_prepare_message()
155 struct sifive_spi *spi = spi_master_get_devdata(device->master); in sifive_spi_set_cs()
158 if (device->mode & SPI_CS_HIGH) in sifive_spi_set_cs()
173 /* Calculate and program the clock rate */ in sifive_spi_prep_transfer()
174 cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1; in sifive_spi_prep_transfer()
178 mode = max_t(unsigned int, t->rx_nbits, t->tx_nbits); in sifive_spi_prep_transfer()
181 cr = SIFIVE_SPI_FMT_LEN(t->bits_per_word); in sifive_spi_prep_transfer()
193 if (device->mode & SPI_LSB_FIRST) in sifive_spi_prep_transfer()
195 if (!t->rx_buf) in sifive_spi_prep_transfer()
202 * (8/mode) * fifo_depth / hz <= 5 * 10^-6 in sifive_spi_prep_transfer()
205 return 1600000 * spi->fifo_depth <= t->speed_hz * mode; in sifive_spi_prep_transfer()
216 complete(&spi->done); in sifive_spi_irq()
232 reinit_completion(&spi->done); in sifive_spi_wait()
234 wait_for_completion(&spi->done); in sifive_spi_wait()
255 sifive_spi_transfer_one(struct spi_master *master, struct spi_device *device, in sifive_spi_transfer_one() argument
258 struct sifive_spi *spi = spi_master_get_devdata(master); in sifive_spi_transfer_one()
260 const u8 *tx_ptr = t->tx_buf; in sifive_spi_transfer_one()
261 u8 *rx_ptr = t->rx_buf; in sifive_spi_transfer_one()
262 unsigned int remaining_words = t->len; in sifive_spi_transfer_one()
265 unsigned int n_words = min(remaining_words, spi->fifo_depth); in sifive_spi_transfer_one()
275 n_words - 1); in sifive_spi_transfer_one()
286 remaining_words -= n_words; in sifive_spi_transfer_one()
297 struct spi_master *master; in sifive_spi_probe() local
299 master = spi_alloc_master(&pdev->dev, sizeof(struct sifive_spi)); in sifive_spi_probe()
300 if (!master) { in sifive_spi_probe()
301 dev_err(&pdev->dev, "out of memory\n"); in sifive_spi_probe()
302 return -ENOMEM; in sifive_spi_probe()
305 spi = spi_master_get_devdata(master); in sifive_spi_probe()
306 init_completion(&spi->done); in sifive_spi_probe()
307 platform_set_drvdata(pdev, master); in sifive_spi_probe()
309 spi->regs = devm_platform_ioremap_resource(pdev, 0); in sifive_spi_probe()
310 if (IS_ERR(spi->regs)) { in sifive_spi_probe()
311 ret = PTR_ERR(spi->regs); in sifive_spi_probe()
315 spi->clk = devm_clk_get(&pdev->dev, NULL); in sifive_spi_probe()
316 if (IS_ERR(spi->clk)) { in sifive_spi_probe()
317 dev_err(&pdev->dev, "Unable to find bus clock\n"); in sifive_spi_probe()
318 ret = PTR_ERR(spi->clk); in sifive_spi_probe()
330 of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth", in sifive_spi_probe()
331 &spi->fifo_depth); in sifive_spi_probe()
333 spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH; in sifive_spi_probe()
336 of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word", in sifive_spi_probe()
340 dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n"); in sifive_spi_probe()
341 ret = -EINVAL; in sifive_spi_probe()
345 /* Spin up the bus clock before hitting registers */ in sifive_spi_probe()
346 ret = clk_prepare_enable(spi->clk); in sifive_spi_probe()
348 dev_err(&pdev->dev, "Unable to enable bus clock\n"); in sifive_spi_probe()
353 spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF); in sifive_spi_probe()
356 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive); in sifive_spi_probe()
358 dev_err(&pdev->dev, "Could not auto probe CS lines\n"); in sifive_spi_probe()
359 ret = -EINVAL; in sifive_spi_probe()
365 dev_err(&pdev->dev, "Invalid number of spi slaves\n"); in sifive_spi_probe()
366 ret = -EINVAL; in sifive_spi_probe()
370 /* Define our master */ in sifive_spi_probe()
371 master->dev.of_node = pdev->dev.of_node; in sifive_spi_probe()
372 master->bus_num = pdev->id; in sifive_spi_probe()
373 master->num_chipselect = num_cs; in sifive_spi_probe()
374 master->mode_bits = SPI_CPHA | SPI_CPOL in sifive_spi_probe()
379 * we need to "left-align" the bits (unless SPI_LSB_FIRST) in sifive_spi_probe()
381 master->bits_per_word_mask = SPI_BPW_MASK(8); in sifive_spi_probe()
382 master->flags = SPI_CONTROLLER_MUST_TX | SPI_MASTER_GPIO_SS; in sifive_spi_probe()
383 master->prepare_message = sifive_spi_prepare_message; in sifive_spi_probe()
384 master->set_cs = sifive_spi_set_cs; in sifive_spi_probe()
385 master->transfer_one = sifive_spi_transfer_one; in sifive_spi_probe()
387 pdev->dev.dma_mask = NULL; in sifive_spi_probe()
388 /* Configure the SPI master hardware */ in sifive_spi_probe()
392 ret = devm_request_irq(&pdev->dev, irq, sifive_spi_irq, 0, in sifive_spi_probe()
393 dev_name(&pdev->dev), spi); in sifive_spi_probe()
395 dev_err(&pdev->dev, "Unable to bind to interrupt\n"); in sifive_spi_probe()
399 dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n", in sifive_spi_probe()
400 irq, master->num_chipselect); in sifive_spi_probe()
402 ret = devm_spi_register_master(&pdev->dev, master); in sifive_spi_probe()
404 dev_err(&pdev->dev, "spi_register_master failed\n"); in sifive_spi_probe()
411 clk_disable_unprepare(spi->clk); in sifive_spi_probe()
413 spi_master_put(master); in sifive_spi_probe()
420 struct spi_master *master = platform_get_drvdata(pdev); in sifive_spi_remove() local
421 struct sifive_spi *spi = spi_master_get_devdata(master); in sifive_spi_remove()
425 clk_disable_unprepare(spi->clk); in sifive_spi_remove()
432 struct spi_master *master = dev_get_drvdata(dev); in sifive_spi_suspend() local
433 struct sifive_spi *spi = spi_master_get_devdata(master); in sifive_spi_suspend()
436 ret = spi_master_suspend(master); in sifive_spi_suspend()
443 clk_disable_unprepare(spi->clk); in sifive_spi_suspend()
450 struct spi_master *master = dev_get_drvdata(dev); in sifive_spi_resume() local
451 struct sifive_spi *spi = spi_master_get_devdata(master); in sifive_spi_resume()
454 ret = clk_prepare_enable(spi->clk); in sifive_spi_resume()
457 ret = spi_master_resume(master); in sifive_spi_resume()
459 clk_disable_unprepare(spi->clk); in sifive_spi_resume()