100 #define SIMDR2_BITLEN1(i)	(((i) - 1) << 24) /* Data Size (8-32 bits) */
105 #define SISCR_BRPS_MASK		GENMASK(12, 8)	/* Prescaler Setting (1-32) */
138 #define SIFCTR_TFWM_32		(1 << 29)	/*  Transfer Request when 32 empty stages */
153 #define SIFCTR_RFWM_32		(4 << 13)	/*  Transfer Request when 32 valid stages */
279 		if (!div_pow && div <= 32 && div > 2)  in sh_msiof_spi_set_clk_regs()
287 		for (; brps > 32; div_pow++)  in sh_msiof_spi_set_clk_regs()
290 		/* Set transfer rate composite divisor to 2^5 * 32 = 1024 */  in sh_msiof_spi_set_clk_regs()
294 		brps = 32;  in sh_msiof_spi_set_clk_regs()
415 	int k;  in sh_msiof_spi_write_fifo_8()  local
417 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_8()
418 		sh_msiof_write(p, SITFDR, buf_8[k] << fs);  in sh_msiof_spi_write_fifo_8()
425 	int k;  in sh_msiof_spi_write_fifo_16()  local
427 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_16()
428 		sh_msiof_write(p, SITFDR, buf_16[k] << fs);  in sh_msiof_spi_write_fifo_16()
435 	int k;  in sh_msiof_spi_write_fifo_16u()  local
437 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_16u()
438 		sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs);  in sh_msiof_spi_write_fifo_16u()
445 	int k;  in sh_msiof_spi_write_fifo_32()  local
447 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_32()
448 		sh_msiof_write(p, SITFDR, buf_32[k] << fs);  in sh_msiof_spi_write_fifo_32()
455 	int k;  in sh_msiof_spi_write_fifo_32u()  local
457 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_32u()
458 		sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs);  in sh_msiof_spi_write_fifo_32u()
465 	int k;  in sh_msiof_spi_write_fifo_s32()  local
467 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_s32()
468 		sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs));  in sh_msiof_spi_write_fifo_s32()
475 	int k;  in sh_msiof_spi_write_fifo_s32u()  local
477 	for (k = 0; k < words; k++)  in sh_msiof_spi_write_fifo_s32u()
478 		sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs));  in sh_msiof_spi_write_fifo_s32u()
485 	int k;  in sh_msiof_spi_read_fifo_8()  local
487 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_8()
488 		buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs;  in sh_msiof_spi_read_fifo_8()
495 	int k;  in sh_msiof_spi_read_fifo_16()  local
497 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_16()
498 		buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs;  in sh_msiof_spi_read_fifo_16()
505 	int k;  in sh_msiof_spi_read_fifo_16u()  local
507 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_16u()
508 		put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]);  in sh_msiof_spi_read_fifo_16u()
515 	int k;  in sh_msiof_spi_read_fifo_32()  local
517 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_32()
518 		buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs;  in sh_msiof_spi_read_fifo_32()
525 	int k;  in sh_msiof_spi_read_fifo_32u()  local
527 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_32u()
528 		put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]);  in sh_msiof_spi_read_fifo_32u()
535 	int k;  in sh_msiof_spi_read_fifo_s32()  local
537 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_s32()
538 		buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs);  in sh_msiof_spi_read_fifo_s32()
545 	int k;  in sh_msiof_spi_read_fifo_s32u()  local
547 	for (k = 0; k < words; k++)  in sh_msiof_spi_read_fifo_s32u()
548 		put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]);  in sh_msiof_spi_read_fifo_s32u()
689 	fifo_shift = 32 - bits;  in sh_msiof_spi_txrx_once()
792 	/* setup msiof transfer mode registers (32-bit words) */  in sh_msiof_dma_once()
793 	sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);  in sh_msiof_dma_once()
934 		 *  DMA supports 32-bit words only, hence pack 8-bit and 16-bit  in sh_msiof_transfer_one()
977 		bits = 32;  in sh_msiof_transfer_one()
1051 	.bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32),
1060 			      SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1069 			      SPI_BPW_MASK(24) | SPI_BPW_MASK(32),