Lines Matching +full:qup +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2008-2014, The Linux foundation. All rights reserved.
19 #include <linux/dma-mapping.h>
116 #define SPI_MAX_XFER (SZ_64K - 64)
158 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
174 return controller->n_words * controller->w_size; in spi_qup_len()
179 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
195 return -EIO; in spi_qup_set_state()
199 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
202 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
209 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
210 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
214 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
223 return -EIO; in spi_qup_set_state()
231 u8 *rx_buf = controller->rx_buf; in spi_qup_read_from_fifo()
235 for (; num_words; num_words--) { in spi_qup_read_from_fifo()
237 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); in spi_qup_read_from_fifo()
239 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_read_from_fifo()
240 controller->rx_bytes, in spi_qup_read_from_fifo()
241 controller->w_size); in spi_qup_read_from_fifo()
244 controller->rx_bytes += num_bytes; in spi_qup_read_from_fifo()
248 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) { in spi_qup_read_from_fifo()
256 shift *= (controller->w_size - i - 1); in spi_qup_read_from_fifo()
257 rx_buf[controller->rx_bytes] = word >> shift; in spi_qup_read_from_fifo()
265 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_read()
267 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes, in spi_qup_read()
268 controller->w_size); in spi_qup_read()
269 words_per_block = controller->in_blk_sz >> 2; in spi_qup_read()
274 controller->base + QUP_OPERATIONAL); in spi_qup_read()
293 remainder -= num_words; in spi_qup_read()
310 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_read()
313 controller->base + QUP_OPERATIONAL); in spi_qup_read()
319 const u8 *tx_buf = controller->tx_buf; in spi_qup_write_to_fifo()
323 for (; num_words; num_words--) { in spi_qup_write_to_fifo()
326 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_write_to_fifo()
327 controller->tx_bytes, in spi_qup_write_to_fifo()
328 controller->w_size); in spi_qup_write_to_fifo()
331 data = tx_buf[controller->tx_bytes + i]; in spi_qup_write_to_fifo()
332 word |= data << (BITS_PER_BYTE * (3 - i)); in spi_qup_write_to_fifo()
335 controller->tx_bytes += num_bytes; in spi_qup_write_to_fifo()
337 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); in spi_qup_write_to_fifo()
343 struct spi_qup *qup = data; in spi_qup_dma_done() local
345 complete(&qup->done); in spi_qup_dma_done()
350 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_write()
353 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes, in spi_qup_write()
354 controller->w_size); in spi_qup_write()
355 words_per_block = controller->out_blk_sz >> 2; in spi_qup_write()
360 controller->base + QUP_OPERATIONAL); in spi_qup_write()
379 remainder -= num_words; in spi_qup_write()
393 struct spi_qup *qup = spi_master_get_devdata(master); in spi_qup_prep_sg() local
400 chan = master->dma_tx; in spi_qup_prep_sg()
402 chan = master->dma_rx; in spi_qup_prep_sg()
406 return desc ? PTR_ERR(desc) : -EINVAL; in spi_qup_prep_sg()
408 desc->callback = callback; in spi_qup_prep_sg()
409 desc->callback_param = qup; in spi_qup_prep_sg()
419 if (xfer->tx_buf) in spi_qup_dma_terminate()
420 dmaengine_terminate_all(master->dma_tx); in spi_qup_dma_terminate()
421 if (xfer->rx_buf) in spi_qup_dma_terminate()
422 dmaengine_terminate_all(master->dma_rx); in spi_qup_dma_terminate()
449 struct spi_master *master = spi->master; in spi_qup_do_dma()
450 struct spi_qup *qup = spi_master_get_devdata(master); in spi_qup_do_dma() local
454 if (xfer->rx_buf) in spi_qup_do_dma()
456 else if (xfer->tx_buf) in spi_qup_do_dma()
459 rx_sgl = xfer->rx_sg.sgl; in spi_qup_do_dma()
460 tx_sgl = xfer->tx_sg.sgl; in spi_qup_do_dma()
466 qup->n_words = spi_qup_sgl_get_nents_len(rx_sgl, in spi_qup_do_dma()
467 SPI_MAX_XFER, &rx_nents) / qup->w_size; in spi_qup_do_dma()
469 qup->n_words = spi_qup_sgl_get_nents_len(tx_sgl, in spi_qup_do_dma()
470 SPI_MAX_XFER, &tx_nents) / qup->w_size; in spi_qup_do_dma()
471 if (!qup->n_words) in spi_qup_do_dma()
472 return -EIO; in spi_qup_do_dma()
478 /* before issuing the descriptors, set the QUP to run */ in spi_qup_do_dma()
479 ret = spi_qup_set_state(qup, QUP_STATE_RUN); in spi_qup_do_dma()
481 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_dma()
489 dma_async_issue_pending(master->dma_rx); in spi_qup_do_dma()
498 dma_async_issue_pending(master->dma_tx); in spi_qup_do_dma()
501 if (!wait_for_completion_timeout(&qup->done, timeout)) in spi_qup_do_dma()
502 return -ETIMEDOUT; in spi_qup_do_dma()
504 for (; rx_sgl && rx_nents--; rx_sgl = sg_next(rx_sgl)) in spi_qup_do_dma()
506 for (; tx_sgl && tx_nents--; tx_sgl = sg_next(tx_sgl)) in spi_qup_do_dma()
517 struct spi_master *master = spi->master; in spi_qup_do_pio()
518 struct spi_qup *qup = spi_master_get_devdata(master); in spi_qup_do_pio() local
521 n_words = qup->n_words; in spi_qup_do_pio()
523 qup->rx_buf = xfer->rx_buf; in spi_qup_do_pio()
524 qup->tx_buf = xfer->tx_buf; in spi_qup_do_pio()
528 qup->n_words = SPI_MAX_XFER; in spi_qup_do_pio()
530 qup->n_words = n_words % SPI_MAX_XFER; in spi_qup_do_pio()
532 if (qup->tx_buf && offset) in spi_qup_do_pio()
533 qup->tx_buf = xfer->tx_buf + offset * SPI_MAX_XFER; in spi_qup_do_pio()
535 if (qup->rx_buf && offset) in spi_qup_do_pio()
536 qup->rx_buf = xfer->rx_buf + offset * SPI_MAX_XFER; in spi_qup_do_pio()
542 if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32))) in spi_qup_do_pio()
543 qup->mode = QUP_IO_M_MODE_FIFO; in spi_qup_do_pio()
549 ret = spi_qup_set_state(qup, QUP_STATE_RUN); in spi_qup_do_pio()
551 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_pio()
555 ret = spi_qup_set_state(qup, QUP_STATE_PAUSE); in spi_qup_do_pio()
557 dev_warn(qup->dev, "cannot set PAUSE state\n"); in spi_qup_do_pio()
561 if (qup->mode == QUP_IO_M_MODE_FIFO) in spi_qup_do_pio()
562 spi_qup_write(qup); in spi_qup_do_pio()
564 ret = spi_qup_set_state(qup, QUP_STATE_RUN); in spi_qup_do_pio()
566 dev_warn(qup->dev, "cannot set RUN state\n"); in spi_qup_do_pio()
570 if (!wait_for_completion_timeout(&qup->done, timeout)) in spi_qup_do_pio()
571 return -ETIMEDOUT; in spi_qup_do_pio()
574 } while (iterations--); in spi_qup_do_pio()
583 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
584 controller->tx_bytes, controller->w_size); in spi_qup_data_pending()
586 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
587 controller->rx_bytes, controller->w_size); in spi_qup_data_pending()
598 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
599 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
600 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
602 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
603 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
607 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); in spi_qup_qup_irq()
609 dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
611 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
613 dev_warn(controller->dev, "INPUT_OVER_RUN\n"); in spi_qup_qup_irq()
615 error = -EIO; in spi_qup_qup_irq()
620 dev_warn(controller->dev, "CLK_OVER_RUN\n"); in spi_qup_qup_irq()
622 dev_warn(controller->dev, "CLK_UNDER_RUN\n"); in spi_qup_qup_irq()
624 error = -EIO; in spi_qup_qup_irq()
627 spin_lock(&controller->lock); in spi_qup_qup_irq()
628 if (!controller->error) in spi_qup_qup_irq()
629 controller->error = error; in spi_qup_qup_irq()
630 spin_unlock(&controller->lock); in spi_qup_qup_irq()
632 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
633 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
642 complete(&controller->done); in spi_qup_qup_irq()
646 complete(&controller->done); in spi_qup_qup_irq()
649 if (!spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
653 complete(&controller->done); in spi_qup_qup_irq()
662 struct spi_qup *controller = spi_master_get_devdata(spi->master); in spi_qup_io_prep()
665 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { in spi_qup_io_prep()
666 dev_err(controller->dev, "too big size for loopback %d > %d\n", in spi_qup_io_prep()
667 xfer->len, controller->in_fifo_sz); in spi_qup_io_prep()
668 return -EIO; in spi_qup_io_prep()
671 ret = clk_set_rate(controller->cclk, xfer->speed_hz); in spi_qup_io_prep()
673 dev_err(controller->dev, "fail to set frequency %d", in spi_qup_io_prep()
674 xfer->speed_hz); in spi_qup_io_prep()
675 return -EIO; in spi_qup_io_prep()
678 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_io_prep()
679 controller->n_words = xfer->len / controller->w_size; in spi_qup_io_prep()
681 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) in spi_qup_io_prep()
682 controller->mode = QUP_IO_M_MODE_FIFO; in spi_qup_io_prep()
683 else if (spi->master->can_dma && in spi_qup_io_prep()
684 spi->master->can_dma(spi->master, spi, xfer) && in spi_qup_io_prep()
685 spi->master->cur_msg_mapped) in spi_qup_io_prep()
686 controller->mode = QUP_IO_M_MODE_BAM; in spi_qup_io_prep()
688 controller->mode = QUP_IO_M_MODE_BLOCK; in spi_qup_io_prep()
693 /* prep qup for another spi transaction of specific type */
696 struct spi_qup *controller = spi_master_get_devdata(spi->master); in spi_qup_io_config()
697 u32 config, iomode, control; in spi_qup_io_config() local
700 spin_lock_irqsave(&controller->lock, flags); in spi_qup_io_config()
701 controller->xfer = xfer; in spi_qup_io_config()
702 controller->error = 0; in spi_qup_io_config()
703 controller->rx_bytes = 0; in spi_qup_io_config()
704 controller->tx_bytes = 0; in spi_qup_io_config()
705 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_io_config()
709 dev_err(controller->dev, "cannot set RESET state\n"); in spi_qup_io_config()
710 return -EIO; in spi_qup_io_config()
713 switch (controller->mode) { in spi_qup_io_config()
715 writel_relaxed(controller->n_words, in spi_qup_io_config()
716 controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
717 writel_relaxed(controller->n_words, in spi_qup_io_config()
718 controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
720 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
721 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
724 writel_relaxed(controller->n_words, in spi_qup_io_config()
725 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
726 writel_relaxed(controller->n_words, in spi_qup_io_config()
727 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
729 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
730 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
732 if (!controller->qup_v1) { in spi_qup_io_config()
735 input_cnt = controller->base + QUP_MX_INPUT_CNT; in spi_qup_io_config()
739 * That case is a non-balanced transfer when there is in spi_qup_io_config()
742 if (xfer->tx_buf) in spi_qup_io_config()
745 writel_relaxed(controller->n_words, input_cnt); in spi_qup_io_config()
747 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
751 reinit_completion(&controller->done); in spi_qup_io_config()
752 writel_relaxed(controller->n_words, in spi_qup_io_config()
753 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
754 writel_relaxed(controller->n_words, in spi_qup_io_config()
755 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
757 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
758 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
761 dev_err(controller->dev, "unknown mode = %d\n", in spi_qup_io_config()
762 controller->mode); in spi_qup_io_config()
763 return -EIO; in spi_qup_io_config()
766 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
770 if (!spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
775 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
776 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
778 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
780 control = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
782 if (spi->mode & SPI_CPOL) in spi_qup_io_config()
787 writel_relaxed(control, controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
789 config = readl_relaxed(controller->base + SPI_CONFIG); in spi_qup_io_config()
791 if (spi->mode & SPI_LOOP) in spi_qup_io_config()
792 config |= SPI_CONFIG_LOOPBACK; in spi_qup_io_config()
794 config &= ~SPI_CONFIG_LOOPBACK; in spi_qup_io_config()
796 if (spi->mode & SPI_CPHA) in spi_qup_io_config()
797 config &= ~SPI_CONFIG_INPUT_FIRST; in spi_qup_io_config()
799 config |= SPI_CONFIG_INPUT_FIRST; in spi_qup_io_config()
802 * HS_MODE improves signal stability for spi-clk high rates, in spi_qup_io_config()
805 if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP)) in spi_qup_io_config()
806 config |= SPI_CONFIG_HS_MODE; in spi_qup_io_config()
808 config &= ~SPI_CONFIG_HS_MODE; in spi_qup_io_config()
810 writel_relaxed(config, controller->base + SPI_CONFIG); in spi_qup_io_config()
812 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_io_config()
813 config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N); in spi_qup_io_config()
814 config |= xfer->bits_per_word - 1; in spi_qup_io_config()
815 config |= QUP_CONFIG_SPI_MODE; in spi_qup_io_config()
817 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_io_config()
818 if (!xfer->tx_buf) in spi_qup_io_config()
819 config |= QUP_CONFIG_NO_OUTPUT; in spi_qup_io_config()
820 if (!xfer->rx_buf) in spi_qup_io_config()
821 config |= QUP_CONFIG_NO_INPUT; in spi_qup_io_config()
824 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_io_config()
827 if (!controller->qup_v1) { in spi_qup_io_config()
835 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
838 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); in spi_qup_io_config()
856 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC); in spi_qup_transfer_one()
858 xfer->len) * 8, timeout); in spi_qup_transfer_one()
861 reinit_completion(&controller->done); in spi_qup_transfer_one()
863 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
864 controller->xfer = xfer; in spi_qup_transfer_one()
865 controller->error = 0; in spi_qup_transfer_one()
866 controller->rx_bytes = 0; in spi_qup_transfer_one()
867 controller->tx_bytes = 0; in spi_qup_transfer_one()
868 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
870 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
876 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
878 ret = controller->error; in spi_qup_transfer_one()
879 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
881 if (ret && spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
890 struct spi_qup *qup = spi_master_get_devdata(master); in spi_qup_can_dma() local
894 if (xfer->rx_buf) { in spi_qup_can_dma()
895 if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) || in spi_qup_can_dma()
896 IS_ERR_OR_NULL(master->dma_rx)) in spi_qup_can_dma()
898 if (qup->qup_v1 && (xfer->len % qup->in_blk_sz)) in spi_qup_can_dma()
902 if (xfer->tx_buf) { in spi_qup_can_dma()
903 if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) || in spi_qup_can_dma()
904 IS_ERR_OR_NULL(master->dma_tx)) in spi_qup_can_dma()
906 if (qup->qup_v1 && (xfer->len % qup->out_blk_sz)) in spi_qup_can_dma()
910 n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_can_dma()
911 if (n_words <= (qup->in_fifo_sz / sizeof(u32))) in spi_qup_can_dma()
919 if (!IS_ERR_OR_NULL(master->dma_rx)) in spi_qup_release_dma()
920 dma_release_channel(master->dma_rx); in spi_qup_release_dma()
921 if (!IS_ERR_OR_NULL(master->dma_tx)) in spi_qup_release_dma()
922 dma_release_channel(master->dma_tx); in spi_qup_release_dma()
928 struct dma_slave_config *rx_conf = &spi->rx_conf, in spi_qup_init_dma()
929 *tx_conf = &spi->tx_conf; in spi_qup_init_dma()
930 struct device *dev = spi->dev; in spi_qup_init_dma()
934 master->dma_rx = dma_request_chan(dev, "rx"); in spi_qup_init_dma()
935 if (IS_ERR(master->dma_rx)) in spi_qup_init_dma()
936 return PTR_ERR(master->dma_rx); in spi_qup_init_dma()
938 master->dma_tx = dma_request_chan(dev, "tx"); in spi_qup_init_dma()
939 if (IS_ERR(master->dma_tx)) { in spi_qup_init_dma()
940 ret = PTR_ERR(master->dma_tx); in spi_qup_init_dma()
945 rx_conf->direction = DMA_DEV_TO_MEM; in spi_qup_init_dma()
946 rx_conf->device_fc = 1; in spi_qup_init_dma()
947 rx_conf->src_addr = base + QUP_INPUT_FIFO; in spi_qup_init_dma()
948 rx_conf->src_maxburst = spi->in_blk_sz; in spi_qup_init_dma()
950 tx_conf->direction = DMA_MEM_TO_DEV; in spi_qup_init_dma()
951 tx_conf->device_fc = 1; in spi_qup_init_dma()
952 tx_conf->dst_addr = base + QUP_OUTPUT_FIFO; in spi_qup_init_dma()
953 tx_conf->dst_maxburst = spi->out_blk_sz; in spi_qup_init_dma()
955 ret = dmaengine_slave_config(master->dma_rx, rx_conf); in spi_qup_init_dma()
961 ret = dmaengine_slave_config(master->dma_tx, tx_conf); in spi_qup_init_dma()
970 dma_release_channel(master->dma_tx); in spi_qup_init_dma()
972 dma_release_channel(master->dma_rx); in spi_qup_init_dma()
982 controller = spi_master_get_devdata(spi->master); in spi_qup_set_cs()
983 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
991 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
1005 dev = &pdev->dev; in spi_qup_probe()
1024 if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) in spi_qup_probe()
1029 return -ENXIO; in spi_qup_probe()
1050 return -ENOMEM; in spi_qup_probe()
1053 /* use num-cs unless not present or out of range */ in spi_qup_probe()
1054 if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) || in spi_qup_probe()
1056 master->num_chipselect = SPI_NUM_CHIPSELECTS; in spi_qup_probe()
1058 master->num_chipselect = num_cs; in spi_qup_probe()
1060 master->use_gpio_descriptors = true; in spi_qup_probe()
1061 master->max_native_cs = SPI_NUM_CHIPSELECTS; in spi_qup_probe()
1062 master->bus_num = pdev->id; in spi_qup_probe()
1063 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in spi_qup_probe()
1064 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in spi_qup_probe()
1065 master->max_speed_hz = max_freq; in spi_qup_probe()
1066 master->transfer_one = spi_qup_transfer_one; in spi_qup_probe()
1067 master->dev.of_node = pdev->dev.of_node; in spi_qup_probe()
1068 master->auto_runtime_pm = true; in spi_qup_probe()
1069 master->dma_alignment = dma_get_cache_alignment(); in spi_qup_probe()
1070 master->max_dma_len = SPI_MAX_XFER; in spi_qup_probe()
1076 controller->dev = dev; in spi_qup_probe()
1077 controller->base = base; in spi_qup_probe()
1078 controller->iclk = iclk; in spi_qup_probe()
1079 controller->cclk = cclk; in spi_qup_probe()
1080 controller->irq = irq; in spi_qup_probe()
1082 ret = spi_qup_init_dma(master, res->start); in spi_qup_probe()
1083 if (ret == -EPROBE_DEFER) in spi_qup_probe()
1086 master->can_dma = spi_qup_can_dma; in spi_qup_probe()
1088 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev); in spi_qup_probe()
1090 if (!controller->qup_v1) in spi_qup_probe()
1091 master->set_cs = spi_qup_set_cs; in spi_qup_probe()
1093 spin_lock_init(&controller->lock); in spi_qup_probe()
1094 init_completion(&controller->done); in spi_qup_probe()
1100 controller->out_blk_sz = size * 16; in spi_qup_probe()
1102 controller->out_blk_sz = 4; in spi_qup_probe()
1106 controller->in_blk_sz = size * 16; in spi_qup_probe()
1108 controller->in_blk_sz = 4; in spi_qup_probe()
1111 controller->out_fifo_sz = controller->out_blk_sz * (2 << size); in spi_qup_probe()
1114 controller->in_fifo_sz = controller->in_blk_sz * (2 << size); in spi_qup_probe()
1117 controller->in_blk_sz, controller->in_fifo_sz, in spi_qup_probe()
1118 controller->out_blk_sz, controller->out_fifo_sz); in spi_qup_probe()
1131 if (!controller->qup_v1) in spi_qup_probe()
1137 /* if earlier version of the QUP, disable INPUT_OVERRUN */ in spi_qup_probe()
1138 if (controller->qup_v1) in spi_qup_probe()
1147 IRQF_TRIGGER_HIGH, pdev->name, controller); in spi_qup_probe()
1163 pm_runtime_disable(&pdev->dev); in spi_qup_probe()
1178 u32 config; in spi_qup_pm_suspend_runtime() local
1181 config = readl(controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1182 config |= QUP_CONFIG_CLOCK_AUTO_GATE; in spi_qup_pm_suspend_runtime()
1183 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1185 clk_disable_unprepare(controller->cclk); in spi_qup_pm_suspend_runtime()
1186 clk_disable_unprepare(controller->iclk); in spi_qup_pm_suspend_runtime()
1195 u32 config; in spi_qup_pm_resume_runtime() local
1198 ret = clk_prepare_enable(controller->iclk); in spi_qup_pm_resume_runtime()
1202 ret = clk_prepare_enable(controller->cclk); in spi_qup_pm_resume_runtime()
1204 clk_disable_unprepare(controller->iclk); in spi_qup_pm_resume_runtime()
1209 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1210 config &= ~QUP_CONFIG_CLOCK_AUTO_GATE; in spi_qup_pm_resume_runtime()
1211 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1236 clk_disable_unprepare(controller->cclk); in spi_qup_suspend()
1237 clk_disable_unprepare(controller->iclk); in spi_qup_suspend()
1247 ret = clk_prepare_enable(controller->iclk); in spi_qup_resume()
1251 ret = clk_prepare_enable(controller->cclk); in spi_qup_resume()
1253 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1268 clk_disable_unprepare(controller->cclk); in spi_qup_resume()
1269 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1276 struct spi_master *master = dev_get_drvdata(&pdev->dev); in spi_qup_remove()
1280 ret = pm_runtime_resume_and_get(&pdev->dev); in spi_qup_remove()
1290 clk_disable_unprepare(controller->cclk); in spi_qup_remove()
1291 clk_disable_unprepare(controller->iclk); in spi_qup_remove()
1293 pm_runtime_put_noidle(&pdev->dev); in spi_qup_remove()
1294 pm_runtime_disable(&pdev->dev); in spi_qup_remove()
1300 { .compatible = "qcom,spi-qup-v1.1.1", .data = (void *)1, },
1301 { .compatible = "qcom,spi-qup-v2.1.1", },
1302 { .compatible = "qcom,spi-qup-v2.2.1", },