Lines Matching +full:mmp2 +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-or-later
32 #include "spi-pxa2xx.h"
37 MODULE_ALIAS("platform:pxa2xx-spi");
79 /* LPSS offset from drv_data->ioaddr */
81 /* Register offsets from drv_data->lpss_base or -1 */
105 .reg_capabilities = -1,
115 .reg_capabilities = -1,
125 .reg_capabilities = -1,
135 .reg_general = -1,
138 .reg_capabilities = -1,
145 .reg_general = -1,
158 .reg_general = -1,
174 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; in lpss_get_config()
179 switch (drv_data->ssp_type) { in is_lpss_ssp()
194 return drv_data->ssp_type == QUARK_X1000_SSP; in is_quark_x1000_ssp()
199 return drv_data->ssp_type == MMP2_SSP; in is_mmp2_ssp()
204 return drv_data->ssp_type == MRFLD_SSP; in is_mrfld_ssp()
215 switch (drv_data->ssp_type) { in pxa2xx_spi_get_ssrc1_change_mask()
228 switch (drv_data->ssp_type) { in pxa2xx_spi_get_rx_default_thre()
242 switch (drv_data->ssp_type) { in pxa2xx_spi_txfifo_full()
262 switch (drv_data->ssp_type) { in pxa2xx_spi_clear_rx_thre()
279 switch (drv_data->ssp_type) { in pxa2xx_spi_set_rx_thre()
295 switch (drv_data->ssp_type) { in pxa2xx_configure_sscr0()
303 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) in pxa2xx_configure_sscr0()
314 WARN_ON(!drv_data->lpss_base); in __lpss_ssp_read_priv()
315 return readl(drv_data->lpss_base + offset); in __lpss_ssp_read_priv()
321 WARN_ON(!drv_data->lpss_base); in __lpss_ssp_write_priv()
322 writel(value, drv_data->lpss_base + offset); in __lpss_ssp_write_priv()
326 * lpss_ssp_setup - perform LPSS SSP specific setup
338 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset; in lpss_ssp_setup()
341 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_setup()
344 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); in lpss_ssp_setup()
347 if (drv_data->controller_info->enable_dma) { in lpss_ssp_setup()
348 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); in lpss_ssp_setup()
350 if (config->reg_general >= 0) { in lpss_ssp_setup()
352 config->reg_general); in lpss_ssp_setup()
355 config->reg_general, value); in lpss_ssp_setup()
364 spi_controller_get_devdata(spi->controller); in lpss_ssp_select_cs()
367 if (!config->cs_sel_mask) in lpss_ssp_select_cs()
370 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_select_cs()
372 cs = spi->chip_select; in lpss_ssp_select_cs()
373 cs <<= config->cs_sel_shift; in lpss_ssp_select_cs()
374 if (cs != (value & config->cs_sel_mask)) { in lpss_ssp_select_cs()
382 value &= ~config->cs_sel_mask; in lpss_ssp_select_cs()
385 config->reg_cs_ctrl, value); in lpss_ssp_select_cs()
387 (drv_data->controller->max_speed_hz / 2)); in lpss_ssp_select_cs()
394 spi_controller_get_devdata(spi->controller); in lpss_ssp_cs_control()
403 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); in lpss_ssp_cs_control()
408 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); in lpss_ssp_cs_control()
409 if (config->cs_clk_stays_gated) { in lpss_ssp_cs_control()
413 * Changing CS alone when dynamic clock gating is on won't in lpss_ssp_cs_control()
415 * that specify delays, or have no data. Toggle the clock mode in lpss_ssp_cs_control()
430 spi_controller_get_devdata(spi->controller); in cs_assert()
432 if (drv_data->ssp_type == CE4100_SSP) { in cs_assert()
433 pxa2xx_spi_write(drv_data, SSSR, spi->chip_select); in cs_assert()
444 spi_controller_get_devdata(spi->controller); in cs_deassert()
447 if (drv_data->ssp_type == CE4100_SSP) in cs_deassert()
475 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); in pxa2xx_spi_flush()
487 pxa_ssp_disable(drv_data->ssp); in pxa2xx_spi_off()
492 u8 n_bytes = drv_data->n_bytes; in null_writer()
495 || (drv_data->tx == drv_data->tx_end)) in null_writer()
499 drv_data->tx += n_bytes; in null_writer()
506 u8 n_bytes = drv_data->n_bytes; in null_reader()
508 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in null_reader()
510 drv_data->rx += n_bytes; in null_reader()
513 return drv_data->rx == drv_data->rx_end; in null_reader()
519 || (drv_data->tx == drv_data->tx_end)) in u8_writer()
522 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); in u8_writer()
523 ++drv_data->tx; in u8_writer()
530 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u8_reader()
531 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u8_reader()
532 ++drv_data->rx; in u8_reader()
535 return drv_data->rx == drv_data->rx_end; in u8_reader()
541 || (drv_data->tx == drv_data->tx_end)) in u16_writer()
544 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); in u16_writer()
545 drv_data->tx += 2; in u16_writer()
552 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u16_reader()
553 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u16_reader()
554 drv_data->rx += 2; in u16_reader()
557 return drv_data->rx == drv_data->rx_end; in u16_reader()
563 || (drv_data->tx == drv_data->tx_end)) in u32_writer()
566 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); in u32_writer()
567 drv_data->tx += 4; in u32_writer()
574 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) { in u32_reader()
575 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); in u32_reader()
576 drv_data->rx += 4; in u32_reader()
579 return drv_data->rx == drv_data->rx_end; in u32_reader()
584 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold; in reset_sccr1()
587 if (drv_data->controller->cur_msg) { in reset_sccr1()
588 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi); in reset_sccr1()
589 threshold = chip->threshold; in reset_sccr1()
594 switch (drv_data->ssp_type) { in reset_sccr1()
612 write_SSSR_CS(drv_data, drv_data->clear_sr); in int_stop_and_reset()
626 dev_err(drv_data->ssp->dev, "%s\n", msg); in int_error_stop()
628 drv_data->controller->cur_msg->status = err; in int_error_stop()
629 spi_finalize_current_transfer(drv_data->controller); in int_error_stop()
636 spi_finalize_current_transfer(drv_data->controller); in int_transfer_complete()
643 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr); in interrupt_transfer()
648 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO); in interrupt_transfer()
653 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO); in interrupt_transfer()
659 if (drv_data->read(drv_data)) { in interrupt_transfer()
667 if (drv_data->read(drv_data)) { in interrupt_transfer()
671 } while (drv_data->write(drv_data)); in interrupt_transfer()
673 if (drv_data->read(drv_data)) { in interrupt_transfer()
678 if (drv_data->tx == drv_data->tx_end) { in interrupt_transfer()
694 bytes_left = drv_data->rx_end - drv_data->rx; in interrupt_transfer()
695 switch (drv_data->n_bytes) { in interrupt_transfer()
722 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n"); in handle_bad_msg()
729 u32 mask = drv_data->mask_sr; in ssp_int()
738 if (pm_runtime_suspended(drv_data->ssp->dev)) in ssp_int()
764 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); in ssp_int()
767 if (!drv_data->controller->cur_msg) { in ssp_int()
773 return drv_data->transfer_handler(drv_data); in ssp_int()
832 scale = fls_long(q1 - 1); in quark_x1000_get_clk_div()
834 q1 >>= scale - 9; in quark_x1000_get_clk_div()
835 mul >>= scale - 9; in quark_x1000_get_clk_div()
848 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); in quark_x1000_get_clk_div()
853 r2 = abs(fref2 / q2 - rate); in quark_x1000_get_clk_div()
883 r1 = abs(fssp - rate); in quark_x1000_get_clk_div()
894 return q - 1; in quark_x1000_get_clk_div()
899 unsigned long ssp_clk = drv_data->controller->max_speed_hz; in ssp_get_clk_div()
900 const struct ssp_device *ssp = drv_data->ssp; in ssp_get_clk_div()
905 * Calculate the divisor for the SCR (Serial Clock Rate), avoiding in ssp_get_clk_div()
908 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) in ssp_get_clk_div()
909 return (DIV_ROUND_UP(ssp_clk, 2 * rate) - 1) & 0xff; in ssp_get_clk_div()
911 return (DIV_ROUND_UP(ssp_clk, rate) - 1) & 0xfff; in ssp_get_clk_div()
918 spi_get_ctldata(drv_data->controller->cur_msg->spi); in pxa2xx_ssp_get_clk_div()
921 switch (drv_data->ssp_type) { in pxa2xx_ssp_get_clk_div()
923 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); in pxa2xx_ssp_get_clk_div()
938 return chip->enable_dma && in pxa2xx_spi_can_dma()
939 xfer->len <= MAX_DMA_LEN && in pxa2xx_spi_can_dma()
940 xfer->len >= chip->dma_burst_size; in pxa2xx_spi_can_dma()
948 struct spi_message *message = controller->cur_msg; in pxa2xx_spi_transfer_one()
950 u32 dma_thresh = chip->dma_threshold; in pxa2xx_spi_transfer_one()
951 u32 dma_burst = chip->dma_burst_size; in pxa2xx_spi_transfer_one()
962 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { in pxa2xx_spi_transfer_one()
964 /* Reject already-mapped transfers; PIO won't always work */ in pxa2xx_spi_transfer_one()
965 if (message->is_dma_mapped in pxa2xx_spi_transfer_one()
966 || transfer->rx_dma || transfer->tx_dma) { in pxa2xx_spi_transfer_one()
967 dev_err(&spi->dev, in pxa2xx_spi_transfer_one()
969 transfer->len, MAX_DMA_LEN); in pxa2xx_spi_transfer_one()
970 return -EINVAL; in pxa2xx_spi_transfer_one()
974 dev_warn_ratelimited(&spi->dev, in pxa2xx_spi_transfer_one()
976 transfer->len, MAX_DMA_LEN); in pxa2xx_spi_transfer_one()
981 dev_err(&spi->dev, "Flush failed\n"); in pxa2xx_spi_transfer_one()
982 return -EIO; in pxa2xx_spi_transfer_one()
984 drv_data->tx = (void *)transfer->tx_buf; in pxa2xx_spi_transfer_one()
985 drv_data->tx_end = drv_data->tx + transfer->len; in pxa2xx_spi_transfer_one()
986 drv_data->rx = transfer->rx_buf; in pxa2xx_spi_transfer_one()
987 drv_data->rx_end = drv_data->rx + transfer->len; in pxa2xx_spi_transfer_one()
990 bits = transfer->bits_per_word; in pxa2xx_spi_transfer_one()
991 speed = transfer->speed_hz; in pxa2xx_spi_transfer_one()
996 drv_data->n_bytes = 1; in pxa2xx_spi_transfer_one()
997 drv_data->read = drv_data->rx ? u8_reader : null_reader; in pxa2xx_spi_transfer_one()
998 drv_data->write = drv_data->tx ? u8_writer : null_writer; in pxa2xx_spi_transfer_one()
1000 drv_data->n_bytes = 2; in pxa2xx_spi_transfer_one()
1001 drv_data->read = drv_data->rx ? u16_reader : null_reader; in pxa2xx_spi_transfer_one()
1002 drv_data->write = drv_data->tx ? u16_writer : null_writer; in pxa2xx_spi_transfer_one()
1004 drv_data->n_bytes = 4; in pxa2xx_spi_transfer_one()
1005 drv_data->read = drv_data->rx ? u32_reader : null_reader; in pxa2xx_spi_transfer_one()
1006 drv_data->write = drv_data->tx ? u32_writer : null_writer; in pxa2xx_spi_transfer_one()
1012 if (chip->enable_dma) { in pxa2xx_spi_transfer_one()
1017 dev_warn_ratelimited(&spi->dev, in pxa2xx_spi_transfer_one()
1021 dma_mapped = controller->can_dma && in pxa2xx_spi_transfer_one()
1022 controller->can_dma(controller, spi, transfer) && in pxa2xx_spi_transfer_one()
1023 controller->cur_msg_mapped; in pxa2xx_spi_transfer_one()
1027 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; in pxa2xx_spi_transfer_one()
1034 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; in pxa2xx_spi_transfer_one()
1035 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
1040 drv_data->transfer_handler = interrupt_transfer; in pxa2xx_spi_transfer_one()
1043 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; in pxa2xx_spi_transfer_one()
1044 write_SSSR_CS(drv_data, drv_data->clear_sr); in pxa2xx_spi_transfer_one()
1050 dev_dbg(&spi->dev, "%u Hz actual, %s\n", in pxa2xx_spi_transfer_one()
1051 controller->max_speed_hz in pxa2xx_spi_transfer_one()
1055 dev_dbg(&spi->dev, "%u Hz actual, %s\n", in pxa2xx_spi_transfer_one()
1056 controller->max_speed_hz / 2 in pxa2xx_spi_transfer_one()
1061 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold); in pxa2xx_spi_transfer_one()
1062 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold); in pxa2xx_spi_transfer_one()
1069 thresh |= SFIFOTT_RxThresh(chip->lpss_rx_threshold); in pxa2xx_spi_transfer_one()
1070 thresh |= SFIFOTT_TxThresh(chip->lpss_tx_threshold); in pxa2xx_spi_transfer_one()
1076 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate); in pxa2xx_spi_transfer_one()
1080 pxa_ssp_disable(drv_data->ssp); in pxa2xx_spi_transfer_one()
1083 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); in pxa2xx_spi_transfer_one()
1092 pxa_ssp_enable(drv_data->ssp); in pxa2xx_spi_transfer_one()
1098 /* On MMP2, flipping SSE doesn't to empty Tx FIFO. */ in pxa2xx_spi_transfer_one()
1099 dev_warn(&spi->dev, "%u bytes of garbage in Tx FIFO!\n", tx_level); in pxa2xx_spi_transfer_one()
1100 if (tx_level > transfer->len) in pxa2xx_spi_transfer_one()
1101 tx_level = transfer->len; in pxa2xx_spi_transfer_one()
1102 drv_data->tx += tx_level; in pxa2xx_spi_transfer_one()
1107 while (drv_data->write(drv_data)) in pxa2xx_spi_transfer_one()
1109 if (drv_data->gpiod_ready) { in pxa2xx_spi_transfer_one()
1110 gpiod_set_value(drv_data->gpiod_ready, 1); in pxa2xx_spi_transfer_one()
1112 gpiod_set_value(drv_data->gpiod_ready, 0); in pxa2xx_spi_transfer_one()
1129 int_error_stop(drv_data, "transfer aborted", -EINTR); in pxa2xx_spi_slave_abort()
1151 if (atomic_read(&drv_data->dma_running)) in pxa2xx_spi_handle_err()
1171 spi_controller_get_devdata(spi->controller); in setup()
1174 switch (drv_data->ssp_type) { in setup()
1197 tx_thres = config->tx_threshold_lo; in setup()
1198 tx_hi_thres = config->tx_threshold_hi; in setup()
1199 rx_thres = config->rx_threshold; in setup()
1203 if (spi_controller_is_slave(drv_data->controller)) { in setup()
1218 return -ENOMEM; in setup()
1220 if (drv_data->ssp_type == CE4100_SSP) { in setup()
1221 if (spi->chip_select > 4) { in setup()
1222 dev_err(&spi->dev, in setup()
1225 return -EINVAL; in setup()
1228 chip->enable_dma = drv_data->controller_info->enable_dma; in setup()
1229 chip->timeout = TIMOUT_DFLT; in setup()
1236 chip_info = spi->controller_data; in setup()
1240 if (chip_info->timeout) in setup()
1241 chip->timeout = chip_info->timeout; in setup()
1242 if (chip_info->tx_threshold) in setup()
1243 tx_thres = chip_info->tx_threshold; in setup()
1244 if (chip_info->tx_hi_threshold) in setup()
1245 tx_hi_thres = chip_info->tx_hi_threshold; in setup()
1246 if (chip_info->rx_threshold) in setup()
1247 rx_thres = chip_info->rx_threshold; in setup()
1248 chip->dma_threshold = 0; in setup()
1251 chip->cr1 = 0; in setup()
1252 if (spi_controller_is_slave(drv_data->controller)) { in setup()
1253 chip->cr1 |= SSCR1_SCFR; in setup()
1254 chip->cr1 |= SSCR1_SCLKDIR; in setup()
1255 chip->cr1 |= SSCR1_SFRMDIR; in setup()
1256 chip->cr1 |= SSCR1_SPH; in setup()
1260 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); in setup()
1261 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) | in setup()
1266 chip->lpss_rx_threshold = rx_thres; in setup()
1267 chip->lpss_tx_threshold = tx_thres; in setup()
1272 * chip_info goes away after setting chip->enable_dma, the burst and in setup()
1275 if (chip->enable_dma) { in setup()
1278 spi->bits_per_word, in setup()
1279 &chip->dma_burst_size, in setup()
1280 &chip->dma_threshold)) { in setup()
1281 dev_warn(&spi->dev, in setup()
1284 dev_dbg(&spi->dev, in setup()
1286 chip->dma_burst_size); in setup()
1289 switch (drv_data->ssp_type) { in setup()
1291 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) in setup()
1297 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | in setup()
1301 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | in setup()
1306 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); in setup()
1307 chip->cr1 |= ((spi->mode & SPI_CPHA) ? SSCR1_SPH : 0) | in setup()
1308 ((spi->mode & SPI_CPOL) ? SSCR1_SPO : 0); in setup()
1310 if (spi->mode & SPI_LOOP) in setup()
1311 chip->cr1 |= SSCR1_LBM; in setup()
1344 /* SPT-LP */
1347 /* SPT-H */
1350 /* KBL-H */
1353 /* CML-V */
1356 /* BXT A-Step */
1360 /* BXT B-Step */
1368 /* ICL-LP */
1380 /* TGL-H */
1385 /* ADL-P */
1389 /* ADL-M */
1397 /* RPL-S */
1402 /* ADL-S */
1407 /* MTL-P */
1411 /* CNL-LP */
1415 /* CNL-H */
1419 /* CML-LP */
1423 /* CML-H */
1427 /* TGL-LP */
1439 { .compatible = "marvell,mmp2-ssp", .data = (void *)MMP2_SSP },
1448 return param == chan->device->dev; in pxa2xx_spi_idma_filter()
1457 struct device *dev = &pdev->dev; in pxa2xx_spi_init_pdata()
1458 struct device *parent = dev->parent; in pxa2xx_spi_init_pdata()
1471 match = device_get_match_data(&pdev->dev); in pxa2xx_spi_init_pdata()
1475 type = (enum pxa_ssp_type)pcidev_id->driver_data; in pxa2xx_spi_init_pdata()
1477 return ERR_PTR(-EINVAL); in pxa2xx_spi_init_pdata()
1479 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); in pxa2xx_spi_init_pdata()
1481 return ERR_PTR(-ENOMEM); in pxa2xx_spi_init_pdata()
1483 ssp = &pdata->ssp; in pxa2xx_spi_init_pdata()
1486 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); in pxa2xx_spi_init_pdata()
1487 if (IS_ERR(ssp->mmio_base)) in pxa2xx_spi_init_pdata()
1488 return ERR_CAST(ssp->mmio_base); in pxa2xx_spi_init_pdata()
1490 ssp->phys_base = res->start; in pxa2xx_spi_init_pdata()
1494 pdata->tx_param = parent; in pxa2xx_spi_init_pdata()
1495 pdata->rx_param = parent; in pxa2xx_spi_init_pdata()
1496 pdata->dma_filter = pxa2xx_spi_idma_filter; in pxa2xx_spi_init_pdata()
1500 ssp->clk = devm_clk_get(&pdev->dev, NULL); in pxa2xx_spi_init_pdata()
1501 if (IS_ERR(ssp->clk)) in pxa2xx_spi_init_pdata()
1502 return ERR_CAST(ssp->clk); in pxa2xx_spi_init_pdata()
1504 ssp->irq = platform_get_irq(pdev, 0); in pxa2xx_spi_init_pdata()
1505 if (ssp->irq < 0) in pxa2xx_spi_init_pdata()
1506 return ERR_PTR(ssp->irq); in pxa2xx_spi_init_pdata()
1508 ssp->type = type; in pxa2xx_spi_init_pdata()
1509 ssp->dev = &pdev->dev; in pxa2xx_spi_init_pdata()
1513 ssp->port_id = -1; in pxa2xx_spi_init_pdata()
1515 ssp->port_id = uid; in pxa2xx_spi_init_pdata()
1517 pdata->is_slave = device_property_read_bool(&pdev->dev, "spi-slave"); in pxa2xx_spi_init_pdata()
1518 pdata->num_chipselect = 1; in pxa2xx_spi_init_pdata()
1519 pdata->enable_dma = true; in pxa2xx_spi_init_pdata()
1520 pdata->dma_burst_size = 1; in pxa2xx_spi_init_pdata()
1530 if (has_acpi_companion(drv_data->ssp->dev)) { in pxa2xx_spi_fw_translate_cs()
1531 switch (drv_data->ssp_type) { in pxa2xx_spi_fw_translate_cs()
1539 return cs - 1; in pxa2xx_spi_fw_translate_cs()
1556 struct device *dev = &pdev->dev; in pxa2xx_spi_probe()
1569 dev_err(&pdev->dev, "missing platform data\n"); in pxa2xx_spi_probe()
1574 ssp = pxa_ssp_request(pdev->id, pdev->name); in pxa2xx_spi_probe()
1576 ssp = &platform_info->ssp; in pxa2xx_spi_probe()
1578 if (!ssp->mmio_base) { in pxa2xx_spi_probe()
1579 dev_err(&pdev->dev, "failed to get SSP\n"); in pxa2xx_spi_probe()
1580 return -ENODEV; in pxa2xx_spi_probe()
1583 if (platform_info->is_slave) in pxa2xx_spi_probe()
1589 dev_err(&pdev->dev, "cannot alloc spi_controller\n"); in pxa2xx_spi_probe()
1590 status = -ENOMEM; in pxa2xx_spi_probe()
1594 drv_data->controller = controller; in pxa2xx_spi_probe()
1595 drv_data->controller_info = platform_info; in pxa2xx_spi_probe()
1596 drv_data->ssp = ssp; in pxa2xx_spi_probe()
1598 device_set_node(&controller->dev, dev_fwnode(dev)); in pxa2xx_spi_probe()
1600 /* The spi->mode bits understood by this driver: */ in pxa2xx_spi_probe()
1601 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; in pxa2xx_spi_probe()
1603 controller->bus_num = ssp->port_id; in pxa2xx_spi_probe()
1604 controller->dma_alignment = DMA_ALIGNMENT; in pxa2xx_spi_probe()
1605 controller->cleanup = cleanup; in pxa2xx_spi_probe()
1606 controller->setup = setup; in pxa2xx_spi_probe()
1607 controller->set_cs = pxa2xx_spi_set_cs; in pxa2xx_spi_probe()
1608 controller->transfer_one = pxa2xx_spi_transfer_one; in pxa2xx_spi_probe()
1609 controller->slave_abort = pxa2xx_spi_slave_abort; in pxa2xx_spi_probe()
1610 controller->handle_err = pxa2xx_spi_handle_err; in pxa2xx_spi_probe()
1611 controller->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; in pxa2xx_spi_probe()
1612 controller->fw_translate_cs = pxa2xx_spi_fw_translate_cs; in pxa2xx_spi_probe()
1613 controller->auto_runtime_pm = true; in pxa2xx_spi_probe()
1614 controller->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; in pxa2xx_spi_probe()
1616 drv_data->ssp_type = ssp->type; in pxa2xx_spi_probe()
1619 switch (drv_data->ssp_type) { in pxa2xx_spi_probe()
1621 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in pxa2xx_spi_probe()
1624 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); in pxa2xx_spi_probe()
1628 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; in pxa2xx_spi_probe()
1629 drv_data->dma_cr1 = 0; in pxa2xx_spi_probe()
1630 drv_data->clear_sr = SSSR_ROR; in pxa2xx_spi_probe()
1631 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; in pxa2xx_spi_probe()
1633 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in pxa2xx_spi_probe()
1634 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; in pxa2xx_spi_probe()
1635 drv_data->dma_cr1 = DEFAULT_DMA_CR1; in pxa2xx_spi_probe()
1636 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; in pxa2xx_spi_probe()
1637 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS in pxa2xx_spi_probe()
1641 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), in pxa2xx_spi_probe()
1644 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); in pxa2xx_spi_probe()
1649 if (platform_info->enable_dma) { in pxa2xx_spi_probe()
1653 platform_info->enable_dma = false; in pxa2xx_spi_probe()
1655 controller->can_dma = pxa2xx_spi_can_dma; in pxa2xx_spi_probe()
1656 controller->max_dma_len = MAX_DMA_LEN; in pxa2xx_spi_probe()
1657 controller->max_transfer_size = in pxa2xx_spi_probe()
1662 /* Enable SOC clock */ in pxa2xx_spi_probe()
1663 status = clk_prepare_enable(ssp->clk); in pxa2xx_spi_probe()
1667 controller->max_speed_hz = clk_get_rate(ssp->clk); in pxa2xx_spi_probe()
1673 controller->min_speed_hz = in pxa2xx_spi_probe()
1674 DIV_ROUND_UP(controller->max_speed_hz, 4096); in pxa2xx_spi_probe()
1676 controller->min_speed_hz = in pxa2xx_spi_probe()
1677 DIV_ROUND_UP(controller->max_speed_hz, 512); in pxa2xx_spi_probe()
1682 switch (drv_data->ssp_type) { in pxa2xx_spi_probe()
1729 if (config->reg_capabilities >= 0) { in pxa2xx_spi_probe()
1731 config->reg_capabilities); in pxa2xx_spi_probe()
1734 platform_info->num_chipselect = ffz(tmp); in pxa2xx_spi_probe()
1735 } else if (config->cs_num) { in pxa2xx_spi_probe()
1736 platform_info->num_chipselect = config->cs_num; in pxa2xx_spi_probe()
1739 controller->num_chipselect = platform_info->num_chipselect; in pxa2xx_spi_probe()
1740 controller->use_gpio_descriptors = true; in pxa2xx_spi_probe()
1742 if (platform_info->is_slave) { in pxa2xx_spi_probe()
1743 drv_data->gpiod_ready = devm_gpiod_get_optional(dev, in pxa2xx_spi_probe()
1745 if (IS_ERR(drv_data->gpiod_ready)) { in pxa2xx_spi_probe()
1746 status = PTR_ERR(drv_data->gpiod_ready); in pxa2xx_spi_probe()
1751 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); in pxa2xx_spi_probe()
1752 pm_runtime_use_autosuspend(&pdev->dev); in pxa2xx_spi_probe()
1753 pm_runtime_set_active(&pdev->dev); in pxa2xx_spi_probe()
1754 pm_runtime_enable(&pdev->dev); in pxa2xx_spi_probe()
1760 dev_err(&pdev->dev, "problem registering SPI controller\n"); in pxa2xx_spi_probe()
1767 pm_runtime_disable(&pdev->dev); in pxa2xx_spi_probe()
1770 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_probe()
1774 free_irq(ssp->irq, drv_data); in pxa2xx_spi_probe()
1784 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_remove()
1786 pm_runtime_get_sync(&pdev->dev); in pxa2xx_spi_remove()
1788 spi_unregister_controller(drv_data->controller); in pxa2xx_spi_remove()
1792 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_remove()
1795 if (drv_data->controller_info->enable_dma) in pxa2xx_spi_remove()
1798 pm_runtime_put_noidle(&pdev->dev); in pxa2xx_spi_remove()
1799 pm_runtime_disable(&pdev->dev); in pxa2xx_spi_remove()
1802 free_irq(ssp->irq, drv_data); in pxa2xx_spi_remove()
1814 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_suspend()
1817 status = spi_controller_suspend(drv_data->controller); in pxa2xx_spi_suspend()
1824 clk_disable_unprepare(ssp->clk); in pxa2xx_spi_suspend()
1832 struct ssp_device *ssp = drv_data->ssp; in pxa2xx_spi_resume()
1835 /* Enable the SSP clock */ in pxa2xx_spi_resume()
1837 status = clk_prepare_enable(ssp->clk); in pxa2xx_spi_resume()
1843 return spi_controller_resume(drv_data->controller); in pxa2xx_spi_resume()
1852 clk_disable_unprepare(drv_data->ssp->clk); in pxa2xx_spi_runtime_suspend()
1860 return clk_prepare_enable(drv_data->ssp->clk); in pxa2xx_spi_runtime_resume()
1872 .name = "pxa2xx-spi",