Lines Matching +full:cs +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
58 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
63 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
82 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
124 /* SPI1 has 4 channels, while SPI2 has 2 */
149 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
156 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
162 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg() local
164 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
169 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_read_cs_reg() local
171 return readl_relaxed(cs->base + idx); in mcspi_read_cs_reg()
176 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_cached_chconf0() local
178 return cs->chconf0; in mcspi_cached_chconf0()
183 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_chconf0() local
185 cs->chconf0 = val; in mcspi_write_chconf0()
195 return 2; in mcspi_bytes_per_word()
222 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_enable() local
225 l = cs->chctrl0; in omap2_mcspi_set_enable()
230 cs->chctrl0 = l; in omap2_mcspi_set_enable()
231 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_set_enable()
232 /* Flash post-writes */ in omap2_mcspi_set_enable()
238 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_set_cs()
245 if (spi->mode & SPI_CS_HIGH) in omap2_mcspi_set_cs()
248 if (spi->controller_state) { in omap2_mcspi_set_cs()
249 int err = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_set_cs()
251 dev_err(mcspi->dev, "failed to get sync: %d\n", err); in omap2_mcspi_set_cs()
264 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_set_cs()
265 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_set_cs()
272 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_set_mode()
288 ctx->modulctrl = l; in omap2_mcspi_set_mode()
294 struct spi_master *master = spi->master; in omap2_mcspi_set_fifo()
295 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_set_fifo() local
305 bytes_per_word = mcspi_bytes_per_word(cs->word_len); in omap2_mcspi_set_fifo()
306 if (t->len % bytes_per_word != 0) in omap2_mcspi_set_fifo()
309 if (t->rx_buf != NULL && t->tx_buf != NULL) in omap2_mcspi_set_fifo()
310 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2; in omap2_mcspi_set_fifo()
314 wcnt = t->len / bytes_per_word; in omap2_mcspi_set_fifo()
319 if (t->rx_buf != NULL) { in omap2_mcspi_set_fifo()
321 xferlevel |= (bytes_per_word - 1) << 8; in omap2_mcspi_set_fifo()
324 if (t->tx_buf != NULL) { in omap2_mcspi_set_fifo()
326 xferlevel |= bytes_per_word - 1; in omap2_mcspi_set_fifo()
331 mcspi->fifo_depth = max_fifo_depth; in omap2_mcspi_set_fifo()
337 if (t->rx_buf != NULL) in omap2_mcspi_set_fifo()
340 if (t->tx_buf != NULL) in omap2_mcspi_set_fifo()
344 mcspi->fifo_depth = 0; in omap2_mcspi_set_fifo()
355 return -ETIMEDOUT; in mcspi_wait_for_reg_bit()
367 if (spi_controller_is_slave(mcspi->master)) { in mcspi_wait_for_completion()
369 mcspi->slave_aborted) in mcspi_wait_for_completion()
370 return -EINTR; in mcspi_wait_for_completion()
381 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_rx_callback()
382 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_rx_callback()
387 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_callback()
393 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_tx_callback()
394 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_tx_callback()
399 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_tx_callback()
410 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_tx_dma()
411 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_tx_dma()
413 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg); in omap2_mcspi_tx_dma()
415 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl, in omap2_mcspi_tx_dma()
416 xfer->tx_sg.nents, in omap2_mcspi_tx_dma()
420 tx->callback = omap2_mcspi_tx_callback; in omap2_mcspi_tx_dma()
421 tx->callback_param = spi; in omap2_mcspi_tx_dma()
426 dma_async_issue_pending(mcspi_dma->dma_tx); in omap2_mcspi_tx_dma()
438 struct scatterlist *sg_out[2]; in omap2_mcspi_rx_dma()
439 int nb_sizes = 0, out_mapped_nents[2], ret, x; in omap2_mcspi_rx_dma()
440 size_t sizes[2]; in omap2_mcspi_rx_dma()
444 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_rx_dma() local
445 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_rx_dma()
448 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_rx_dma()
449 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_rx_dma()
450 count = xfer->len; in omap2_mcspi_rx_dma()
453 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM in omap2_mcspi_rx_dma()
457 if (mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
460 word_len = cs->word_len; in omap2_mcspi_rx_dma()
468 element_count = count >> 2; in omap2_mcspi_rx_dma()
471 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg); in omap2_mcspi_rx_dma()
477 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0) in omap2_mcspi_rx_dma()
482 sizes[0] = count - transfer_reduction; in omap2_mcspi_rx_dma()
484 nb_sizes = 2; in omap2_mcspi_rx_dma()
494 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents, 0, nb_sizes, in omap2_mcspi_rx_dma()
498 dev_err(&spi->dev, "sg_split failed\n"); in omap2_mcspi_rx_dma()
502 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, sg_out[0], in omap2_mcspi_rx_dma()
506 tx->callback = omap2_mcspi_rx_callback; in omap2_mcspi_rx_dma()
507 tx->callback_param = spi; in omap2_mcspi_rx_dma()
513 dma_async_issue_pending(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
516 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion); in omap2_mcspi_rx_dma()
517 if (ret || mcspi->slave_aborted) { in omap2_mcspi_rx_dma()
518 dmaengine_terminate_sync(mcspi_dma->dma_rx); in omap2_mcspi_rx_dma()
526 if (mcspi->fifo_depth > 0) in omap2_mcspi_rx_dma()
535 elements = element_count - 1; in omap2_mcspi_rx_dma()
538 elements--; in omap2_mcspi_rx_dma()
546 ((u8 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
548 ((u16 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
550 ((u32 *)xfer->rx_buf)[elements++] = w; in omap2_mcspi_rx_dma()
553 dev_err(&spi->dev, "DMA RX penultimate word empty\n"); in omap2_mcspi_rx_dma()
554 count -= (bytes_per_word << 1); in omap2_mcspi_rx_dma()
564 ((u8 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
566 ((u16 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
568 ((u32 *)xfer->rx_buf)[elements] = w; in omap2_mcspi_rx_dma()
570 dev_err(&spi->dev, "DMA RX last word empty\n"); in omap2_mcspi_rx_dma()
571 count -= mcspi_bytes_per_word(word_len); in omap2_mcspi_rx_dma()
581 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_dma() local
593 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_txrx_dma()
594 mcspi_dma = &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_txrx_dma()
596 if (cs->word_len <= 8) { in omap2_mcspi_txrx_dma()
599 } else if (cs->word_len <= 16) { in omap2_mcspi_txrx_dma()
601 es = 2; in omap2_mcspi_txrx_dma()
607 count = xfer->len; in omap2_mcspi_txrx_dma()
610 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0; in omap2_mcspi_txrx_dma()
611 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; in omap2_mcspi_txrx_dma()
617 rx = xfer->rx_buf; in omap2_mcspi_txrx_dma()
618 tx = xfer->tx_buf; in omap2_mcspi_txrx_dma()
620 mcspi->slave_aborted = false; in omap2_mcspi_txrx_dma()
621 reinit_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
622 reinit_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_txrx_dma()
623 reinit_completion(&mcspi->txdone); in omap2_mcspi_txrx_dma()
626 if (spi_controller_is_slave(spi->master)) in omap2_mcspi_txrx_dma()
627 mcspi_write_reg(spi->master, in omap2_mcspi_txrx_dma()
639 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion); in omap2_mcspi_txrx_dma()
640 if (ret || mcspi->slave_aborted) { in omap2_mcspi_txrx_dma()
641 dmaengine_terminate_sync(mcspi_dma->dma_tx); in omap2_mcspi_txrx_dma()
646 if (spi_controller_is_slave(mcspi->master)) { in omap2_mcspi_txrx_dma()
647 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone); in omap2_mcspi_txrx_dma()
648 if (ret || mcspi->slave_aborted) in omap2_mcspi_txrx_dma()
652 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
653 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS; in omap2_mcspi_txrx_dma()
657 dev_err(&spi->dev, "EOW timed out\n"); in omap2_mcspi_txrx_dma()
659 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS, in omap2_mcspi_txrx_dma()
665 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0; in omap2_mcspi_txrx_dma()
666 if (mcspi->fifo_depth > 0) { in omap2_mcspi_txrx_dma()
670 dev_err(&spi->dev, "TXFFE timed out\n"); in omap2_mcspi_txrx_dma()
675 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_dma()
680 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_dma()
689 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_txrx_pio() local
692 void __iomem *base = cs->base; in omap2_mcspi_txrx_pio()
698 count = xfer->len; in omap2_mcspi_txrx_pio()
700 word_len = cs->word_len; in omap2_mcspi_txrx_pio()
704 /* We store the pre-calculated register addresses on stack to speed in omap2_mcspi_txrx_pio()
717 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
718 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
721 c -= 1; in omap2_mcspi_txrx_pio()
725 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
728 dev_vdbg(&spi->dev, "write-%d %02x\n", in omap2_mcspi_txrx_pio()
735 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
743 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
744 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
747 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
757 dev_vdbg(&spi->dev, "read-%d %02x\n", in omap2_mcspi_txrx_pio()
758 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
761 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
767 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
768 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
770 c -= 2; in omap2_mcspi_txrx_pio()
774 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
777 dev_vdbg(&spi->dev, "write-%d %04x\n", in omap2_mcspi_txrx_pio()
784 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
788 if (c == 2 && tx == NULL && in omap2_mcspi_txrx_pio()
792 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
793 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
796 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
806 dev_vdbg(&spi->dev, "read-%d %04x\n", in omap2_mcspi_txrx_pio()
807 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
810 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
811 } while (c >= 2); in omap2_mcspi_txrx_pio()
816 rx = xfer->rx_buf; in omap2_mcspi_txrx_pio()
817 tx = xfer->tx_buf; in omap2_mcspi_txrx_pio()
819 c -= 4; in omap2_mcspi_txrx_pio()
823 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
826 dev_vdbg(&spi->dev, "write-%d %08x\n", in omap2_mcspi_txrx_pio()
833 dev_err(&spi->dev, "RXS timed out\n"); in omap2_mcspi_txrx_pio()
841 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
842 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
845 dev_err(&spi->dev, in omap2_mcspi_txrx_pio()
855 dev_vdbg(&spi->dev, "read-%d %08x\n", in omap2_mcspi_txrx_pio()
856 word_len, *(rx - 1)); in omap2_mcspi_txrx_pio()
859 spi_delay_exec(&xfer->word_delay, xfer); in omap2_mcspi_txrx_pio()
864 if (xfer->rx_buf == NULL) { in omap2_mcspi_txrx_pio()
867 dev_err(&spi->dev, "TXS timed out\n"); in omap2_mcspi_txrx_pio()
870 dev_err(&spi->dev, "EOT timed out\n"); in omap2_mcspi_txrx_pio()
880 return count - c; in omap2_mcspi_txrx_pio()
898 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup_transfer() local
901 u8 word_len = spi->bits_per_word; in omap2_mcspi_setup_transfer()
902 u32 speed_hz = spi->max_speed_hz; in omap2_mcspi_setup_transfer()
904 mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_setup_transfer()
906 if (t != NULL && t->bits_per_word) in omap2_mcspi_setup_transfer()
907 word_len = t->bits_per_word; in omap2_mcspi_setup_transfer()
909 cs->word_len = word_len; in omap2_mcspi_setup_transfer()
911 if (t && t->speed_hz) in omap2_mcspi_setup_transfer()
912 speed_hz = t->speed_hz; in omap2_mcspi_setup_transfer()
920 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz; in omap2_mcspi_setup_transfer()
922 clkd = (div - 1) & 0xf; in omap2_mcspi_setup_transfer()
923 extclk = (div - 1) >> 4; in omap2_mcspi_setup_transfer()
929 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS in omap2_mcspi_setup_transfer()
932 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) { in omap2_mcspi_setup_transfer()
944 l |= (word_len - 1) << 7; in omap2_mcspi_setup_transfer()
947 if (!(spi->mode & SPI_CS_HIGH)) in omap2_mcspi_setup_transfer()
948 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */ in omap2_mcspi_setup_transfer()
954 l |= clkd << 2; in omap2_mcspi_setup_transfer()
960 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK; in omap2_mcspi_setup_transfer()
961 cs->chctrl0 |= extclk << 8; in omap2_mcspi_setup_transfer()
962 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0); in omap2_mcspi_setup_transfer()
966 if (spi->mode & SPI_CPOL) in omap2_mcspi_setup_transfer()
970 if (spi->mode & SPI_CPHA) in omap2_mcspi_setup_transfer()
977 cs->mode = spi->mode; in omap2_mcspi_setup_transfer()
979 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n", in omap2_mcspi_setup_transfer()
981 (spi->mode & SPI_CPHA) ? "trailing" : "leading", in omap2_mcspi_setup_transfer()
982 (spi->mode & SPI_CPOL) ? "inverted" : "normal"); in omap2_mcspi_setup_transfer()
996 mcspi_dma->dma_rx = dma_request_chan(mcspi->dev, in omap2_mcspi_request_dma()
997 mcspi_dma->dma_rx_ch_name); in omap2_mcspi_request_dma()
998 if (IS_ERR(mcspi_dma->dma_rx)) { in omap2_mcspi_request_dma()
999 ret = PTR_ERR(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
1000 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
1004 mcspi_dma->dma_tx = dma_request_chan(mcspi->dev, in omap2_mcspi_request_dma()
1005 mcspi_dma->dma_tx_ch_name); in omap2_mcspi_request_dma()
1006 if (IS_ERR(mcspi_dma->dma_tx)) { in omap2_mcspi_request_dma()
1007 ret = PTR_ERR(mcspi_dma->dma_tx); in omap2_mcspi_request_dma()
1008 mcspi_dma->dma_tx = NULL; in omap2_mcspi_request_dma()
1009 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_request_dma()
1010 mcspi_dma->dma_rx = NULL; in omap2_mcspi_request_dma()
1013 init_completion(&mcspi_dma->dma_rx_completion); in omap2_mcspi_request_dma()
1014 init_completion(&mcspi_dma->dma_tx_completion); in omap2_mcspi_request_dma()
1026 for (i = 0; i < master->num_chipselect; i++) { in omap2_mcspi_release_dma()
1027 mcspi_dma = &mcspi->dma_channels[i]; in omap2_mcspi_release_dma()
1029 if (mcspi_dma->dma_rx) { in omap2_mcspi_release_dma()
1030 dma_release_channel(mcspi_dma->dma_rx); in omap2_mcspi_release_dma()
1031 mcspi_dma->dma_rx = NULL; in omap2_mcspi_release_dma()
1033 if (mcspi_dma->dma_tx) { in omap2_mcspi_release_dma()
1034 dma_release_channel(mcspi_dma->dma_tx); in omap2_mcspi_release_dma()
1035 mcspi_dma->dma_tx = NULL; in omap2_mcspi_release_dma()
1042 struct omap2_mcspi_cs *cs; in omap2_mcspi_cleanup() local
1044 if (spi->controller_state) { in omap2_mcspi_cleanup()
1046 cs = spi->controller_state; in omap2_mcspi_cleanup()
1047 list_del(&cs->node); in omap2_mcspi_cleanup()
1049 kfree(cs); in omap2_mcspi_cleanup()
1057 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_setup()
1058 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_setup()
1059 struct omap2_mcspi_cs *cs = spi->controller_state; in omap2_mcspi_setup() local
1061 if (!cs) { in omap2_mcspi_setup()
1062 cs = kzalloc(sizeof(*cs), GFP_KERNEL); in omap2_mcspi_setup()
1063 if (!cs) in omap2_mcspi_setup()
1064 return -ENOMEM; in omap2_mcspi_setup()
1065 cs->base = mcspi->base + spi->chip_select * 0x14; in omap2_mcspi_setup()
1066 cs->phys = mcspi->phys + spi->chip_select * 0x14; in omap2_mcspi_setup()
1067 cs->mode = 0; in omap2_mcspi_setup()
1068 cs->chconf0 = 0; in omap2_mcspi_setup()
1069 cs->chctrl0 = 0; in omap2_mcspi_setup()
1070 spi->controller_state = cs; in omap2_mcspi_setup()
1072 list_add_tail(&cs->node, &ctx->cs); in omap2_mcspi_setup()
1076 ret = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_setup()
1088 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_setup()
1089 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_setup()
1099 irqstat = mcspi_read_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS); in omap2_mcspi_irq_handler()
1104 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQENABLE, 0); in omap2_mcspi_irq_handler()
1106 complete(&mcspi->txdone); in omap2_mcspi_irq_handler()
1114 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels; in omap2_mcspi_slave_abort()
1116 mcspi->slave_aborted = true; in omap2_mcspi_slave_abort()
1117 complete(&mcspi_dma->dma_rx_completion); in omap2_mcspi_slave_abort()
1118 complete(&mcspi_dma->dma_tx_completion); in omap2_mcspi_slave_abort()
1119 complete(&mcspi->txdone); in omap2_mcspi_slave_abort()
1129 /* We only enable one channel at a time -- the one whose message is in omap2_mcspi_transfer_one()
1130 * -- although this controller would gladly in omap2_mcspi_transfer_one()
1133 * chipselect with the FORCE bit ... CS != channel enable. in omap2_mcspi_transfer_one()
1138 struct omap2_mcspi_cs *cs; in omap2_mcspi_transfer_one() local
1145 mcspi_dma = mcspi->dma_channels + spi->chip_select; in omap2_mcspi_transfer_one()
1146 cs = spi->controller_state; in omap2_mcspi_transfer_one()
1147 cd = spi->controller_data; in omap2_mcspi_transfer_one()
1150 * The slave driver could have changed spi->mode in which case in omap2_mcspi_transfer_one()
1151 * it will be different from cs->mode (the current hardware setup). in omap2_mcspi_transfer_one()
1156 if (spi->mode != cs->mode) in omap2_mcspi_transfer_one()
1161 if (spi->cs_gpiod) in omap2_mcspi_transfer_one()
1162 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); in omap2_mcspi_transfer_one()
1165 (t->speed_hz != spi->max_speed_hz) || in omap2_mcspi_transfer_one()
1166 (t->bits_per_word != spi->bits_per_word)) { in omap2_mcspi_transfer_one()
1171 if (t->speed_hz == spi->max_speed_hz && in omap2_mcspi_transfer_one()
1172 t->bits_per_word == spi->bits_per_word) in omap2_mcspi_transfer_one()
1175 if (cd && cd->cs_per_word) { in omap2_mcspi_transfer_one()
1176 chconf = mcspi->ctx.modulctrl; in omap2_mcspi_transfer_one()
1179 mcspi->ctx.modulctrl = in omap2_mcspi_transfer_one()
1187 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1189 else if (t->rx_buf == NULL) in omap2_mcspi_transfer_one()
1192 if (cd && cd->turbo_mode && t->tx_buf == NULL) { in omap2_mcspi_transfer_one()
1194 if (t->len > ((cs->word_len + 7) >> 3)) in omap2_mcspi_transfer_one()
1200 if (t->len) { in omap2_mcspi_transfer_one()
1203 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1204 master->cur_msg_mapped && in omap2_mcspi_transfer_one()
1205 master->can_dma(master, spi, t)) in omap2_mcspi_transfer_one()
1211 if (t->tx_buf == NULL) in omap2_mcspi_transfer_one()
1212 writel_relaxed(0, cs->base in omap2_mcspi_transfer_one()
1215 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && in omap2_mcspi_transfer_one()
1216 master->cur_msg_mapped && in omap2_mcspi_transfer_one()
1217 master->can_dma(master, spi, t)) in omap2_mcspi_transfer_one()
1222 if (count != t->len) { in omap2_mcspi_transfer_one()
1223 status = -EIO; in omap2_mcspi_transfer_one()
1230 if (mcspi->fifo_depth > 0) in omap2_mcspi_transfer_one()
1240 if (cd && cd->cs_per_word) { in omap2_mcspi_transfer_one()
1241 chconf = mcspi->ctx.modulctrl; in omap2_mcspi_transfer_one()
1244 mcspi->ctx.modulctrl = in omap2_mcspi_transfer_one()
1250 if (spi->cs_gpiod) in omap2_mcspi_transfer_one()
1251 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); in omap2_mcspi_transfer_one()
1253 if (mcspi->fifo_depth > 0 && t) in omap2_mcspi_transfer_one()
1263 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_prepare_message()
1264 struct omap2_mcspi_cs *cs; in omap2_mcspi_prepare_message() local
1271 list_for_each_entry(cs, &ctx->cs, node) { in omap2_mcspi_prepare_message()
1272 if (msg->spi->controller_state == cs) in omap2_mcspi_prepare_message()
1275 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) { in omap2_mcspi_prepare_message()
1276 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap2_mcspi_prepare_message()
1277 writel_relaxed(cs->chconf0, in omap2_mcspi_prepare_message()
1278 cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1279 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0); in omap2_mcspi_prepare_message()
1290 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_can_dma()
1292 &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_can_dma()
1294 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) in omap2_mcspi_can_dma()
1300 master->dma_rx = mcspi_dma->dma_rx; in omap2_mcspi_can_dma()
1301 master->dma_tx = mcspi_dma->dma_tx; in omap2_mcspi_can_dma()
1303 return (xfer->len >= DMA_MIN_BYTES); in omap2_mcspi_can_dma()
1308 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master); in omap2_mcspi_max_xfer_size()
1310 &mcspi->dma_channels[spi->chip_select]; in omap2_mcspi_max_xfer_size()
1312 if (mcspi->max_xfer_len && mcspi_dma->dma_rx) in omap2_mcspi_max_xfer_size()
1313 return mcspi->max_xfer_len; in omap2_mcspi_max_xfer_size()
1320 struct spi_master *master = mcspi->master; in omap2_mcspi_controller_setup()
1321 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap2_mcspi_controller_setup()
1324 ret = pm_runtime_resume_and_get(mcspi->dev); in omap2_mcspi_controller_setup()
1330 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN; in omap2_mcspi_controller_setup()
1333 pm_runtime_mark_last_busy(mcspi->dev); in omap2_mcspi_controller_setup()
1334 pm_runtime_put_autosuspend(mcspi->dev); in omap2_mcspi_controller_setup()
1350 * When SPI wake up from off-mode, CS is in activate state. If it was in
1358 struct omap2_mcspi_regs *ctx = &mcspi->ctx; in omap_mcspi_runtime_resume()
1359 struct omap2_mcspi_cs *cs; in omap_mcspi_runtime_resume() local
1367 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl); in omap_mcspi_runtime_resume()
1368 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable); in omap_mcspi_runtime_resume()
1370 list_for_each_entry(cs, &ctx->cs, node) { in omap_mcspi_runtime_resume()
1372 * We need to toggle CS state for OMAP take this in omap_mcspi_runtime_resume()
1375 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) { in omap_mcspi_runtime_resume()
1376 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1377 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1378 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1379 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE; in omap_mcspi_runtime_resume()
1380 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1381 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1383 writel_relaxed(cs->chconf0, in omap_mcspi_runtime_resume()
1384 cs->base + OMAP2_MCSPI_CHCONF0); in omap_mcspi_runtime_resume()
1401 .max_xfer_len = SZ_4K - 1,
1406 .compatible = "ti,omap2-mcspi",
1410 .compatible = "ti,omap4-mcspi",
1414 .compatible = "ti,am654-mcspi",
1429 struct device_node *node = pdev->dev.of_node; in omap2_mcspi_probe()
1432 if (of_property_read_bool(node, "spi-slave")) in omap2_mcspi_probe()
1433 master = spi_alloc_slave(&pdev->dev, sizeof(*mcspi)); in omap2_mcspi_probe()
1435 master = spi_alloc_master(&pdev->dev, sizeof(*mcspi)); in omap2_mcspi_probe()
1437 return -ENOMEM; in omap2_mcspi_probe()
1439 /* the spi->mode bits understood by this driver: */ in omap2_mcspi_probe()
1440 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in omap2_mcspi_probe()
1441 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in omap2_mcspi_probe()
1442 master->setup = omap2_mcspi_setup; in omap2_mcspi_probe()
1443 master->auto_runtime_pm = true; in omap2_mcspi_probe()
1444 master->prepare_message = omap2_mcspi_prepare_message; in omap2_mcspi_probe()
1445 master->can_dma = omap2_mcspi_can_dma; in omap2_mcspi_probe()
1446 master->transfer_one = omap2_mcspi_transfer_one; in omap2_mcspi_probe()
1447 master->set_cs = omap2_mcspi_set_cs; in omap2_mcspi_probe()
1448 master->cleanup = omap2_mcspi_cleanup; in omap2_mcspi_probe()
1449 master->slave_abort = omap2_mcspi_slave_abort; in omap2_mcspi_probe()
1450 master->dev.of_node = node; in omap2_mcspi_probe()
1451 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; in omap2_mcspi_probe()
1452 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15; in omap2_mcspi_probe()
1453 master->use_gpio_descriptors = true; in omap2_mcspi_probe()
1458 mcspi->master = master; in omap2_mcspi_probe()
1460 match = of_match_device(omap_mcspi_of_match, &pdev->dev); in omap2_mcspi_probe()
1463 pdata = match->data; in omap2_mcspi_probe()
1465 of_property_read_u32(node, "ti,spi-num-cs", &num_cs); in omap2_mcspi_probe()
1466 master->num_chipselect = num_cs; in omap2_mcspi_probe()
1467 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL)) in omap2_mcspi_probe()
1468 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN; in omap2_mcspi_probe()
1470 pdata = dev_get_platdata(&pdev->dev); in omap2_mcspi_probe()
1471 master->num_chipselect = pdata->num_cs; in omap2_mcspi_probe()
1472 mcspi->pin_dir = pdata->pin_dir; in omap2_mcspi_probe()
1474 regs_offset = pdata->regs_offset; in omap2_mcspi_probe()
1475 if (pdata->max_xfer_len) { in omap2_mcspi_probe()
1476 mcspi->max_xfer_len = pdata->max_xfer_len; in omap2_mcspi_probe()
1477 master->max_transfer_size = omap2_mcspi_max_xfer_size; in omap2_mcspi_probe()
1481 mcspi->base = devm_ioremap_resource(&pdev->dev, r); in omap2_mcspi_probe()
1482 if (IS_ERR(mcspi->base)) { in omap2_mcspi_probe()
1483 status = PTR_ERR(mcspi->base); in omap2_mcspi_probe()
1486 mcspi->phys = r->start + regs_offset; in omap2_mcspi_probe()
1487 mcspi->base += regs_offset; in omap2_mcspi_probe()
1489 mcspi->dev = &pdev->dev; in omap2_mcspi_probe()
1491 INIT_LIST_HEAD(&mcspi->ctx.cs); in omap2_mcspi_probe()
1493 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect, in omap2_mcspi_probe()
1496 if (mcspi->dma_channels == NULL) { in omap2_mcspi_probe()
1497 status = -ENOMEM; in omap2_mcspi_probe()
1501 for (i = 0; i < master->num_chipselect; i++) { in omap2_mcspi_probe()
1502 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i); in omap2_mcspi_probe()
1503 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i); in omap2_mcspi_probe()
1506 &mcspi->dma_channels[i]); in omap2_mcspi_probe()
1507 if (status == -EPROBE_DEFER) in omap2_mcspi_probe()
1513 dev_err_probe(&pdev->dev, status, "no irq resource found\n"); in omap2_mcspi_probe()
1516 init_completion(&mcspi->txdone); in omap2_mcspi_probe()
1517 status = devm_request_irq(&pdev->dev, status, in omap2_mcspi_probe()
1518 omap2_mcspi_irq_handler, 0, pdev->name, in omap2_mcspi_probe()
1521 dev_err(&pdev->dev, "Cannot request IRQ"); in omap2_mcspi_probe()
1525 pm_runtime_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1526 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); in omap2_mcspi_probe()
1527 pm_runtime_enable(&pdev->dev); in omap2_mcspi_probe()
1533 status = devm_spi_register_controller(&pdev->dev, master); in omap2_mcspi_probe()
1540 pm_runtime_dont_use_autosuspend(&pdev->dev); in omap2_mcspi_probe()
1541 pm_runtime_put_sync(&pdev->dev); in omap2_mcspi_probe()
1542 pm_runtime_disable(&pdev->dev); in omap2_mcspi_probe()
1556 pm_runtime_dont_use_autosuspend(mcspi->dev); in omap2_mcspi_remove()
1557 pm_runtime_put_sync(mcspi->dev); in omap2_mcspi_remove()
1558 pm_runtime_disable(&pdev->dev); in omap2_mcspi_remove()
1574 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n", in omap2_mcspi_suspend()
1579 dev_warn(mcspi->dev, "%s: master suspend failed: %i\n", in omap2_mcspi_suspend()
1593 dev_warn(mcspi->dev, "%s: master resume failed: %i\n", in omap2_mcspi_resume()