Lines Matching +full:npcm845 +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
16 #include <linux/spi/spi-mem.h>
107 /* FIU UMA Write Data Bytes 0-3 Register */
113 /* FIU UMA Write Data Bytes 4-7 Register */
119 /* FIU UMA Write Data Bytes 8-11 Register */
125 /* FIU UMA Write Data Bytes 12-15 Register */
131 /* FIU UMA Read Data Bytes 0-3 Register */
137 /* FIU UMA Read Data Bytes 4-7 Register */
143 /* FIU UMA Read Data Bytes 8-11 Register */
149 /* FIU UMA Read Data Bytes 12-15 Register */
254 struct clk *clk; member
268 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiu_set_drd()
270 ilog2(op->addr.buswidth) << in npcm_fiu_set_drd()
272 fiu->drd_op.addr.buswidth = op->addr.buswidth; in npcm_fiu_set_drd()
273 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiu_set_drd()
275 op->dummy.nbytes << NPCM_FIU_DRD_DBW_SHIFT); in npcm_fiu_set_drd()
276 fiu->drd_op.dummy.nbytes = op->dummy.nbytes; in npcm_fiu_set_drd()
277 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiu_set_drd()
278 NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode); in npcm_fiu_set_drd()
279 fiu->drd_op.cmd.opcode = op->cmd.opcode; in npcm_fiu_set_drd()
280 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiu_set_drd()
282 (op->addr.nbytes - 3) << NPCM_FIU_DRD_ADDSIZ_SHIFT); in npcm_fiu_set_drd()
283 fiu->drd_op.addr.nbytes = op->addr.nbytes; in npcm_fiu_set_drd()
290 spi_controller_get_devdata(desc->mem->spi->master); in npcm_fiu_direct_read()
291 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; in npcm_fiu_direct_read()
292 void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr + in npcm_fiu_direct_read()
297 if (fiu->spix_mode) { in npcm_fiu_direct_read()
301 if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth || in npcm_fiu_direct_read()
302 desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes || in npcm_fiu_direct_read()
303 desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode || in npcm_fiu_direct_read()
304 desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes) in npcm_fiu_direct_read()
305 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl); in npcm_fiu_direct_read()
317 spi_controller_get_devdata(desc->mem->spi->master); in npcm_fiu_direct_write()
318 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; in npcm_fiu_direct_write()
319 void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr + in npcm_fiu_direct_write()
324 if (fiu->spix_mode) in npcm_fiu_direct_write()
338 spi_controller_get_devdata(mem->spi->master); in npcm_fiu_uma_read()
345 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_uma_read()
347 (mem->spi->chip_select << in npcm_fiu_uma_read()
349 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, in npcm_fiu_uma_read()
350 NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode); in npcm_fiu_uma_read()
353 uma_cfg |= ilog2(op->cmd.buswidth); in npcm_fiu_uma_read()
354 uma_cfg |= ilog2(op->addr.buswidth) in npcm_fiu_uma_read()
356 uma_cfg |= ilog2(op->dummy.buswidth) in npcm_fiu_uma_read()
358 uma_cfg |= ilog2(op->data.buswidth) in npcm_fiu_uma_read()
360 uma_cfg |= op->dummy.nbytes << NPCM_FIU_UMA_CFG_DBSIZ_SHIFT; in npcm_fiu_uma_read()
361 uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT; in npcm_fiu_uma_read()
362 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr); in npcm_fiu_uma_read()
364 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0); in npcm_fiu_uma_read()
368 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg); in npcm_fiu_uma_read()
369 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_uma_read()
372 ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, in npcm_fiu_uma_read()
380 regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4), in npcm_fiu_uma_read()
393 spi_controller_get_devdata(mem->spi->master); in npcm_fiu_uma_write()
399 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_uma_write()
401 (mem->spi->chip_select << in npcm_fiu_uma_write()
404 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, in npcm_fiu_uma_write()
410 regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4), in npcm_fiu_uma_write()
415 uma_cfg |= ilog2(op->cmd.buswidth); in npcm_fiu_uma_write()
416 uma_cfg |= ilog2(op->addr.buswidth) << in npcm_fiu_uma_write()
418 uma_cfg |= ilog2(op->data.buswidth) << in npcm_fiu_uma_write()
420 uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT; in npcm_fiu_uma_write()
421 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val); in npcm_fiu_uma_write()
423 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0); in npcm_fiu_uma_write()
427 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg); in npcm_fiu_uma_write()
429 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_uma_write()
433 return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, in npcm_fiu_uma_write()
442 spi_controller_get_devdata(mem->spi->master); in npcm_fiu_manualwrite()
443 u8 *data = (u8 *)op->data.buf.out; in npcm_fiu_manualwrite()
449 num_data_chunks = op->data.nbytes / CHUNK_SIZE; in npcm_fiu_manualwrite()
450 remain_data = op->data.nbytes % CHUNK_SIZE; in npcm_fiu_manualwrite()
452 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_manualwrite()
454 (mem->spi->chip_select << in npcm_fiu_manualwrite()
456 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_manualwrite()
459 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, true, NULL, 0); in npcm_fiu_manualwrite()
466 &data[1], CHUNK_SIZE - 1); in npcm_fiu_manualwrite()
476 &data[1], remain_data - 1); in npcm_fiu_manualwrite()
481 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, in npcm_fiu_manualwrite()
489 u8 *data = op->data.buf.in; in npcm_fiu_read()
496 currlen = op->data.nbytes; in npcm_fiu_read()
499 addr = ((u32)op->addr.val + i); in npcm_fiu_read()
512 currlen -= 16; in npcm_fiu_read()
520 regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG, in npcm_fiux_set_direct_wr()
522 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG, in npcm_fiux_set_direct_wr()
525 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG, in npcm_fiux_set_direct_wr()
534 regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiux_set_direct_rd()
536 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiux_set_direct_rd()
539 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, in npcm_fiux_set_direct_rd()
547 spi_controller_get_devdata(mem->spi->master); in npcm_fiu_exec_op()
548 struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select]; in npcm_fiu_exec_op()
552 dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", in npcm_fiu_exec_op()
553 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, in npcm_fiu_exec_op()
554 op->dummy.buswidth, op->data.buswidth, op->addr.val, in npcm_fiu_exec_op()
555 op->data.nbytes); in npcm_fiu_exec_op()
557 if (fiu->spix_mode || op->addr.nbytes > 4) in npcm_fiu_exec_op()
558 return -ENOTSUPP; in npcm_fiu_exec_op()
560 if (fiu->clkrate != chip->clkrate) { in npcm_fiu_exec_op()
561 ret = clk_set_rate(fiu->clk, chip->clkrate); in npcm_fiu_exec_op()
563 dev_warn(fiu->dev, "Failed setting %lu frequency, stay at %lu frequency\n", in npcm_fiu_exec_op()
564 chip->clkrate, fiu->clkrate); in npcm_fiu_exec_op()
566 fiu->clkrate = chip->clkrate; in npcm_fiu_exec_op()
569 if (op->data.dir == SPI_MEM_DATA_IN) { in npcm_fiu_exec_op()
570 if (!op->addr.nbytes) { in npcm_fiu_exec_op()
571 buf = op->data.buf.in; in npcm_fiu_exec_op()
572 ret = npcm_fiu_uma_read(mem, op, op->addr.val, false, in npcm_fiu_exec_op()
573 buf, op->data.nbytes); in npcm_fiu_exec_op()
578 if (!op->addr.nbytes && !op->data.nbytes) in npcm_fiu_exec_op()
579 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, in npcm_fiu_exec_op()
581 if (op->addr.nbytes && !op->data.nbytes) { in npcm_fiu_exec_op()
584 u32 addr = op->addr.val; in npcm_fiu_exec_op()
586 for (i = op->addr.nbytes - 1; i >= 0; i--) { in npcm_fiu_exec_op()
590 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, in npcm_fiu_exec_op()
591 buf_addr, op->addr.nbytes); in npcm_fiu_exec_op()
593 if (!op->addr.nbytes && op->data.nbytes) in npcm_fiu_exec_op()
594 ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, in npcm_fiu_exec_op()
595 (u8 *)op->data.buf.out, in npcm_fiu_exec_op()
596 op->data.nbytes); in npcm_fiu_exec_op()
597 if (op->addr.nbytes && op->data.nbytes) in npcm_fiu_exec_op()
607 spi_controller_get_devdata(desc->mem->spi->master); in npcm_fiu_dirmap_create()
608 struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; in npcm_fiu_dirmap_create()
611 if (!fiu->res_mem) { in npcm_fiu_dirmap_create()
612 dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n"); in npcm_fiu_dirmap_create()
613 desc->nodirmap = true; in npcm_fiu_dirmap_create()
617 if (!fiu->spix_mode && in npcm_fiu_dirmap_create()
618 desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { in npcm_fiu_dirmap_create()
619 desc->nodirmap = true; in npcm_fiu_dirmap_create()
623 if (!chip->flash_region_mapped_ptr) { in npcm_fiu_dirmap_create()
624 chip->flash_region_mapped_ptr = in npcm_fiu_dirmap_create()
625 devm_ioremap(fiu->dev, (fiu->res_mem->start + in npcm_fiu_dirmap_create()
626 (fiu->info->max_map_size * in npcm_fiu_dirmap_create()
627 desc->mem->spi->chip_select)), in npcm_fiu_dirmap_create()
628 (u32)desc->info.length); in npcm_fiu_dirmap_create()
629 if (!chip->flash_region_mapped_ptr) { in npcm_fiu_dirmap_create()
630 dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n"); in npcm_fiu_dirmap_create()
631 desc->nodirmap = true; in npcm_fiu_dirmap_create()
636 if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) { in npcm_fiu_dirmap_create()
638 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); in npcm_fiu_dirmap_create()
640 dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n"); in npcm_fiu_dirmap_create()
641 desc->nodirmap = true; in npcm_fiu_dirmap_create()
648 regmap_update_bits(fiu->regmap, NPCM_FIU_CFG, in npcm_fiu_dirmap_create()
653 if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) { in npcm_fiu_dirmap_create()
654 if (!fiu->spix_mode) in npcm_fiu_dirmap_create()
655 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl); in npcm_fiu_dirmap_create()
668 struct spi_controller *ctrl = spi->master; in npcm_fiu_setup()
672 chip = &fiu->chip[spi->chip_select]; in npcm_fiu_setup()
673 chip->fiu = fiu; in npcm_fiu_setup()
674 chip->chipselect = spi->chip_select; in npcm_fiu_setup()
675 chip->clkrate = spi->max_speed_hz; in npcm_fiu_setup()
677 fiu->clkrate = clk_get_rate(fiu->clk); in npcm_fiu_setup()
690 { .compatible = "nuvoton,npcm750-fiu", .data = &npcm7xx_fiu_data },
691 { .compatible = "nuvoton,npcm845-fiu", .data = &npxm8xx_fiu_data },
698 struct device *dev = &pdev->dev; in npcm_fiu_probe()
707 return -ENOMEM; in npcm_fiu_probe()
714 return -ENODEV; in npcm_fiu_probe()
717 id = of_alias_get_id(dev->of_node, "fiu"); in npcm_fiu_probe()
718 if (id < 0 || id >= fiu_data_match->fiu_max) { in npcm_fiu_probe()
720 return -EINVAL; in npcm_fiu_probe()
723 fiu->info = &fiu_data_match->npcm_fiu_data_info[id]; in npcm_fiu_probe()
726 fiu->dev = dev; in npcm_fiu_probe()
733 fiu->regmap = devm_regmap_init_mmio(dev, regbase, in npcm_fiu_probe()
735 if (IS_ERR(fiu->regmap)) { in npcm_fiu_probe()
737 return PTR_ERR(fiu->regmap); in npcm_fiu_probe()
740 fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, in npcm_fiu_probe()
742 fiu->clk = devm_clk_get(dev, NULL); in npcm_fiu_probe()
743 if (IS_ERR(fiu->clk)) in npcm_fiu_probe()
744 return PTR_ERR(fiu->clk); in npcm_fiu_probe()
746 fiu->spix_mode = of_property_read_bool(dev->of_node, in npcm_fiu_probe()
747 "nuvoton,spix-mode"); in npcm_fiu_probe()
750 clk_prepare_enable(fiu->clk); in npcm_fiu_probe()
752 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD in npcm_fiu_probe()
754 ctrl->setup = npcm_fiu_setup; in npcm_fiu_probe()
755 ctrl->bus_num = -1; in npcm_fiu_probe()
756 ctrl->mem_ops = &npcm_fiu_mem_ops; in npcm_fiu_probe()
757 ctrl->num_chipselect = fiu->info->max_cs; in npcm_fiu_probe()
758 ctrl->dev.of_node = dev->of_node; in npcm_fiu_probe()
762 clk_disable_unprepare(fiu->clk); in npcm_fiu_probe()
771 clk_disable_unprepare(fiu->clk); in npcm_fiu_remove()
779 .name = "NPCM-FIU",