Lines Matching +full:pio +full:- +full:transfer
1 // SPDX-License-Identifier: GPL-2.0+
15 // Based on code from U-Boot bootloader by:
18 // Based on spi-stmp.c, which is:
28 #include <linux/dma-mapping.h>
40 #include <linux/spi/mxs-spi.h>
43 #define DRIVER_NAME "mxs-spi"
55 #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
66 struct mxs_spi *spi = spi_master_get_devdata(dev->master); in mxs_spi_setup_transfer()
67 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_setup_transfer()
68 const unsigned int hz = min(dev->max_speed_hz, t->speed_hz); in mxs_spi_setup_transfer()
71 dev_err(&dev->dev, "SPI clock rate of zero not allowed\n"); in mxs_spi_setup_transfer()
72 return -EINVAL; in mxs_spi_setup_transfer()
75 if (hz != spi->sck) { in mxs_spi_setup_transfer()
79 * ssp->clk_rate. Otherwise we would set the rate every transfer in mxs_spi_setup_transfer()
82 spi->sck = hz; in mxs_spi_setup_transfer()
90 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_setup_transfer()
94 ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) | in mxs_spi_setup_transfer()
95 ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0), in mxs_spi_setup_transfer()
96 ssp->base + HW_SSP_CTRL1(ssp)); in mxs_spi_setup_transfer()
98 writel(0x0, ssp->base + HW_SSP_CMD0); in mxs_spi_setup_transfer()
99 writel(0x0, ssp->base + HW_SSP_CMD1); in mxs_spi_setup_transfer()
114 * toggle the chip-select lines (nCS pins). in mxs_spi_cs_to_reg()
127 struct mxs_ssp *ssp = &spi->ssp; in mxs_ssp_wait()
131 reg = readl_relaxed(ssp->base + offset); in mxs_ssp_wait()
142 return -ETIMEDOUT; in mxs_ssp_wait()
149 complete(&spi->c); in mxs_ssp_dma_irq_callback()
156 dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n", in mxs_ssp_irq_handler()
158 readl(ssp->base + HW_SSP_CTRL1(ssp)), in mxs_ssp_irq_handler()
159 readl(ssp->base + HW_SSP_STATUS(ssp))); in mxs_ssp_irq_handler()
167 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_txrx_dma()
177 u32 pio[4]; in mxs_spi_txrx_dma() member
182 return -EINVAL; in mxs_spi_txrx_dma()
186 return -ENOMEM; in mxs_spi_txrx_dma()
188 reinit_completion(&spi->c); in mxs_spi_txrx_dma()
191 ctrl0 = readl(ssp->base + HW_SSP_CTRL0); in mxs_spi_txrx_dma()
199 /* Queue the DMA data transfer. */ in mxs_spi_txrx_dma()
201 /* Prepare the transfer descriptor. */ in mxs_spi_txrx_dma()
205 * De-assert CS on last segment if flag is set (i.e., no more in mxs_spi_txrx_dma()
211 if (ssp->devid == IMX23_SSP) { in mxs_spi_txrx_dma()
216 dma_xfer[sg_count].pio[0] = ctrl0; in mxs_spi_txrx_dma()
217 dma_xfer[sg_count].pio[3] = min; in mxs_spi_txrx_dma()
222 ret = -ENOMEM; in mxs_spi_txrx_dma()
233 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, in mxs_spi_txrx_dma()
236 len -= min; in mxs_spi_txrx_dma()
239 /* Queue the PIO register write transfer. */ in mxs_spi_txrx_dma()
240 desc = dmaengine_prep_slave_sg(ssp->dmach, in mxs_spi_txrx_dma()
241 (struct scatterlist *)dma_xfer[sg_count].pio, in mxs_spi_txrx_dma()
242 (ssp->devid == IMX23_SSP) ? 1 : 4, in mxs_spi_txrx_dma()
246 dev_err(ssp->dev, in mxs_spi_txrx_dma()
247 "Failed to get PIO reg. write descriptor.\n"); in mxs_spi_txrx_dma()
248 ret = -EINVAL; in mxs_spi_txrx_dma()
252 desc = dmaengine_prep_slave_sg(ssp->dmach, in mxs_spi_txrx_dma()
258 dev_err(ssp->dev, in mxs_spi_txrx_dma()
260 ret = -EINVAL; in mxs_spi_txrx_dma()
269 desc->callback = mxs_ssp_dma_irq_callback; in mxs_spi_txrx_dma()
270 desc->callback_param = spi; in mxs_spi_txrx_dma()
272 /* Start the transfer. */ in mxs_spi_txrx_dma()
274 dma_async_issue_pending(ssp->dmach); in mxs_spi_txrx_dma()
276 if (!wait_for_completion_timeout(&spi->c, in mxs_spi_txrx_dma()
278 dev_err(ssp->dev, "DMA transfer timeout\n"); in mxs_spi_txrx_dma()
279 ret = -ETIMEDOUT; in mxs_spi_txrx_dma()
280 dmaengine_terminate_all(ssp->dmach); in mxs_spi_txrx_dma()
287 while (--sg_count >= 0) { in mxs_spi_txrx_dma()
289 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1, in mxs_spi_txrx_dma()
302 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_txrx_pio()
305 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()
307 while (len--) { in mxs_spi_txrx_pio()
310 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()
312 if (ssp->devid == IMX23_SSP) { in mxs_spi_txrx_pio()
314 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()
316 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()
318 writel(1, ssp->base + HW_SSP_XFER_SIZE); in mxs_spi_txrx_pio()
323 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_txrx_pio()
326 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()
329 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()
332 return -ETIMEDOUT; in mxs_spi_txrx_pio()
335 writel(*buf, ssp->base + HW_SSP_DATA(ssp)); in mxs_spi_txrx_pio()
338 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_txrx_pio()
343 return -ETIMEDOUT; in mxs_spi_txrx_pio()
345 *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff); in mxs_spi_txrx_pio()
349 return -ETIMEDOUT; in mxs_spi_txrx_pio()
357 return -ETIMEDOUT; in mxs_spi_txrx_pio()
364 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_transfer_one()
371 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_spi_transfer_one()
372 writel(mxs_spi_cs_to_reg(m->spi->chip_select), in mxs_spi_transfer_one()
373 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); in mxs_spi_transfer_one()
375 list_for_each_entry(t, &m->transfers, transfer_list) { in mxs_spi_transfer_one()
379 status = mxs_spi_setup_transfer(m->spi, t); in mxs_spi_transfer_one()
383 /* De-assert on last transfer, inverted by cs_change flag */ in mxs_spi_transfer_one()
384 flag = (&t->transfer_list == m->transfers.prev) ^ t->cs_change ? in mxs_spi_transfer_one()
388 * Small blocks can be transfered via PIO. in mxs_spi_transfer_one()
396 if (t->len < 32) { in mxs_spi_transfer_one()
398 ssp->base + HW_SSP_CTRL1(ssp) + in mxs_spi_transfer_one()
401 if (t->tx_buf) in mxs_spi_transfer_one()
403 (void *)t->tx_buf, in mxs_spi_transfer_one()
404 t->len, flag | TXRX_WRITE); in mxs_spi_transfer_one()
405 if (t->rx_buf) in mxs_spi_transfer_one()
407 t->rx_buf, t->len, in mxs_spi_transfer_one()
411 ssp->base + HW_SSP_CTRL1(ssp) + in mxs_spi_transfer_one()
414 if (t->tx_buf) in mxs_spi_transfer_one()
416 (void *)t->tx_buf, t->len, in mxs_spi_transfer_one()
418 if (t->rx_buf) in mxs_spi_transfer_one()
420 t->rx_buf, t->len, in mxs_spi_transfer_one()
427 stmp_reset_block(ssp->base); in mxs_spi_transfer_one()
431 m->actual_length += t->len; in mxs_spi_transfer_one()
434 m->status = status; in mxs_spi_transfer_one()
444 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_runtime_suspend()
447 clk_disable_unprepare(ssp->clk); in mxs_spi_runtime_suspend()
451 int ret2 = clk_prepare_enable(ssp->clk); in mxs_spi_runtime_suspend()
465 struct mxs_ssp *ssp = &spi->ssp; in mxs_spi_runtime_resume()
472 ret = clk_prepare_enable(ssp->clk); in mxs_spi_runtime_resume()
520 { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
521 { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
529 of_match_device(mxs_spi_dt_ids, &pdev->dev); in mxs_spi_probe()
530 struct device_node *np = pdev->dev.of_node; in mxs_spi_probe()
542 * as a default. Override with "clock-frequency" DT prop. in mxs_spi_probe()
554 clk = devm_clk_get(&pdev->dev, NULL); in mxs_spi_probe()
558 devid = (enum mxs_ssp_id) of_id->data; in mxs_spi_probe()
559 ret = of_property_read_u32(np, "clock-frequency", in mxs_spi_probe()
564 master = spi_alloc_master(&pdev->dev, sizeof(*spi)); in mxs_spi_probe()
566 return -ENOMEM; in mxs_spi_probe()
570 master->transfer_one_message = mxs_spi_transfer_one; in mxs_spi_probe()
571 master->bits_per_word_mask = SPI_BPW_MASK(8); in mxs_spi_probe()
572 master->mode_bits = SPI_CPOL | SPI_CPHA; in mxs_spi_probe()
573 master->num_chipselect = 3; in mxs_spi_probe()
574 master->dev.of_node = np; in mxs_spi_probe()
575 master->flags = SPI_MASTER_HALF_DUPLEX; in mxs_spi_probe()
576 master->auto_runtime_pm = true; in mxs_spi_probe()
579 ssp = &spi->ssp; in mxs_spi_probe()
580 ssp->dev = &pdev->dev; in mxs_spi_probe()
581 ssp->clk = clk; in mxs_spi_probe()
582 ssp->base = base; in mxs_spi_probe()
583 ssp->devid = devid; in mxs_spi_probe()
585 init_completion(&spi->c); in mxs_spi_probe()
587 ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0, in mxs_spi_probe()
588 dev_name(&pdev->dev), ssp); in mxs_spi_probe()
592 ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx"); in mxs_spi_probe()
593 if (IS_ERR(ssp->dmach)) { in mxs_spi_probe()
594 dev_err(ssp->dev, "Failed to request DMA\n"); in mxs_spi_probe()
595 ret = PTR_ERR(ssp->dmach); in mxs_spi_probe()
599 pm_runtime_enable(ssp->dev); in mxs_spi_probe()
600 if (!pm_runtime_enabled(ssp->dev)) { in mxs_spi_probe()
601 ret = mxs_spi_runtime_resume(ssp->dev); in mxs_spi_probe()
603 dev_err(ssp->dev, "runtime resume failed\n"); in mxs_spi_probe()
608 ret = pm_runtime_resume_and_get(ssp->dev); in mxs_spi_probe()
610 dev_err(ssp->dev, "runtime_get_sync failed\n"); in mxs_spi_probe()
614 clk_set_rate(ssp->clk, clk_freq); in mxs_spi_probe()
616 ret = stmp_reset_block(ssp->base); in mxs_spi_probe()
620 ret = devm_spi_register_master(&pdev->dev, master); in mxs_spi_probe()
622 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret); in mxs_spi_probe()
626 pm_runtime_put(ssp->dev); in mxs_spi_probe()
631 pm_runtime_put(ssp->dev); in mxs_spi_probe()
633 pm_runtime_disable(ssp->dev); in mxs_spi_probe()
635 dma_release_channel(ssp->dmach); in mxs_spi_probe()
649 ssp = &spi->ssp; in mxs_spi_remove()
651 pm_runtime_disable(&pdev->dev); in mxs_spi_remove()
652 if (!pm_runtime_status_suspended(&pdev->dev)) in mxs_spi_remove()
653 mxs_spi_runtime_suspend(&pdev->dev); in mxs_spi_remove()
655 dma_release_channel(ssp->dmach); in mxs_spi_remove()
675 MODULE_ALIAS("platform:mxs-spi");