Lines Matching +full:inactive +full:- +full:delay +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/platform_data/spi-mt65xx.h>
20 #include <linux/spi/spi-mem.h>
21 #include <linux/dma-mapping.h>
114 * struct mtk_spi_compatible - device data structure
132 * struct mtk_spi - SPI driver instance
150 * @spimem_done: SPI-MEM operation completion
151 * @use_spimem: Enables SPI-MEM
153 * @tx_dma: DMA start for SPI-MEM TX
154 * @rx_dma: DMA start for SPI-MEM RX
229 { .compatible = "mediatek,spi-ipm",
232 { .compatible = "mediatek,mt2701-spi",
235 { .compatible = "mediatek,mt2712-spi",
238 { .compatible = "mediatek,mt6589-spi",
241 { .compatible = "mediatek,mt6765-spi",
244 { .compatible = "mediatek,mt7622-spi",
247 { .compatible = "mediatek,mt7629-spi",
250 { .compatible = "mediatek,mt8135-spi",
253 { .compatible = "mediatek,mt8173-spi",
256 { .compatible = "mediatek,mt8183-spi",
259 { .compatible = "mediatek,mt8192-spi",
262 { .compatible = "mediatek,mt6893-spi",
274 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
276 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
278 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
280 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
285 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); in mtk_spi_set_hw_cs_timing()
286 struct spi_delay *cs_setup = &spi->cs_setup; in mtk_spi_set_hw_cs_timing()
287 struct spi_delay *cs_hold = &spi->cs_hold; in mtk_spi_set_hw_cs_timing()
288 struct spi_delay *cs_inactive = &spi->cs_inactive; in mtk_spi_set_hw_cs_timing()
289 u32 setup, hold, inactive; in mtk_spi_set_hw_cs_timing() local
291 int delay; in mtk_spi_set_hw_cs_timing() local
293 delay = spi_delay_to_ns(cs_setup, NULL); in mtk_spi_set_hw_cs_timing()
294 if (delay < 0) in mtk_spi_set_hw_cs_timing()
295 return delay; in mtk_spi_set_hw_cs_timing()
296 setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; in mtk_spi_set_hw_cs_timing()
298 delay = spi_delay_to_ns(cs_hold, NULL); in mtk_spi_set_hw_cs_timing()
299 if (delay < 0) in mtk_spi_set_hw_cs_timing()
300 return delay; in mtk_spi_set_hw_cs_timing()
301 hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; in mtk_spi_set_hw_cs_timing()
303 delay = spi_delay_to_ns(cs_inactive, NULL); in mtk_spi_set_hw_cs_timing()
304 if (delay < 0) in mtk_spi_set_hw_cs_timing()
305 return delay; in mtk_spi_set_hw_cs_timing()
306 inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000; in mtk_spi_set_hw_cs_timing()
309 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
310 if (mdata->dev_comp->enhance_timing) { in mtk_spi_set_hw_cs_timing()
314 reg_val |= (((hold - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
320 reg_val |= (((setup - 1) & 0xffff) in mtk_spi_set_hw_cs_timing()
327 reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_set_hw_cs_timing()
332 reg_val |= (((setup - 1) & 0xff) in mtk_spi_set_hw_cs_timing()
336 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_set_hw_cs_timing()
339 if (inactive) { in mtk_spi_set_hw_cs_timing()
340 inactive = min_t(u32, inactive, 0x100); in mtk_spi_set_hw_cs_timing()
341 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_set_hw_cs_timing()
343 reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); in mtk_spi_set_hw_cs_timing()
344 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_set_hw_cs_timing()
355 struct mtk_chip_config *chip_config = spi->controller_data; in mtk_spi_hw_init()
358 cpha = spi->mode & SPI_CPHA ? 1 : 0; in mtk_spi_hw_init()
359 cpol = spi->mode & SPI_CPOL ? 1 : 0; in mtk_spi_hw_init()
361 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
362 if (mdata->dev_comp->ipm_design) { in mtk_spi_hw_init()
365 if (spi->mode & SPI_LOOP) in mtk_spi_hw_init()
381 if (spi->mode & SPI_LSB_FIRST) { in mtk_spi_hw_init()
398 if (mdata->dev_comp->enhance_timing) { in mtk_spi_hw_init()
400 if (spi->mode & SPI_CS_HIGH) in mtk_spi_hw_init()
405 if (chip_config->sample_sel) in mtk_spi_hw_init()
420 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
423 if (mdata->dev_comp->need_pad_sel) in mtk_spi_hw_init()
424 writel(mdata->pad_sel[spi->chip_select], in mtk_spi_hw_init()
425 mdata->base + SPI_PAD_SEL_REG); in mtk_spi_hw_init()
427 /* tick delay */ in mtk_spi_hw_init()
428 if (mdata->dev_comp->enhance_timing) { in mtk_spi_hw_init()
429 if (mdata->dev_comp->ipm_design) { in mtk_spi_hw_init()
430 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
432 reg_val |= ((chip_config->tick_delay & 0x7) in mtk_spi_hw_init()
434 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_hw_init()
436 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
438 reg_val |= ((chip_config->tick_delay & 0x7) in mtk_spi_hw_init()
440 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
443 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
445 reg_val |= ((chip_config->tick_delay & 0x3) in mtk_spi_hw_init()
447 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_hw_init()
458 return mtk_spi_hw_init(master, msg->spi); in mtk_spi_prepare_message()
464 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); in mtk_spi_set_cs()
466 if (spi->mode & SPI_CS_HIGH) in mtk_spi_set_cs()
469 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
472 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
475 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
476 mdata->state = MTK_SPI_IDLE; in mtk_spi_set_cs()
487 if (speed_hz < mdata->spi_clk_hz / 2) in mtk_spi_prepare_transfer()
488 div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz); in mtk_spi_prepare_transfer()
494 if (mdata->dev_comp->enhance_timing) { in mtk_spi_prepare_transfer()
495 reg_val = readl(mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
497 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
500 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
502 writel(reg_val, mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
504 reg_val = readl(mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
506 reg_val |= (((sck_time - 1) & 0xff) in mtk_spi_prepare_transfer()
509 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
510 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
519 if (mdata->dev_comp->ipm_design) in mtk_spi_setup_packet()
521 mdata->xfer_len, in mtk_spi_setup_packet()
525 mdata->xfer_len, in mtk_spi_setup_packet()
528 packet_loop = mdata->xfer_len / packet_size; in mtk_spi_setup_packet()
530 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
531 if (mdata->dev_comp->ipm_design) in mtk_spi_setup_packet()
535 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; in mtk_spi_setup_packet()
537 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; in mtk_spi_setup_packet()
538 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
546 cmd = readl(mdata->base + SPI_CMD_REG); in mtk_spi_enable_transfer()
547 if (mdata->state == MTK_SPI_IDLE) in mtk_spi_enable_transfer()
551 writel(cmd, mdata->base + SPI_CMD_REG); in mtk_spi_enable_transfer()
558 if (mdata->dev_comp->ipm_design) { in mtk_spi_get_mult_delta()
574 if (mdata->tx_sgl_len && mdata->rx_sgl_len) { in mtk_spi_update_mdata_len()
575 if (mdata->tx_sgl_len > mdata->rx_sgl_len) { in mtk_spi_update_mdata_len()
576 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len); in mtk_spi_update_mdata_len()
577 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
578 mdata->rx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
579 mdata->tx_sgl_len -= mdata->xfer_len; in mtk_spi_update_mdata_len()
581 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len); in mtk_spi_update_mdata_len()
582 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
583 mdata->tx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
584 mdata->rx_sgl_len -= mdata->xfer_len; in mtk_spi_update_mdata_len()
586 } else if (mdata->tx_sgl_len) { in mtk_spi_update_mdata_len()
587 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len); in mtk_spi_update_mdata_len()
588 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
589 mdata->tx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
590 } else if (mdata->rx_sgl_len) { in mtk_spi_update_mdata_len()
591 mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len); in mtk_spi_update_mdata_len()
592 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
593 mdata->rx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
602 if (mdata->tx_sgl) { in mtk_spi_setup_dma_addr()
603 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), in mtk_spi_setup_dma_addr()
604 mdata->base + SPI_TX_SRC_REG); in mtk_spi_setup_dma_addr()
606 if (mdata->dev_comp->dma_ext) in mtk_spi_setup_dma_addr()
607 writel((u32)(xfer->tx_dma >> 32), in mtk_spi_setup_dma_addr()
608 mdata->base + SPI_TX_SRC_REG_64); in mtk_spi_setup_dma_addr()
612 if (mdata->rx_sgl) { in mtk_spi_setup_dma_addr()
613 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), in mtk_spi_setup_dma_addr()
614 mdata->base + SPI_RX_DST_REG); in mtk_spi_setup_dma_addr()
616 if (mdata->dev_comp->dma_ext) in mtk_spi_setup_dma_addr()
617 writel((u32)(xfer->rx_dma >> 32), in mtk_spi_setup_dma_addr()
618 mdata->base + SPI_RX_DST_REG_64); in mtk_spi_setup_dma_addr()
631 mdata->cur_transfer = xfer; in mtk_spi_fifo_transfer()
632 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); in mtk_spi_fifo_transfer()
633 mdata->num_xfered = 0; in mtk_spi_fifo_transfer()
634 mtk_spi_prepare_transfer(master, xfer->speed_hz); in mtk_spi_fifo_transfer()
637 if (xfer->tx_buf) { in mtk_spi_fifo_transfer()
638 cnt = xfer->len / 4; in mtk_spi_fifo_transfer()
639 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); in mtk_spi_fifo_transfer()
640 remainder = xfer->len % 4; in mtk_spi_fifo_transfer()
643 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); in mtk_spi_fifo_transfer()
644 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_fifo_transfer()
660 mdata->tx_sgl = NULL; in mtk_spi_dma_transfer()
661 mdata->rx_sgl = NULL; in mtk_spi_dma_transfer()
662 mdata->tx_sgl_len = 0; in mtk_spi_dma_transfer()
663 mdata->rx_sgl_len = 0; in mtk_spi_dma_transfer()
664 mdata->cur_transfer = xfer; in mtk_spi_dma_transfer()
665 mdata->num_xfered = 0; in mtk_spi_dma_transfer()
667 mtk_spi_prepare_transfer(master, xfer->speed_hz); in mtk_spi_dma_transfer()
669 cmd = readl(mdata->base + SPI_CMD_REG); in mtk_spi_dma_transfer()
670 if (xfer->tx_buf) in mtk_spi_dma_transfer()
672 if (xfer->rx_buf) in mtk_spi_dma_transfer()
674 writel(cmd, mdata->base + SPI_CMD_REG); in mtk_spi_dma_transfer()
676 if (xfer->tx_buf) in mtk_spi_dma_transfer()
677 mdata->tx_sgl = xfer->tx_sg.sgl; in mtk_spi_dma_transfer()
678 if (xfer->rx_buf) in mtk_spi_dma_transfer()
679 mdata->rx_sgl = xfer->rx_sg.sgl; in mtk_spi_dma_transfer()
681 if (mdata->tx_sgl) { in mtk_spi_dma_transfer()
682 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); in mtk_spi_dma_transfer()
683 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); in mtk_spi_dma_transfer()
685 if (mdata->rx_sgl) { in mtk_spi_dma_transfer()
686 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); in mtk_spi_dma_transfer()
687 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); in mtk_spi_dma_transfer()
702 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); in mtk_spi_transfer_one()
706 if (mdata->dev_comp->ipm_design) { in mtk_spi_transfer_one()
707 if (!xfer->tx_buf || !xfer->rx_buf) { in mtk_spi_transfer_one()
709 if (xfer->rx_buf) in mtk_spi_transfer_one()
712 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_transfer_one()
715 if (master->can_dma(master, spi, xfer)) in mtk_spi_transfer_one()
725 /* Buffers for DMA transactions must be 4-byte aligned */ in mtk_spi_can_dma()
726 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && in mtk_spi_can_dma()
727 (unsigned long)xfer->tx_buf % 4 == 0 && in mtk_spi_can_dma()
728 (unsigned long)xfer->rx_buf % 4 == 0); in mtk_spi_can_dma()
733 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); in mtk_spi_setup()
735 if (!spi->controller_data) in mtk_spi_setup()
736 spi->controller_data = (void *)&mtk_default_chip_info; in mtk_spi_setup()
738 if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) in mtk_spi_setup()
739 /* CS de-asserted, gpiolib will handle inversion */ in mtk_spi_setup()
740 gpiod_direction_output(spi->cs_gpiod, 0); in mtk_spi_setup()
750 struct spi_transfer *trans = mdata->cur_transfer; in mtk_spi_interrupt()
752 reg_val = readl(mdata->base + SPI_STATUS0_REG); in mtk_spi_interrupt()
754 mdata->state = MTK_SPI_PAUSED; in mtk_spi_interrupt()
756 mdata->state = MTK_SPI_IDLE; in mtk_spi_interrupt()
758 /* SPI-MEM ops */ in mtk_spi_interrupt()
759 if (mdata->use_spimem) { in mtk_spi_interrupt()
760 complete(&mdata->spimem_done); in mtk_spi_interrupt()
764 if (!master->can_dma(master, NULL, trans)) { in mtk_spi_interrupt()
765 if (trans->rx_buf) { in mtk_spi_interrupt()
766 cnt = mdata->xfer_len / 4; in mtk_spi_interrupt()
767 ioread32_rep(mdata->base + SPI_RX_DATA_REG, in mtk_spi_interrupt()
768 trans->rx_buf + mdata->num_xfered, cnt); in mtk_spi_interrupt()
769 remainder = mdata->xfer_len % 4; in mtk_spi_interrupt()
771 reg_val = readl(mdata->base + SPI_RX_DATA_REG); in mtk_spi_interrupt()
772 memcpy(trans->rx_buf + in mtk_spi_interrupt()
773 mdata->num_xfered + in mtk_spi_interrupt()
780 mdata->num_xfered += mdata->xfer_len; in mtk_spi_interrupt()
781 if (mdata->num_xfered == trans->len) { in mtk_spi_interrupt()
786 len = trans->len - mdata->num_xfered; in mtk_spi_interrupt()
787 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); in mtk_spi_interrupt()
790 cnt = mdata->xfer_len / 4; in mtk_spi_interrupt()
791 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, in mtk_spi_interrupt()
792 trans->tx_buf + mdata->num_xfered, cnt); in mtk_spi_interrupt()
794 remainder = mdata->xfer_len % 4; in mtk_spi_interrupt()
798 trans->tx_buf + (cnt * 4) + mdata->num_xfered, in mtk_spi_interrupt()
800 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_interrupt()
808 if (mdata->tx_sgl) in mtk_spi_interrupt()
809 trans->tx_dma += mdata->xfer_len; in mtk_spi_interrupt()
810 if (mdata->rx_sgl) in mtk_spi_interrupt()
811 trans->rx_dma += mdata->xfer_len; in mtk_spi_interrupt()
813 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { in mtk_spi_interrupt()
814 mdata->tx_sgl = sg_next(mdata->tx_sgl); in mtk_spi_interrupt()
815 if (mdata->tx_sgl) { in mtk_spi_interrupt()
816 trans->tx_dma = sg_dma_address(mdata->tx_sgl); in mtk_spi_interrupt()
817 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); in mtk_spi_interrupt()
820 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { in mtk_spi_interrupt()
821 mdata->rx_sgl = sg_next(mdata->rx_sgl); in mtk_spi_interrupt()
822 if (mdata->rx_sgl) { in mtk_spi_interrupt()
823 trans->rx_dma = sg_dma_address(mdata->rx_sgl); in mtk_spi_interrupt()
824 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); in mtk_spi_interrupt()
828 if (!mdata->tx_sgl && !mdata->rx_sgl) { in mtk_spi_interrupt()
830 cmd = readl(mdata->base + SPI_CMD_REG); in mtk_spi_interrupt()
833 writel(cmd, mdata->base + SPI_CMD_REG); in mtk_spi_interrupt()
852 if (op->data.dir != SPI_MEM_NO_DATA) { in mtk_spi_mem_adjust_op_size()
853 opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes; in mtk_spi_mem_adjust_op_size()
854 if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { in mtk_spi_mem_adjust_op_size()
855 op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len; in mtk_spi_mem_adjust_op_size()
856 /* force data buffer dma-aligned. */ in mtk_spi_mem_adjust_op_size()
857 op->data.nbytes -= op->data.nbytes % 4; in mtk_spi_mem_adjust_op_size()
870 if (op->addr.nbytes && op->dummy.nbytes && in mtk_spi_mem_supports_op()
871 op->addr.buswidth != op->dummy.buswidth) in mtk_spi_mem_supports_op()
874 if (op->addr.nbytes + op->dummy.nbytes > 16) in mtk_spi_mem_supports_op()
877 if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) { in mtk_spi_mem_supports_op()
878 if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE > in mtk_spi_mem_supports_op()
880 op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0) in mtk_spi_mem_supports_op()
892 writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK), in mtk_spi_mem_setup_dma_xfer()
893 mdata->base + SPI_TX_SRC_REG); in mtk_spi_mem_setup_dma_xfer()
895 if (mdata->dev_comp->dma_ext) in mtk_spi_mem_setup_dma_xfer()
896 writel((u32)(mdata->tx_dma >> 32), in mtk_spi_mem_setup_dma_xfer()
897 mdata->base + SPI_TX_SRC_REG_64); in mtk_spi_mem_setup_dma_xfer()
900 if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_spi_mem_setup_dma_xfer()
901 writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK), in mtk_spi_mem_setup_dma_xfer()
902 mdata->base + SPI_RX_DST_REG); in mtk_spi_mem_setup_dma_xfer()
904 if (mdata->dev_comp->dma_ext) in mtk_spi_mem_setup_dma_xfer()
905 writel((u32)(mdata->rx_dma >> 32), in mtk_spi_mem_setup_dma_xfer()
906 mdata->base + SPI_RX_DST_REG_64); in mtk_spi_mem_setup_dma_xfer()
914 struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); in mtk_spi_transfer_wait()
920 u64 ms = 8000LL; in mtk_spi_transfer_wait() local
922 if (op->data.dir == SPI_MEM_NO_DATA) in mtk_spi_transfer_wait()
923 ms *= 32; /* prevent we may get 0 for short transfers. */ in mtk_spi_transfer_wait()
925 ms *= op->data.nbytes; in mtk_spi_transfer_wait()
926 ms = div_u64(ms, mem->spi->max_speed_hz); in mtk_spi_transfer_wait()
927 ms += ms + 1000; /* 1s tolerance */ in mtk_spi_transfer_wait()
929 if (ms > UINT_MAX) in mtk_spi_transfer_wait()
930 ms = UINT_MAX; in mtk_spi_transfer_wait()
932 if (!wait_for_completion_timeout(&mdata->spimem_done, in mtk_spi_transfer_wait()
933 msecs_to_jiffies(ms))) { in mtk_spi_transfer_wait()
934 dev_err(mdata->dev, "spi-mem transfer timeout\n"); in mtk_spi_transfer_wait()
935 return -ETIMEDOUT; in mtk_spi_transfer_wait()
944 struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master); in mtk_spi_mem_exec_op()
949 mdata->use_spimem = true; in mtk_spi_mem_exec_op()
950 reinit_completion(&mdata->spimem_done); in mtk_spi_mem_exec_op()
953 mtk_spi_hw_init(mem->spi->master, mem->spi); in mtk_spi_mem_exec_op()
954 mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz); in mtk_spi_mem_exec_op()
956 reg_val = readl(mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_mem_exec_op()
963 if (op->addr.nbytes || op->dummy.nbytes) in mtk_spi_mem_exec_op()
964 reg_val |= (op->addr.nbytes + op->dummy.nbytes) << in mtk_spi_mem_exec_op()
968 if (op->data.dir == SPI_MEM_NO_DATA) { in mtk_spi_mem_exec_op()
970 writel(0, mdata->base + SPI_CFG1_REG); in mtk_spi_mem_exec_op()
973 mdata->xfer_len = op->data.nbytes; in mtk_spi_mem_exec_op()
974 mtk_spi_setup_packet(mem->spi->master); in mtk_spi_mem_exec_op()
977 if (op->addr.nbytes || op->dummy.nbytes) { in mtk_spi_mem_exec_op()
978 if (op->addr.buswidth == 1 || op->dummy.buswidth == 1) in mtk_spi_mem_exec_op()
984 if (op->addr.buswidth == 2 || in mtk_spi_mem_exec_op()
985 op->dummy.buswidth == 2 || in mtk_spi_mem_exec_op()
986 op->data.buswidth == 2) in mtk_spi_mem_exec_op()
988 else if (op->addr.buswidth == 4 || in mtk_spi_mem_exec_op()
989 op->dummy.buswidth == 4 || in mtk_spi_mem_exec_op()
990 op->data.buswidth == 4) in mtk_spi_mem_exec_op()
999 if (op->data.dir == SPI_MEM_DATA_IN) in mtk_spi_mem_exec_op()
1003 writel(reg_val, mdata->base + SPI_CFG3_IPM_REG); in mtk_spi_mem_exec_op()
1005 tx_size = 1 + op->addr.nbytes + op->dummy.nbytes; in mtk_spi_mem_exec_op()
1006 if (op->data.dir == SPI_MEM_DATA_OUT) in mtk_spi_mem_exec_op()
1007 tx_size += op->data.nbytes; in mtk_spi_mem_exec_op()
1013 mdata->use_spimem = false; in mtk_spi_mem_exec_op()
1014 return -ENOMEM; in mtk_spi_mem_exec_op()
1017 tx_tmp_buf[0] = op->cmd.opcode; in mtk_spi_mem_exec_op()
1019 if (op->addr.nbytes) { in mtk_spi_mem_exec_op()
1022 for (i = 0; i < op->addr.nbytes; i++) in mtk_spi_mem_exec_op()
1023 tx_tmp_buf[i + 1] = op->addr.val >> in mtk_spi_mem_exec_op()
1024 (8 * (op->addr.nbytes - i - 1)); in mtk_spi_mem_exec_op()
1027 if (op->dummy.nbytes) in mtk_spi_mem_exec_op()
1028 memset(tx_tmp_buf + op->addr.nbytes + 1, in mtk_spi_mem_exec_op()
1030 op->dummy.nbytes); in mtk_spi_mem_exec_op()
1032 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) in mtk_spi_mem_exec_op()
1033 memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1, in mtk_spi_mem_exec_op()
1034 op->data.buf.out, in mtk_spi_mem_exec_op()
1035 op->data.nbytes); in mtk_spi_mem_exec_op()
1037 mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf, in mtk_spi_mem_exec_op()
1039 if (dma_mapping_error(mdata->dev, mdata->tx_dma)) { in mtk_spi_mem_exec_op()
1040 ret = -ENOMEM; in mtk_spi_mem_exec_op()
1044 if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_spi_mem_exec_op()
1045 if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) { in mtk_spi_mem_exec_op()
1046 rx_tmp_buf = kzalloc(op->data.nbytes, in mtk_spi_mem_exec_op()
1049 ret = -ENOMEM; in mtk_spi_mem_exec_op()
1053 rx_tmp_buf = op->data.buf.in; in mtk_spi_mem_exec_op()
1056 mdata->rx_dma = dma_map_single(mdata->dev, in mtk_spi_mem_exec_op()
1058 op->data.nbytes, in mtk_spi_mem_exec_op()
1060 if (dma_mapping_error(mdata->dev, mdata->rx_dma)) { in mtk_spi_mem_exec_op()
1061 ret = -ENOMEM; in mtk_spi_mem_exec_op()
1066 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1068 if (op->data.dir == SPI_MEM_DATA_IN) in mtk_spi_mem_exec_op()
1070 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1072 mtk_spi_mem_setup_dma_xfer(mem->spi->master, op); in mtk_spi_mem_exec_op()
1074 mtk_spi_enable_transfer(mem->spi->master); in mtk_spi_mem_exec_op()
1082 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1084 if (op->data.dir == SPI_MEM_DATA_IN) in mtk_spi_mem_exec_op()
1086 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_mem_exec_op()
1089 if (op->data.dir == SPI_MEM_DATA_IN) { in mtk_spi_mem_exec_op()
1090 dma_unmap_single(mdata->dev, mdata->rx_dma, in mtk_spi_mem_exec_op()
1091 op->data.nbytes, DMA_FROM_DEVICE); in mtk_spi_mem_exec_op()
1092 if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) in mtk_spi_mem_exec_op()
1093 memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes); in mtk_spi_mem_exec_op()
1096 if (op->data.dir == SPI_MEM_DATA_IN && in mtk_spi_mem_exec_op()
1097 !IS_ALIGNED((size_t)op->data.buf.in, 4)) in mtk_spi_mem_exec_op()
1100 dma_unmap_single(mdata->dev, mdata->tx_dma, in mtk_spi_mem_exec_op()
1104 mdata->use_spimem = false; in mtk_spi_mem_exec_op()
1117 struct device *dev = &pdev->dev; in mtk_spi_probe()
1124 return dev_err_probe(dev, -ENOMEM, "failed to alloc spi master\n"); in mtk_spi_probe()
1126 master->auto_runtime_pm = true; in mtk_spi_probe()
1127 master->dev.of_node = dev->of_node; in mtk_spi_probe()
1128 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; in mtk_spi_probe()
1130 master->set_cs = mtk_spi_set_cs; in mtk_spi_probe()
1131 master->prepare_message = mtk_spi_prepare_message; in mtk_spi_probe()
1132 master->transfer_one = mtk_spi_transfer_one; in mtk_spi_probe()
1133 master->can_dma = mtk_spi_can_dma; in mtk_spi_probe()
1134 master->setup = mtk_spi_setup; in mtk_spi_probe()
1135 master->set_cs_timing = mtk_spi_set_hw_cs_timing; in mtk_spi_probe()
1136 master->use_gpio_descriptors = true; in mtk_spi_probe()
1139 mdata->dev_comp = device_get_match_data(dev); in mtk_spi_probe()
1141 if (mdata->dev_comp->enhance_timing) in mtk_spi_probe()
1142 master->mode_bits |= SPI_CS_HIGH; in mtk_spi_probe()
1144 if (mdata->dev_comp->must_tx) in mtk_spi_probe()
1145 master->flags = SPI_MASTER_MUST_TX; in mtk_spi_probe()
1146 if (mdata->dev_comp->ipm_design) in mtk_spi_probe()
1147 master->mode_bits |= SPI_LOOP; in mtk_spi_probe()
1149 if (mdata->dev_comp->ipm_design) { in mtk_spi_probe()
1150 mdata->dev = dev; in mtk_spi_probe()
1151 master->mem_ops = &mtk_spi_mem_ops; in mtk_spi_probe()
1152 init_completion(&mdata->spimem_done); in mtk_spi_probe()
1155 if (mdata->dev_comp->need_pad_sel) { in mtk_spi_probe()
1156 mdata->pad_num = of_property_count_u32_elems(dev->of_node, in mtk_spi_probe()
1157 "mediatek,pad-select"); in mtk_spi_probe()
1158 if (mdata->pad_num < 0) in mtk_spi_probe()
1159 return dev_err_probe(dev, -EINVAL, in mtk_spi_probe()
1160 "No 'mediatek,pad-select' property\n"); in mtk_spi_probe()
1162 mdata->pad_sel = devm_kmalloc_array(dev, mdata->pad_num, in mtk_spi_probe()
1164 if (!mdata->pad_sel) in mtk_spi_probe()
1165 return -ENOMEM; in mtk_spi_probe()
1167 for (i = 0; i < mdata->pad_num; i++) { in mtk_spi_probe()
1168 of_property_read_u32_index(dev->of_node, in mtk_spi_probe()
1169 "mediatek,pad-select", in mtk_spi_probe()
1170 i, &mdata->pad_sel[i]); in mtk_spi_probe()
1171 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) in mtk_spi_probe()
1172 return dev_err_probe(dev, -EINVAL, in mtk_spi_probe()
1173 "wrong pad-sel[%d]: %u\n", in mtk_spi_probe()
1174 i, mdata->pad_sel[i]); in mtk_spi_probe()
1179 mdata->base = devm_platform_ioremap_resource(pdev, 0); in mtk_spi_probe()
1180 if (IS_ERR(mdata->base)) in mtk_spi_probe()
1181 return PTR_ERR(mdata->base); in mtk_spi_probe()
1187 if (!dev->dma_mask) in mtk_spi_probe()
1188 dev->dma_mask = &dev->coherent_dma_mask; in mtk_spi_probe()
1190 if (mdata->dev_comp->ipm_design) in mtk_spi_probe()
1200 mdata->parent_clk = devm_clk_get(dev, "parent-clk"); in mtk_spi_probe()
1201 if (IS_ERR(mdata->parent_clk)) in mtk_spi_probe()
1202 return dev_err_probe(dev, PTR_ERR(mdata->parent_clk), in mtk_spi_probe()
1203 "failed to get parent-clk\n"); in mtk_spi_probe()
1205 mdata->sel_clk = devm_clk_get(dev, "sel-clk"); in mtk_spi_probe()
1206 if (IS_ERR(mdata->sel_clk)) in mtk_spi_probe()
1207 return dev_err_probe(dev, PTR_ERR(mdata->sel_clk), "failed to get sel-clk\n"); in mtk_spi_probe()
1209 mdata->spi_clk = devm_clk_get(dev, "spi-clk"); in mtk_spi_probe()
1210 if (IS_ERR(mdata->spi_clk)) in mtk_spi_probe()
1211 return dev_err_probe(dev, PTR_ERR(mdata->spi_clk), "failed to get spi-clk\n"); in mtk_spi_probe()
1213 mdata->spi_hclk = devm_clk_get_optional(dev, "hclk"); in mtk_spi_probe()
1214 if (IS_ERR(mdata->spi_hclk)) in mtk_spi_probe()
1215 return dev_err_probe(dev, PTR_ERR(mdata->spi_hclk), "failed to get hclk\n"); in mtk_spi_probe()
1217 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); in mtk_spi_probe()
1221 ret = clk_prepare_enable(mdata->spi_hclk); in mtk_spi_probe()
1225 ret = clk_prepare_enable(mdata->spi_clk); in mtk_spi_probe()
1227 clk_disable_unprepare(mdata->spi_hclk); in mtk_spi_probe()
1231 mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk); in mtk_spi_probe()
1233 if (mdata->dev_comp->no_need_unprepare) { in mtk_spi_probe()
1234 clk_disable(mdata->spi_clk); in mtk_spi_probe()
1235 clk_disable(mdata->spi_hclk); in mtk_spi_probe()
1237 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_probe()
1238 clk_disable_unprepare(mdata->spi_hclk); in mtk_spi_probe()
1241 if (mdata->dev_comp->need_pad_sel) { in mtk_spi_probe()
1242 if (mdata->pad_num != master->num_chipselect) in mtk_spi_probe()
1243 return dev_err_probe(dev, -EINVAL, in mtk_spi_probe()
1245 mdata->pad_num, master->num_chipselect); in mtk_spi_probe()
1247 if (!master->cs_gpiods && master->num_chipselect > 1) in mtk_spi_probe()
1248 return dev_err_probe(dev, -EINVAL, in mtk_spi_probe()
1252 if (mdata->dev_comp->dma_ext) in mtk_spi_probe()
1278 ret = pm_runtime_resume_and_get(&pdev->dev); in mtk_spi_remove()
1284 if (mdata->dev_comp->no_need_unprepare) { in mtk_spi_remove()
1285 clk_unprepare(mdata->spi_clk); in mtk_spi_remove()
1286 clk_unprepare(mdata->spi_hclk); in mtk_spi_remove()
1289 pm_runtime_put_noidle(&pdev->dev); in mtk_spi_remove()
1290 pm_runtime_disable(&pdev->dev); in mtk_spi_remove()
1307 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_suspend()
1308 clk_disable_unprepare(mdata->spi_hclk); in mtk_spi_suspend()
1321 ret = clk_prepare_enable(mdata->spi_clk); in mtk_spi_resume()
1327 ret = clk_prepare_enable(mdata->spi_hclk); in mtk_spi_resume()
1330 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_resume()
1337 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_resume()
1338 clk_disable_unprepare(mdata->spi_hclk); in mtk_spi_resume()
1351 if (mdata->dev_comp->no_need_unprepare) { in mtk_spi_runtime_suspend()
1352 clk_disable(mdata->spi_clk); in mtk_spi_runtime_suspend()
1353 clk_disable(mdata->spi_hclk); in mtk_spi_runtime_suspend()
1355 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_runtime_suspend()
1356 clk_disable_unprepare(mdata->spi_hclk); in mtk_spi_runtime_suspend()
1368 if (mdata->dev_comp->no_need_unprepare) { in mtk_spi_runtime_resume()
1369 ret = clk_enable(mdata->spi_clk); in mtk_spi_runtime_resume()
1374 ret = clk_enable(mdata->spi_hclk); in mtk_spi_runtime_resume()
1377 clk_disable(mdata->spi_clk); in mtk_spi_runtime_resume()
1381 ret = clk_prepare_enable(mdata->spi_clk); in mtk_spi_runtime_resume()
1387 ret = clk_prepare_enable(mdata->spi_hclk); in mtk_spi_runtime_resume()
1390 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_runtime_resume()
1407 .name = "mtk-spi",
1420 MODULE_ALIAS("platform:mtk-spi");