Lines Matching +full:mpfs +full:- +full:clock
1 // SPDX-License-Identifier: (GPL-2.0)
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
104 u32 clk_gen; /* divider for spi output clock generated by the controller */
114 return readl(spi->regs + reg); in mchp_corespi_read()
119 writel(val, spi->regs + reg); in mchp_corespi_write()
145 fifo_max = min(spi->rx_len, FIFO_DEPTH); in mchp_corespi_read_fifo()
150 if (spi->rx_buf) in mchp_corespi_read_fifo()
151 *spi->rx_buf++ = data; in mchp_corespi_read_fifo()
154 spi->rx_len -= i; in mchp_corespi_read_fifo()
155 spi->pending -= i; in mchp_corespi_read_fifo()
223 fifo_max = min(spi->tx_len, FIFO_DEPTH); in mchp_corespi_write_fifo()
227 byte = spi->tx_buf ? *spi->tx_buf++ : 0xaa; in mchp_corespi_write_fifo()
232 spi->tx_len -= i; in mchp_corespi_write_fifo()
233 spi->pending += i; in mchp_corespi_write_fifo()
256 struct mchp_corespi *corespi = spi_master_get_devdata(spi->master); in mchp_corespi_set_cs()
259 reg &= ~BIT(spi->chip_select); in mchp_corespi_set_cs()
260 reg |= !disable << spi->chip_select; in mchp_corespi_set_cs()
267 struct mchp_corespi *corespi = spi_master_get_devdata(spi->master); in mchp_corespi_setup()
275 if (spi->mode & SPI_CS_HIGH) { in mchp_corespi_setup()
277 reg |= BIT(spi->chip_select); in mchp_corespi_setup()
295 /* max. possible spi clock rate is the apb clock rate */ in mchp_corespi_init()
296 clk_hz = clk_get_rate(spi->clk); in mchp_corespi_init()
297 master->max_speed_hz = clk_hz; in mchp_corespi_init()
336 if (spi->clk_mode) in mchp_corespi_set_clk_gen()
341 mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen); in mchp_corespi_set_clk_gen()
395 if (spi->rx_len) in mchp_corespi_interrupt()
398 if (spi->tx_len) in mchp_corespi_interrupt()
401 if (!spi->rx_len) in mchp_corespi_interrupt()
411 dev_err(&master->dev, in mchp_corespi_interrupt()
413 spi->rx_len, spi->tx_len); in mchp_corespi_interrupt()
419 dev_err(&master->dev, in mchp_corespi_interrupt()
421 spi->rx_len, spi->tx_len); in mchp_corespi_interrupt()
435 clk_hz = clk_get_rate(spi->clk); in mchp_corespi_calculate_clkgen()
437 return -EINVAL; in mchp_corespi_calculate_clkgen()
441 * There are two possible clock modes for the controller generated in mchp_corespi_calculate_clkgen()
442 * clock's division ratio: in mchp_corespi_calculate_clkgen()
448 * clk_gen is the register name for the clock divider on MPFS. in mchp_corespi_calculate_clkgen()
450 clk_gen = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1; in mchp_corespi_calculate_clkgen()
453 clk_gen = fls(clk_gen) - 1; in mchp_corespi_calculate_clkgen()
456 return -EINVAL; in mchp_corespi_calculate_clkgen()
458 spi->clk_mode = 0; in mchp_corespi_calculate_clkgen()
460 spi->clk_mode = 1; in mchp_corespi_calculate_clkgen()
463 spi->clk_gen = clk_gen; in mchp_corespi_calculate_clkgen()
474 ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz); in mchp_corespi_transfer_one()
476 dev_err(&master->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz); in mchp_corespi_transfer_one()
482 spi->tx_buf = xfer->tx_buf; in mchp_corespi_transfer_one()
483 spi->rx_buf = xfer->rx_buf; in mchp_corespi_transfer_one()
484 spi->tx_len = xfer->len; in mchp_corespi_transfer_one()
485 spi->rx_len = xfer->len; in mchp_corespi_transfer_one()
486 spi->pending = 0; in mchp_corespi_transfer_one()
488 mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH) in mchp_corespi_transfer_one()
489 ? FIFO_DEPTH : spi->tx_len); in mchp_corespi_transfer_one()
491 if (spi->tx_len) in mchp_corespi_transfer_one()
499 struct spi_device *spi_dev = msg->spi; in mchp_corespi_prepare_message()
503 mchp_corespi_set_mode(spi, spi_dev->mode); in mchp_corespi_prepare_message()
516 master = devm_spi_alloc_master(&pdev->dev, sizeof(*spi)); in mchp_corespi_probe()
518 return dev_err_probe(&pdev->dev, -ENOMEM, in mchp_corespi_probe()
523 if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) in mchp_corespi_probe()
526 master->num_chipselect = num_cs; in mchp_corespi_probe()
527 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in mchp_corespi_probe()
528 master->setup = mchp_corespi_setup; in mchp_corespi_probe()
529 master->bits_per_word_mask = SPI_BPW_MASK(8); in mchp_corespi_probe()
530 master->transfer_one = mchp_corespi_transfer_one; in mchp_corespi_probe()
531 master->prepare_message = mchp_corespi_prepare_message; in mchp_corespi_probe()
532 master->set_cs = mchp_corespi_set_cs; in mchp_corespi_probe()
533 master->dev.of_node = pdev->dev.of_node; in mchp_corespi_probe()
537 spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in mchp_corespi_probe()
538 if (IS_ERR(spi->regs)) in mchp_corespi_probe()
539 return PTR_ERR(spi->regs); in mchp_corespi_probe()
541 spi->irq = platform_get_irq(pdev, 0); in mchp_corespi_probe()
542 if (spi->irq <= 0) in mchp_corespi_probe()
543 return dev_err_probe(&pdev->dev, -ENXIO, in mchp_corespi_probe()
545 spi->irq); in mchp_corespi_probe()
547 ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt, in mchp_corespi_probe()
548 IRQF_SHARED, dev_name(&pdev->dev), master); in mchp_corespi_probe()
550 return dev_err_probe(&pdev->dev, ret, in mchp_corespi_probe()
553 spi->clk = devm_clk_get(&pdev->dev, NULL); in mchp_corespi_probe()
554 if (IS_ERR(spi->clk)) in mchp_corespi_probe()
555 return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk), in mchp_corespi_probe()
558 ret = clk_prepare_enable(spi->clk); in mchp_corespi_probe()
560 return dev_err_probe(&pdev->dev, ret, in mchp_corespi_probe()
561 "failed to enable clock\n"); in mchp_corespi_probe()
565 ret = devm_spi_register_master(&pdev->dev, master); in mchp_corespi_probe()
568 clk_disable_unprepare(spi->clk); in mchp_corespi_probe()
569 return dev_err_probe(&pdev->dev, ret, in mchp_corespi_probe()
573 dev_info(&pdev->dev, "Registered SPI controller %d\n", master->bus_num); in mchp_corespi_probe()
584 clk_disable_unprepare(spi->clk); in mchp_corespi_remove()
598 { .compatible = "microchip,mpfs-spi" },
607 .name = "microchip-corespi",