Lines Matching +full:rx +full:- +full:tx +full:- +full:swap
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
68 #define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
70 #define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */
71 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
73 #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
74 #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
88 #define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */
89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */
90 #define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */
91 #define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */
92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */
93 #define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */
94 #define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */
101 #define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */
102 #define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */
104 #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */
105 #define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */
106 #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */
107 #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */
108 #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */
124 #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */
125 #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */
179 if (!spicc->data->has_oen) in meson_spicc_oen_enable()
182 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | in meson_spicc_oen_enable()
185 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); in meson_spicc_oen_enable()
191 readl_relaxed(spicc->base + SPICC_STATREG)); in meson_spicc_txfull()
197 readl_relaxed(spicc->base + SPICC_STATREG)); in meson_spicc_rxready()
202 unsigned int bytes = spicc->bytes_per_word; in meson_spicc_pull_data()
207 while (bytes--) { in meson_spicc_pull_data()
208 byte = *spicc->tx_buf++; in meson_spicc_pull_data()
213 spicc->tx_remain--; in meson_spicc_pull_data()
220 unsigned int bytes = spicc->bytes_per_word; in meson_spicc_push_data()
224 while (bytes--) { in meson_spicc_push_data()
226 *spicc->rx_buf++ = byte; in meson_spicc_push_data()
230 spicc->rx_remain--; in meson_spicc_push_data()
235 /* Empty RX FIFO */ in meson_spicc_rx()
236 while (spicc->rx_remain && in meson_spicc_rx()
239 readl_relaxed(spicc->base + SPICC_RXDATA)); in meson_spicc_rx()
244 /* Fill Up TX FIFO */ in meson_spicc_tx()
245 while (spicc->tx_remain && in meson_spicc_tx()
248 spicc->base + SPICC_TXDATA); in meson_spicc_tx()
255 spicc->xfer_remain / in meson_spicc_setup_burst()
256 spicc->bytes_per_word, in meson_spicc_setup_burst()
257 spicc->data->fifo_size); in meson_spicc_setup_burst()
259 spicc->tx_remain = burst_len; in meson_spicc_setup_burst()
260 spicc->rx_remain = burst_len; in meson_spicc_setup_burst()
261 spicc->xfer_remain -= burst_len * spicc->bytes_per_word; in meson_spicc_setup_burst()
266 burst_len - 1), in meson_spicc_setup_burst()
267 spicc->base + SPICC_CONREG); in meson_spicc_setup_burst()
269 /* Fill TX FIFO */ in meson_spicc_setup_burst()
277 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); in meson_spicc_irq()
279 /* Empty RX FIFO */ in meson_spicc_irq()
282 if (!spicc->xfer_remain) { in meson_spicc_irq()
284 writel(0, spicc->base + SPICC_INTREG); in meson_spicc_irq()
286 complete(&spicc->done); in meson_spicc_irq()
295 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_irq()
306 if (spicc->data->has_enhance_clk_div) { in meson_spicc_auto_io_delay()
308 readl_relaxed(spicc->base + SPICC_ENH_CTL0)); in meson_spicc_auto_io_delay()
313 readl_relaxed(spicc->base + SPICC_CONREG)); in meson_spicc_auto_io_delay()
320 hz = clk_get_rate(spicc->clk); in meson_spicc_auto_io_delay()
335 conf = readl_relaxed(spicc->base + SPICC_TESTREG); in meson_spicc_auto_io_delay()
340 writel_relaxed(conf, spicc->base + SPICC_TESTREG); in meson_spicc_auto_io_delay()
349 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); in meson_spicc_setup_xfer()
354 (spicc->bytes_per_word << 3) - 1); in meson_spicc_setup_xfer()
358 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_setup_xfer()
360 clk_set_rate(spicc->clk, xfer->speed_hz); in meson_spicc_setup_xfer()
364 writel_relaxed(0, spicc->base + SPICC_DMAREG); in meson_spicc_setup_xfer()
369 if (spicc->data->has_oen) in meson_spicc_reset_fifo()
372 spicc->base + SPICC_ENH_CTL0); in meson_spicc_reset_fifo()
375 spicc->base + SPICC_TESTREG); in meson_spicc_reset_fifo()
378 readl_relaxed(spicc->base + SPICC_RXDATA); in meson_spicc_reset_fifo()
380 if (spicc->data->has_oen) in meson_spicc_reset_fifo()
382 spicc->base + SPICC_ENH_CTL0); in meson_spicc_reset_fifo()
393 spicc->xfer = xfer; in meson_spicc_transfer_one()
396 spicc->tx_buf = (u8 *)xfer->tx_buf; in meson_spicc_transfer_one()
397 spicc->rx_buf = (u8 *)xfer->rx_buf; in meson_spicc_transfer_one()
398 spicc->xfer_remain = xfer->len; in meson_spicc_transfer_one()
400 /* Pre-calculate word size */ in meson_spicc_transfer_one()
401 spicc->bytes_per_word = in meson_spicc_transfer_one()
402 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8); in meson_spicc_transfer_one()
404 if (xfer->len % spicc->bytes_per_word) in meson_spicc_transfer_one()
405 return -EINVAL; in meson_spicc_transfer_one()
416 reinit_completion(&spicc->done); in meson_spicc_transfer_one()
419 timeout = 8LL * MSEC_PER_SEC * xfer->len; in meson_spicc_transfer_one()
420 do_div(timeout, xfer->speed_hz); in meson_spicc_transfer_one()
423 timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC; in meson_spicc_transfer_one()
429 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_transfer_one()
432 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG); in meson_spicc_transfer_one()
434 if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout))) in meson_spicc_transfer_one()
435 return -ETIMEDOUT; in meson_spicc_transfer_one()
444 struct spi_device *spi = message->spi; in meson_spicc_prepare_message()
445 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; in meson_spicc_prepare_message()
448 spicc->message = message; in meson_spicc_prepare_message()
457 if (spi->mode & SPI_CPOL) in meson_spicc_prepare_message()
462 if (spi->mode & SPI_CPHA) in meson_spicc_prepare_message()
469 if (spi->mode & SPI_CS_HIGH) in meson_spicc_prepare_message()
474 if (spi->mode & SPI_READY) in meson_spicc_prepare_message()
480 conf |= FIELD_PREP(SPICC_CS_MASK, spi->chip_select); in meson_spicc_prepare_message()
483 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1); in meson_spicc_prepare_message()
485 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_prepare_message()
488 writel_relaxed(0, spicc->base + SPICC_PERIODREG); in meson_spicc_prepare_message()
490 writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG); in meson_spicc_prepare_message()
498 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK; in meson_spicc_unprepare_transfer()
501 writel(0, spicc->base + SPICC_INTREG); in meson_spicc_unprepare_transfer()
503 device_reset_optional(&spicc->pdev->dev); in meson_spicc_unprepare_transfer()
506 writel_relaxed(conf, spicc->base + SPICC_CONREG); in meson_spicc_unprepare_transfer()
513 if (!spi->controller_state) in meson_spicc_setup()
514 spi->controller_state = spi_master_get_devdata(spi->master); in meson_spicc_setup()
521 spi->controller_state = NULL; in meson_spicc_cleanup()
526 * x-----------------x x------------x x------\
527 * |---| pow2 fixed div |---| pow2 div |----| |
528 * | x-----------------x x------------x | |
529 * src ---| | mux |-- out
530 * | x-----------------x x------------x | |
531 * |---| enh fixed div |---| enh div |0---| |
532 * x-----------------x x------------x x------/
535 * src -> pow2 fixed div -> pow2 div -> out
538 * src -> pow2 fixed div -> pow2 div -> mux -> out
539 * src -> enh fixed div -> enh div -> mux -> out
542 * pclk -> pow2 fixed div -> pow2 div -> mux -> out
543 * pclk -> enh fixed div -> enh div -> mux -> out
558 if (!spicc->master->cur_msg) in meson_spicc_pow2_recalc_rate()
570 if (!spicc->master->cur_msg) in meson_spicc_pow2_determine_rate()
571 return -EINVAL; in meson_spicc_pow2_determine_rate()
582 if (!spicc->master->cur_msg) in meson_spicc_pow2_set_rate()
583 return -EINVAL; in meson_spicc_pow2_set_rate()
596 struct device *dev = &spicc->pdev->dev; in meson_spicc_pow2_clk_init()
612 return -ENOMEM; in meson_spicc_pow2_clk_init()
618 if (spicc->data->has_pclk) in meson_spicc_pow2_clk_init()
619 parent_data[0].hw = __clk_get_hw(spicc->pclk); in meson_spicc_pow2_clk_init()
621 parent_data[0].hw = __clk_get_hw(spicc->core); in meson_spicc_pow2_clk_init()
624 pow2_fixed_div->mult = 1, in meson_spicc_pow2_clk_init()
625 pow2_fixed_div->div = 4, in meson_spicc_pow2_clk_init()
626 pow2_fixed_div->hw.init = &init; in meson_spicc_pow2_clk_init()
628 clk = devm_clk_register(dev, &pow2_fixed_div->hw); in meson_spicc_pow2_clk_init()
640 parent_data[0].hw = &pow2_fixed_div->hw; in meson_spicc_pow2_clk_init()
643 spicc->pow2_div.shift = 16, in meson_spicc_pow2_clk_init()
644 spicc->pow2_div.width = 3, in meson_spicc_pow2_clk_init()
645 spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO, in meson_spicc_pow2_clk_init()
646 spicc->pow2_div.reg = spicc->base + SPICC_CONREG; in meson_spicc_pow2_clk_init()
647 spicc->pow2_div.hw.init = &init; in meson_spicc_pow2_clk_init()
649 spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw); in meson_spicc_pow2_clk_init()
650 if (WARN_ON(IS_ERR(spicc->clk))) in meson_spicc_pow2_clk_init()
651 return PTR_ERR(spicc->clk); in meson_spicc_pow2_clk_init()
658 struct device *dev = &spicc->pdev->dev; in meson_spicc_enh_clk_init()
676 return -ENOMEM; in meson_spicc_enh_clk_init()
682 if (spicc->data->has_pclk) in meson_spicc_enh_clk_init()
683 parent_data[0].hw = __clk_get_hw(spicc->pclk); in meson_spicc_enh_clk_init()
685 parent_data[0].hw = __clk_get_hw(spicc->core); in meson_spicc_enh_clk_init()
688 enh_fixed_div->mult = 1, in meson_spicc_enh_clk_init()
689 enh_fixed_div->div = 2, in meson_spicc_enh_clk_init()
690 enh_fixed_div->hw.init = &init; in meson_spicc_enh_clk_init()
692 clk = devm_clk_register(dev, &enh_fixed_div->hw); in meson_spicc_enh_clk_init()
698 return -ENOMEM; in meson_spicc_enh_clk_init()
704 parent_data[0].hw = &enh_fixed_div->hw; in meson_spicc_enh_clk_init()
707 enh_div->shift = 16, in meson_spicc_enh_clk_init()
708 enh_div->width = 8, in meson_spicc_enh_clk_init()
709 enh_div->reg = spicc->base + SPICC_ENH_CTL0; in meson_spicc_enh_clk_init()
710 enh_div->hw.init = &init; in meson_spicc_enh_clk_init()
712 clk = devm_clk_register(dev, &enh_div->hw); in meson_spicc_enh_clk_init()
718 return -ENOMEM; in meson_spicc_enh_clk_init()
723 parent_data[0].hw = &spicc->pow2_div.hw; in meson_spicc_enh_clk_init()
724 parent_data[1].hw = &enh_div->hw; in meson_spicc_enh_clk_init()
728 mux->mask = 0x1, in meson_spicc_enh_clk_init()
729 mux->shift = 24, in meson_spicc_enh_clk_init()
730 mux->reg = spicc->base + SPICC_ENH_CTL0; in meson_spicc_enh_clk_init()
731 mux->hw.init = &init; in meson_spicc_enh_clk_init()
733 spicc->clk = devm_clk_register(dev, &mux->hw); in meson_spicc_enh_clk_init()
734 if (WARN_ON(IS_ERR(spicc->clk))) in meson_spicc_enh_clk_init()
735 return PTR_ERR(spicc->clk); in meson_spicc_enh_clk_init()
746 master = spi_alloc_master(&pdev->dev, sizeof(*spicc)); in meson_spicc_probe()
748 dev_err(&pdev->dev, "master allocation failed\n"); in meson_spicc_probe()
749 return -ENOMEM; in meson_spicc_probe()
752 spicc->master = master; in meson_spicc_probe()
754 spicc->data = of_device_get_match_data(&pdev->dev); in meson_spicc_probe()
755 if (!spicc->data) { in meson_spicc_probe()
756 dev_err(&pdev->dev, "failed to get match data\n"); in meson_spicc_probe()
757 ret = -EINVAL; in meson_spicc_probe()
761 spicc->pdev = pdev; in meson_spicc_probe()
764 init_completion(&spicc->done); in meson_spicc_probe()
766 spicc->base = devm_platform_ioremap_resource(pdev, 0); in meson_spicc_probe()
767 if (IS_ERR(spicc->base)) { in meson_spicc_probe()
768 dev_err(&pdev->dev, "io resource mapping failed\n"); in meson_spicc_probe()
769 ret = PTR_ERR(spicc->base); in meson_spicc_probe()
775 spicc->base + SPICC_CONREG); in meson_spicc_probe()
778 writel_relaxed(0, spicc->base + SPICC_INTREG); in meson_spicc_probe()
786 ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq, in meson_spicc_probe()
789 dev_err(&pdev->dev, "irq request failed\n"); in meson_spicc_probe()
793 spicc->core = devm_clk_get(&pdev->dev, "core"); in meson_spicc_probe()
794 if (IS_ERR(spicc->core)) { in meson_spicc_probe()
795 dev_err(&pdev->dev, "core clock request failed\n"); in meson_spicc_probe()
796 ret = PTR_ERR(spicc->core); in meson_spicc_probe()
800 if (spicc->data->has_pclk) { in meson_spicc_probe()
801 spicc->pclk = devm_clk_get(&pdev->dev, "pclk"); in meson_spicc_probe()
802 if (IS_ERR(spicc->pclk)) { in meson_spicc_probe()
803 dev_err(&pdev->dev, "pclk clock request failed\n"); in meson_spicc_probe()
804 ret = PTR_ERR(spicc->pclk); in meson_spicc_probe()
809 ret = clk_prepare_enable(spicc->core); in meson_spicc_probe()
811 dev_err(&pdev->dev, "core clock enable failed\n"); in meson_spicc_probe()
815 ret = clk_prepare_enable(spicc->pclk); in meson_spicc_probe()
817 dev_err(&pdev->dev, "pclk clock enable failed\n"); in meson_spicc_probe()
821 device_reset_optional(&pdev->dev); in meson_spicc_probe()
823 master->num_chipselect = 4; in meson_spicc_probe()
824 master->dev.of_node = pdev->dev.of_node; in meson_spicc_probe()
825 master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH; in meson_spicc_probe()
826 master->bits_per_word_mask = SPI_BPW_MASK(32) | in meson_spicc_probe()
830 master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); in meson_spicc_probe()
831 master->min_speed_hz = spicc->data->min_speed_hz; in meson_spicc_probe()
832 master->max_speed_hz = spicc->data->max_speed_hz; in meson_spicc_probe()
833 master->setup = meson_spicc_setup; in meson_spicc_probe()
834 master->cleanup = meson_spicc_cleanup; in meson_spicc_probe()
835 master->prepare_message = meson_spicc_prepare_message; in meson_spicc_probe()
836 master->unprepare_transfer_hardware = meson_spicc_unprepare_transfer; in meson_spicc_probe()
837 master->transfer_one = meson_spicc_transfer_one; in meson_spicc_probe()
838 master->use_gpio_descriptors = true; in meson_spicc_probe()
844 dev_err(&pdev->dev, "pow2 clock registration failed\n"); in meson_spicc_probe()
848 if (spicc->data->has_enhance_clk_div) { in meson_spicc_probe()
851 dev_err(&pdev->dev, "clock registration failed\n"); in meson_spicc_probe()
856 ret = devm_spi_register_master(&pdev->dev, master); in meson_spicc_probe()
858 dev_err(&pdev->dev, "spi master registration failed\n"); in meson_spicc_probe()
865 clk_disable_unprepare(spicc->pclk); in meson_spicc_probe()
868 clk_disable_unprepare(spicc->core); in meson_spicc_probe()
881 writel(0, spicc->base + SPICC_CONREG); in meson_spicc_remove()
883 clk_disable_unprepare(spicc->core); in meson_spicc_remove()
884 clk_disable_unprepare(spicc->pclk); in meson_spicc_remove()
886 spi_master_put(spicc->master); in meson_spicc_remove()
916 .compatible = "amlogic,meson-gx-spicc",
920 .compatible = "amlogic,meson-axg-spicc",
924 .compatible = "amlogic,meson-g12a-spicc",
935 .name = "meson-spicc",