178 	int (*exec_op)(struct intel_spi *ispi,
188 static void intel_spi_dump_regs(struct intel_spi *ispi)  in intel_spi_dump_regs()  argument
193 	dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));  in intel_spi_dump_regs()
195 	value = readl(ispi->base + HSFSTS_CTL);  in intel_spi_dump_regs()
196 	dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);  in intel_spi_dump_regs()
198 		dev_dbg(ispi->dev, "-> Locked\n");  in intel_spi_dump_regs()
200 	dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));  in intel_spi_dump_regs()
201 	dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));  in intel_spi_dump_regs()
204 		dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",  in intel_spi_dump_regs()
205 			i, readl(ispi->base + FDATA(i)));  in intel_spi_dump_regs()
207 	dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));  in intel_spi_dump_regs()
209 	for (i = 0; i < ispi->nregions; i++)  in intel_spi_dump_regs()
210 		dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,  in intel_spi_dump_regs()
211 			readl(ispi->base + FREG(i)));  in intel_spi_dump_regs()
212 	for (i = 0; i < ispi->pr_num; i++)  in intel_spi_dump_regs()
213 		dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,  in intel_spi_dump_regs()
214 			readl(ispi->pregs + PR(i)));  in intel_spi_dump_regs()
216 	if (ispi->sregs) {  in intel_spi_dump_regs()
217 		value = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_dump_regs()
218 		dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);  in intel_spi_dump_regs()
219 		dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",  in intel_spi_dump_regs()
220 			readl(ispi->sregs + PREOP_OPTYPE));  in intel_spi_dump_regs()
221 		dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",  in intel_spi_dump_regs()
222 			readl(ispi->sregs + OPMENU0));  in intel_spi_dump_regs()
223 		dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",  in intel_spi_dump_regs()
224 			readl(ispi->sregs + OPMENU1));  in intel_spi_dump_regs()
227 	dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));  in intel_spi_dump_regs()
228 	dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));  in intel_spi_dump_regs()
230 	dev_dbg(ispi->dev, "Protected regions:\n");  in intel_spi_dump_regs()
231 	for (i = 0; i < ispi->pr_num; i++) {  in intel_spi_dump_regs()
234 		value = readl(ispi->pregs + PR(i));  in intel_spi_dump_regs()
241 		dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",  in intel_spi_dump_regs()
246 	dev_dbg(ispi->dev, "Flash regions:\n");  in intel_spi_dump_regs()
247 	for (i = 0; i < ispi->nregions; i++) {  in intel_spi_dump_regs()
250 		region = readl(ispi->base + FREG(i));  in intel_spi_dump_regs()
255 			dev_dbg(ispi->dev, " %02d disabled\n", i);  in intel_spi_dump_regs()
257 			dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",  in intel_spi_dump_regs()
261 	dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",  in intel_spi_dump_regs()
262 		ispi->swseq_reg ? 'S' : 'H');  in intel_spi_dump_regs()
263 	dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",  in intel_spi_dump_regs()
264 		ispi->swseq_erase ? 'S' : 'H');  in intel_spi_dump_regs()
268 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)  in intel_spi_read_block()  argument
278 		memcpy_fromio(buf, ispi->base + FDATA(i), bytes);  in intel_spi_read_block()
288 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,  in intel_spi_write_block()  argument
299 		memcpy_toio(ispi->base + FDATA(i), buf, bytes);  in intel_spi_write_block()
308 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)  in intel_spi_wait_hw_busy()  argument
312 	return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,  in intel_spi_wait_hw_busy()
317 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)  in intel_spi_wait_sw_busy()  argument
321 	return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,  in intel_spi_wait_sw_busy()
326 static bool intel_spi_set_writeable(struct intel_spi *ispi)  in intel_spi_set_writeable()  argument
328 	if (!ispi->info->set_writeable)  in intel_spi_set_writeable()
331 	return ispi->info->set_writeable(ispi->base, ispi->info->data);  in intel_spi_set_writeable()
334 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)  in intel_spi_opcode_index()  argument
339 	if (ispi->locked) {  in intel_spi_opcode_index()
340 		for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)  in intel_spi_opcode_index()
341 			if (ispi->opcodes[i] == opcode)  in intel_spi_opcode_index()
348 	writel(opcode, ispi->sregs + OPMENU0);  in intel_spi_opcode_index()
349 	preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
350 	writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
355 static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len)  in intel_spi_hw_cycle()  argument
360 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
383 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
385 	ret = intel_spi_wait_hw_busy(ispi);  in intel_spi_hw_cycle()
389 	status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
398 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,  in intel_spi_sw_cycle()  argument
405 	ret = intel_spi_opcode_index(ispi, opcode, optype);  in intel_spi_sw_cycle()
416 	atomic_preopcode = ispi->atomic_preopcode;  in intel_spi_sw_cycle()
417 	ispi->atomic_preopcode = 0;  in intel_spi_sw_cycle()
432 			preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_sw_cycle()
448 	writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
450 	ret = intel_spi_wait_sw_busy(ispi);  in intel_spi_sw_cycle()
454 	status = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
463 static u32 intel_spi_chip_addr(const struct intel_spi *ispi,  in intel_spi_chip_addr()  argument
469 	return mem->spi->chip_select == 1 ? ispi->chip0_size : 0;  in intel_spi_chip_addr()
472 static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_read_reg()  argument
480 	writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR);  in intel_spi_read_reg()
482 	if (ispi->swseq_reg)  in intel_spi_read_reg()
483 		ret = intel_spi_sw_cycle(ispi, opcode, nbytes,  in intel_spi_read_reg()
486 		ret = intel_spi_hw_cycle(ispi, opcode, nbytes);  in intel_spi_read_reg()
491 	return intel_spi_read_block(ispi, op->data.buf.in, nbytes);  in intel_spi_read_reg()
494 static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_write_reg()  argument
514 		if (!ispi->swseq_reg)  in intel_spi_write_reg()
517 		preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
519 			if (ispi->locked)  in intel_spi_write_reg()
521 			writel(opcode, ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
528 		ispi->atomic_preopcode = opcode;  in intel_spi_write_reg()
541 	writel(intel_spi_chip_addr(ispi, mem), ispi->base + FADDR);  in intel_spi_write_reg()
544 	ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes);  in intel_spi_write_reg()
548 	if (ispi->swseq_reg)  in intel_spi_write_reg()
549 		return intel_spi_sw_cycle(ispi, opcode, nbytes,  in intel_spi_write_reg()
551 	return intel_spi_hw_cycle(ispi, opcode, nbytes);  in intel_spi_write_reg()
554 static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_read()  argument
558 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_read()
568 	if (WARN_ON_ONCE(ispi->atomic_preopcode))  in intel_spi_read()
569 		ispi->atomic_preopcode = 0;  in intel_spi_read()
578 		writel(addr, ispi->base + FADDR);  in intel_spi_read()
580 		val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_read()
586 		writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_read()
588 		ret = intel_spi_wait_hw_busy(ispi);  in intel_spi_read()
592 		status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_read()
599 			dev_err(ispi->dev, "read error: %x: %#x\n", addr, status);  in intel_spi_read()
603 		ret = intel_spi_read_block(ispi, read_buf, block_size);  in intel_spi_read()
615 static int intel_spi_write(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_write()  argument
619 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_write()
626 	ispi->atomic_preopcode = 0;  in intel_spi_write()
635 		writel(addr, ispi->base + FADDR);  in intel_spi_write()
637 		val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_write()
643 		ret = intel_spi_write_block(ispi, write_buf, block_size);  in intel_spi_write()
645 			dev_err(ispi->dev, "failed to write block\n");  in intel_spi_write()
651 		writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_write()
653 		ret = intel_spi_wait_hw_busy(ispi);  in intel_spi_write()
655 			dev_err(ispi->dev, "timeout\n");  in intel_spi_write()
659 		status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_write()
666 			dev_err(ispi->dev, "write error: %x: %#x\n", addr, status);  in intel_spi_write()
678 static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem,  in intel_spi_erase()  argument
682 	u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;  in intel_spi_erase()
687 	writel(addr, ispi->base + FADDR);  in intel_spi_erase()
689 	if (ispi->swseq_erase)  in intel_spi_erase()
690 		return intel_spi_sw_cycle(ispi, opcode, 0,  in intel_spi_erase()
694 	ispi->atomic_preopcode = 0;  in intel_spi_erase()
696 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_erase()
701 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_erase()
703 	ret = intel_spi_wait_hw_busy(ispi);  in intel_spi_erase()
707 	status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_erase()
742 intel_spi_match_mem_op(struct intel_spi *ispi, const struct spi_mem_op *op)  in intel_spi_match_mem_op()  argument
746 	for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) {  in intel_spi_match_mem_op()
757 	struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master);  in intel_spi_supports_mem_op()  local
760 	iop = intel_spi_match_mem_op(ispi, op);  in intel_spi_supports_mem_op()
762 		dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);  in intel_spi_supports_mem_op()
770 	if (ispi->swseq_reg && ispi->locked) {  in intel_spi_supports_mem_op()
774 		for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) {  in intel_spi_supports_mem_op()
775 			if (ispi->opcodes[i] == op->cmd.opcode)  in intel_spi_supports_mem_op()
779 		dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);  in intel_spi_supports_mem_op()
788 	struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master);  in intel_spi_exec_mem_op()  local
791 	iop = intel_spi_match_mem_op(ispi, op);  in intel_spi_exec_mem_op()
795 	return iop->exec_op(ispi, mem, iop, op);  in intel_spi_exec_mem_op()
800 	const struct intel_spi *ispi = spi_master_get_devdata(mem->spi->master);  in intel_spi_get_name()  local
806 	return dev_name(ispi->dev);  in intel_spi_get_name()
811 	struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master);  in intel_spi_dirmap_create()  local
814 	iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl);  in intel_spi_dirmap_create()
825 	struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master);  in intel_spi_dirmap_read()  local
835 	ret = iop->exec_op(ispi, desc->mem, iop, &op);  in intel_spi_dirmap_read()
842 	struct intel_spi *ispi = spi_master_get_devdata(desc->mem->spi->master);  in intel_spi_dirmap_write()  local
851 	ret = iop->exec_op(ispi, desc->mem, iop, &op);  in intel_spi_dirmap_write()
1067 static int intel_spi_init(struct intel_spi *ispi)  in intel_spi_init()  argument
1073 	switch (ispi->info->type) {  in intel_spi_init()
1075 		ispi->sregs = ispi->base + BYT_SSFSTS_CTL;  in intel_spi_init()
1076 		ispi->pregs = ispi->base + BYT_PR;  in intel_spi_init()
1077 		ispi->nregions = BYT_FREG_NUM;  in intel_spi_init()
1078 		ispi->pr_num = BYT_PR_NUM;  in intel_spi_init()
1079 		ispi->swseq_reg = true;  in intel_spi_init()
1083 		ispi->sregs = ispi->base + LPT_SSFSTS_CTL;  in intel_spi_init()
1084 		ispi->pregs = ispi->base + LPT_PR;  in intel_spi_init()
1085 		ispi->nregions = LPT_FREG_NUM;  in intel_spi_init()
1086 		ispi->pr_num = LPT_PR_NUM;  in intel_spi_init()
1087 		ispi->swseq_reg = true;  in intel_spi_init()
1091 		ispi->sregs = ispi->base + BXT_SSFSTS_CTL;  in intel_spi_init()
1092 		ispi->pregs = ispi->base + BXT_PR;  in intel_spi_init()
1093 		ispi->nregions = BXT_FREG_NUM;  in intel_spi_init()
1094 		ispi->pr_num = BXT_PR_NUM;  in intel_spi_init()
1099 		ispi->sregs = NULL;  in intel_spi_init()
1100 		ispi->pregs = ispi->base + CNL_PR;  in intel_spi_init()
1101 		ispi->nregions = CNL_FREG_NUM;  in intel_spi_init()
1102 		ispi->pr_num = CNL_PR_NUM;  in intel_spi_init()
1111 	if (writeable && !intel_spi_set_writeable(ispi)) {  in intel_spi_init()
1112 		dev_warn(ispi->dev, "can't disable chip write protection\n");  in intel_spi_init()
1117 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_init()
1119 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_init()
1129 	lvscc = readl(ispi->base + LVSCC);  in intel_spi_init()
1130 	uvscc = readl(ispi->base + UVSCC);  in intel_spi_init()
1132 		ispi->swseq_erase = true;  in intel_spi_init()
1134 	if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)  in intel_spi_init()
1139 	if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) {  in intel_spi_init()
1140 		dev_err(ispi->dev, "software sequencer not supported, but required\n");  in intel_spi_init()
1149 	if (ispi->swseq_reg) {  in intel_spi_init()
1151 		val = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1153 		writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1157 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_init()
1158 	ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);  in intel_spi_init()
1160 	if (ispi->locked && ispi->sregs) {  in intel_spi_init()
1166 		opmenu0 = readl(ispi->sregs + OPMENU0);  in intel_spi_init()
1167 		opmenu1 = readl(ispi->sregs + OPMENU1);  in intel_spi_init()
1170 			for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {  in intel_spi_init()
1171 				ispi->opcodes[i] = opmenu0 >> i * 8;  in intel_spi_init()
1172 				ispi->opcodes[i + 4] = opmenu1 >> i * 8;  in intel_spi_init()
1178 		dev_dbg(ispi->dev, "Using erase_64k memory operations");  in intel_spi_init()
1179 		ispi->mem_ops = erase_64k_mem_ops;  in intel_spi_init()
1181 		dev_dbg(ispi->dev, "Using generic memory operations");  in intel_spi_init()
1182 		ispi->mem_ops = generic_mem_ops;  in intel_spi_init()
1185 	intel_spi_dump_regs(ispi);  in intel_spi_init()
1189 static bool intel_spi_is_protected(const struct intel_spi *ispi,  in intel_spi_is_protected()  argument
1194 	for (i = 0; i < ispi->pr_num; i++) {  in intel_spi_is_protected()
1197 		pr_value = readl(ispi->pregs + PR(i));  in intel_spi_is_protected()
1215 static void intel_spi_fill_partition(struct intel_spi *ispi,  in intel_spi_fill_partition()  argument
1231 	for (i = 1; i < ispi->nregions; i++) {  in intel_spi_fill_partition()
1234 		region = readl(ispi->base + FREG(i));  in intel_spi_fill_partition()
1248 		if (!writeable || intel_spi_is_protected(ispi, base, limit))  in intel_spi_fill_partition()
1257 static int intel_spi_read_desc(struct intel_spi *ispi)  in intel_spi_read_desc()  argument
1271 	ret = intel_spi_read(ispi, NULL, NULL, &op);  in intel_spi_read_desc()
1273 		dev_warn(ispi->dev, "failed to read descriptor\n");  in intel_spi_read_desc()
1277 	dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]);  in intel_spi_read_desc()
1278 	dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]);  in intel_spi_read_desc()
1281 		dev_warn(ispi->dev, "descriptor signature not valid\n");  in intel_spi_read_desc()
1286 	dev_dbg(ispi->dev, "FCBA=%#x\n", fcba);  in intel_spi_read_desc()
1292 	ret = intel_spi_read(ispi, NULL, NULL, &op);  in intel_spi_read_desc()
1294 		dev_warn(ispi->dev, "failed to read FLCOMP\n");  in intel_spi_read_desc()
1298 	dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp);  in intel_spi_read_desc()
1302 		ispi->chip0_size = SZ_512K;  in intel_spi_read_desc()
1305 		ispi->chip0_size = SZ_1M;  in intel_spi_read_desc()
1308 		ispi->chip0_size = SZ_2M;  in intel_spi_read_desc()
1311 		ispi->chip0_size = SZ_4M;  in intel_spi_read_desc()
1314 		ispi->chip0_size = SZ_8M;  in intel_spi_read_desc()
1317 		ispi->chip0_size = SZ_16M;  in intel_spi_read_desc()
1320 		ispi->chip0_size = SZ_32M;  in intel_spi_read_desc()
1323 		ispi->chip0_size = SZ_64M;  in intel_spi_read_desc()
1329 	dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K);  in intel_spi_read_desc()
1333 		ispi->master->num_chipselect = 1;  in intel_spi_read_desc()
1335 		ispi->master->num_chipselect = 2;  in intel_spi_read_desc()
1339 	dev_dbg(ispi->dev, "%u flash components found\n",  in intel_spi_read_desc()
1340 		ispi->master->num_chipselect);  in intel_spi_read_desc()
1344 static int intel_spi_populate_chip(struct intel_spi *ispi)  in intel_spi_populate_chip()  argument
1350 	pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);  in intel_spi_populate_chip()
1355 	pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts,  in intel_spi_populate_chip()
1360 	intel_spi_fill_partition(ispi, pdata->parts);  in intel_spi_populate_chip()
1366 	if (!spi_new_device(ispi->master, &chip))  in intel_spi_populate_chip()
1370 	if (ispi->master->num_chipselect < 2)  in intel_spi_populate_chip()
1373 	ret = intel_spi_read_desc(ispi);  in intel_spi_populate_chip()
1380 	if (!spi_new_device(ispi->master, &chip))  in intel_spi_populate_chip()
1398 	struct intel_spi *ispi;  in intel_spi_probe()  local
1401 	master = devm_spi_alloc_master(dev, sizeof(*ispi));  in intel_spi_probe()
1407 	ispi = spi_master_get_devdata(master);  in intel_spi_probe()
1409 	ispi->base = devm_ioremap_resource(dev, mem);  in intel_spi_probe()
1410 	if (IS_ERR(ispi->base))  in intel_spi_probe()
1411 		return PTR_ERR(ispi->base);  in intel_spi_probe()
1413 	ispi->dev = dev;  in intel_spi_probe()
1414 	ispi->master = master;  in intel_spi_probe()
1415 	ispi->info = info;  in intel_spi_probe()
1417 	ret = intel_spi_init(ispi);  in intel_spi_probe()
1425 	return intel_spi_populate_chip(ispi);  in intel_spi_probe()