24 #define HSFSTS_CTL			0x04  macro
195 	value = readl(ispi->base + HSFSTS_CTL);  in intel_spi_dump_regs()
312 	return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,  in intel_spi_wait_hw_busy()
360 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
383 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
389 	status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_hw_cycle()
580 		val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_read()
586 		writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_read()
592 		status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_read()
637 		val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_write()
651 		writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_write()
659 		status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_write()
696 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_erase()
701 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_erase()
707 	status = readl(ispi->base + HSFSTS_CTL);  in intel_spi_erase()
1117 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_init()
1119 	writel(val, ispi->base + HSFSTS_CTL);  in intel_spi_init()
1157 	val = readl(ispi->base + HSFSTS_CTL);  in intel_spi_init()