67 /* Offsets are from @ispi->sregs */
144  * @sregs: Start of software sequencer registers
162 	void __iomem *sregs;  member
216 	if (ispi->sregs) {  in intel_spi_dump_regs()
217 		value = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_dump_regs()
220 			readl(ispi->sregs + PREOP_OPTYPE));  in intel_spi_dump_regs()
222 			readl(ispi->sregs + OPMENU0));  in intel_spi_dump_regs()
224 			readl(ispi->sregs + OPMENU1));  in intel_spi_dump_regs()
321 	return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,  in intel_spi_wait_sw_busy()
348 	writel(opcode, ispi->sregs + OPMENU0);  in intel_spi_opcode_index()
349 	preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
350 	writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);  in intel_spi_opcode_index()
432 			preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_sw_cycle()
448 	writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
454 	status = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_sw_cycle()
517 		preop = readw(ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
521 			writel(opcode, ispi->sregs + PREOP_OPTYPE);  in intel_spi_write_reg()
1075 		ispi->sregs = ispi->base + BYT_SSFSTS_CTL;  in intel_spi_init()
1083 		ispi->sregs = ispi->base + LPT_SSFSTS_CTL;  in intel_spi_init()
1091 		ispi->sregs = ispi->base + BXT_SSFSTS_CTL;  in intel_spi_init()
1099 		ispi->sregs = NULL;  in intel_spi_init()
1139 	if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) {  in intel_spi_init()
1151 		val = readl(ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1153 		writel(val, ispi->sregs + SSFSTS_CTL);  in intel_spi_init()
1160 	if (ispi->locked && ispi->sregs) {  in intel_spi_init()
1166 		opmenu0 = readl(ispi->sregs + OPMENU0);  in intel_spi_init()
1167 		opmenu1 = readl(ispi->sregs + OPMENU1);  in intel_spi_init()