Lines Matching +full:spi +full:- +full:rx +full:- +full:delay +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/delay.h>
9 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
26 #include <linux/dma/imx-dma.h>
38 "time in us to run a transfer in polling mode\n");
74 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi);
111 void (*rx)(struct spi_imx_data *spi_imx); member
134 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
139 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
144 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
149 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
155 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
157 if (spi_imx->rx_buf) { \
158 *(type *)spi_imx->rx_buf = val; \
159 spi_imx->rx_buf += sizeof(type); \
162 spi_imx->remainder -= sizeof(type); \
170 if (spi_imx->tx_buf) { \
171 val = *(type *)spi_imx->tx_buf; \
172 spi_imx->tx_buf += sizeof(type); \
175 spi_imx->count -= sizeof(type); \
177 writel(val, spi_imx->base + MXC_CSPITXDATA); \
234 static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi, in spi_imx_can_dma() argument
239 if (!use_dma || controller->fallback) in spi_imx_can_dma()
242 if (!controller->dma_rx) in spi_imx_can_dma()
245 if (spi_imx->slave_mode) in spi_imx_can_dma()
248 if (transfer->len < spi_imx->devtype_data->fifo_size) in spi_imx_can_dma()
251 spi_imx->dynamic_burst = 0; in spi_imx_can_dma()
297 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap_u32()
299 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap_u32()
303 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_rx_swap_u32()
309 *(u32 *)spi_imx->rx_buf = val; in spi_imx_buf_rx_swap_u32()
310 spi_imx->rx_buf += sizeof(u32); in spi_imx_buf_rx_swap_u32()
313 spi_imx->remainder -= sizeof(u32); in spi_imx_buf_rx_swap_u32()
321 unaligned = spi_imx->remainder % 4; in spi_imx_buf_rx_swap()
328 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_rx_swap()
333 val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap()
335 while (unaligned--) { in spi_imx_buf_rx_swap()
336 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap()
337 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; in spi_imx_buf_rx_swap()
338 spi_imx->rx_buf++; in spi_imx_buf_rx_swap()
340 spi_imx->remainder--; in spi_imx_buf_rx_swap()
351 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap_u32()
352 val = *(u32 *)spi_imx->tx_buf; in spi_imx_buf_tx_swap_u32()
353 spi_imx->tx_buf += sizeof(u32); in spi_imx_buf_tx_swap_u32()
356 spi_imx->count -= sizeof(u32); in spi_imx_buf_tx_swap_u32()
358 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_tx_swap_u32()
365 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap_u32()
373 unaligned = spi_imx->count % 4; in spi_imx_buf_tx_swap()
380 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_tx_swap()
385 while (unaligned--) { in spi_imx_buf_tx_swap()
386 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap()
387 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); in spi_imx_buf_tx_swap()
388 spi_imx->tx_buf++; in spi_imx_buf_tx_swap()
390 spi_imx->count--; in spi_imx_buf_tx_swap()
393 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap()
398 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); in mx53_ecspi_rx_slave()
400 if (spi_imx->rx_buf) { in mx53_ecspi_rx_slave()
401 int n_bytes = spi_imx->slave_burst % sizeof(val); in mx53_ecspi_rx_slave()
406 memcpy(spi_imx->rx_buf, in mx53_ecspi_rx_slave()
407 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); in mx53_ecspi_rx_slave()
409 spi_imx->rx_buf += n_bytes; in mx53_ecspi_rx_slave()
410 spi_imx->slave_burst -= n_bytes; in mx53_ecspi_rx_slave()
413 spi_imx->remainder -= sizeof(u32); in mx53_ecspi_rx_slave()
419 int n_bytes = spi_imx->count % sizeof(val); in mx53_ecspi_tx_slave()
424 if (spi_imx->tx_buf) { in mx53_ecspi_tx_slave()
425 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, in mx53_ecspi_tx_slave()
426 spi_imx->tx_buf, n_bytes); in mx53_ecspi_tx_slave()
428 spi_imx->tx_buf += n_bytes; in mx53_ecspi_tx_slave()
431 spi_imx->count -= n_bytes; in mx53_ecspi_tx_slave()
433 writel(val, spi_imx->base + MXC_CSPITXDATA); in mx53_ecspi_tx_slave()
441 * there are two 4-bit dividers, the pre-divider divides by in mx51_ecspi_clkdiv()
442 * $pre, the post-divider by 2^$post in mx51_ecspi_clkdiv()
445 unsigned int fin = spi_imx->spi_clk; in mx51_ecspi_clkdiv()
449 post = fls(fin) - fls(fspi); in mx51_ecspi_clkdiv()
455 post = max(4U, post) - 4; in mx51_ecspi_clkdiv()
457 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", in mx51_ecspi_clkdiv()
462 pre = DIV_ROUND_UP(fin, fspi << post) - 1; in mx51_ecspi_clkdiv()
464 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", in mx51_ecspi_clkdiv()
487 writel(val, spi_imx->base + MX51_ECSPI_INT); in mx51_ecspi_intctrl()
494 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
496 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
501 writel(0, spi_imx->base + MX51_ECSPI_DMA); in mx51_disable_dma()
508 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
510 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
516 struct spi_device *spi = msg->spi; in mx51_ecspi_prepare_message() local
520 u32 testreg, delay; in mx51_ecspi_prepare_message() local
521 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
525 if (spi_imx->slave_mode) in mx51_ecspi_prepare_message()
533 if (spi->mode & SPI_READY) in mx51_ecspi_prepare_message()
534 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); in mx51_ecspi_prepare_message()
537 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); in mx51_ecspi_prepare_message()
543 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_message()
545 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
546 if (spi->mode & SPI_LOOP) in mx51_ecspi_prepare_message()
550 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
554 * is not functional for imx53 Soc, config SPI burst completed when in mx51_ecspi_prepare_message()
557 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_message()
558 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); in mx51_ecspi_prepare_message()
560 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); in mx51_ecspi_prepare_message()
562 if (spi->mode & SPI_CPOL) { in mx51_ecspi_prepare_message()
563 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); in mx51_ecspi_prepare_message()
564 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); in mx51_ecspi_prepare_message()
566 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); in mx51_ecspi_prepare_message()
567 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); in mx51_ecspi_prepare_message()
570 if (spi->mode & SPI_CS_HIGH) in mx51_ecspi_prepare_message()
571 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); in mx51_ecspi_prepare_message()
573 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); in mx51_ecspi_prepare_message()
578 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
584 * effect of the delay it takes for the hardware to apply changes in mx51_ecspi_prepare_message()
588 * the SPI communication as the device on the other end would consider in mx51_ecspi_prepare_message()
591 * Because spi_imx->spi_bus_clk is only set in prepare_message in mx51_ecspi_prepare_message()
594 * delay calculation. In case all transfers have speed_hz == 0, then in mx51_ecspi_prepare_message()
595 * min_speed_hz is ~0 and the resulting delay is zero. in mx51_ecspi_prepare_message()
597 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in mx51_ecspi_prepare_message()
598 if (!xfer->speed_hz) in mx51_ecspi_prepare_message()
600 min_speed_hz = min(xfer->speed_hz, min_speed_hz); in mx51_ecspi_prepare_message()
603 delay = (2 * 1000000) / min_speed_hz; in mx51_ecspi_prepare_message()
604 if (likely(delay < 10)) /* SCLK is faster than 200 kHz */ in mx51_ecspi_prepare_message()
605 udelay(delay); in mx51_ecspi_prepare_message()
607 usleep_range(delay, delay + 10); in mx51_ecspi_prepare_message()
613 struct spi_device *spi) in mx51_configure_cpha() argument
615 bool cpha = (spi->mode & SPI_CPHA); in mx51_configure_cpha()
616 bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; in mx51_configure_cpha()
617 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_configure_cpha()
623 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); in mx51_configure_cpha()
625 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); in mx51_configure_cpha()
627 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_configure_cpha()
631 struct spi_device *spi) in mx51_ecspi_prepare_transfer() argument
633 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
638 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_transfer()
639 ctrl |= (spi_imx->slave_burst * 8 - 1) in mx51_ecspi_prepare_transfer()
642 ctrl |= (spi_imx->bits_per_word - 1) in mx51_ecspi_prepare_transfer()
648 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); in mx51_ecspi_prepare_transfer()
649 spi_imx->spi_bus_clk = clk; in mx51_ecspi_prepare_transfer()
651 mx51_configure_cpha(spi_imx, spi); in mx51_ecspi_prepare_transfer()
657 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed) in mx51_ecspi_prepare_transfer()
662 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
671 if (spi_imx->devtype_data->tx_glitch_fixed) in mx51_setup_wml()
672 tx_wml = spi_imx->wml; in mx51_setup_wml()
677 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | in mx51_setup_wml()
679 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | in mx51_setup_wml()
681 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); in mx51_setup_wml()
686 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; in mx51_ecspi_rx_available()
693 readl(spi_imx->base + MXC_CSPIRXDATA); in mx51_ecspi_reset()
736 writel(val, spi_imx->base + MXC_CSPIINT); in mx31_intctrl()
743 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
745 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
755 struct spi_device *spi) in mx31_prepare_transfer() argument
760 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx31_prepare_transfer()
762 spi_imx->spi_bus_clk = clk; in mx31_prepare_transfer()
765 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; in mx31_prepare_transfer()
768 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; in mx31_prepare_transfer()
771 if (spi->mode & SPI_CPHA) in mx31_prepare_transfer()
773 if (spi->mode & SPI_CPOL) in mx31_prepare_transfer()
775 if (spi->mode & SPI_CS_HIGH) in mx31_prepare_transfer()
777 if (!spi->cs_gpiod) in mx31_prepare_transfer()
778 reg |= (spi->chip_select) << in mx31_prepare_transfer()
782 if (spi_imx->usedma) in mx31_prepare_transfer()
785 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_prepare_transfer()
787 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
788 if (spi->mode & SPI_LOOP) in mx31_prepare_transfer()
792 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
794 if (spi_imx->usedma) { in mx31_prepare_transfer()
800 spi_imx->base + MX31_CSPI_DMAREG); in mx31_prepare_transfer()
808 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; in mx31_rx_available()
814 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) in mx31_reset()
815 readl(spi_imx->base + MXC_CSPIRXDATA); in mx31_reset()
840 writel(val, spi_imx->base + MXC_CSPIINT); in mx21_intctrl()
847 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
849 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
859 struct spi_device *spi) in mx21_prepare_transfer() argument
865 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) in mx21_prepare_transfer()
867 spi_imx->spi_bus_clk = clk; in mx21_prepare_transfer()
869 reg |= spi_imx->bits_per_word - 1; in mx21_prepare_transfer()
871 if (spi->mode & SPI_CPHA) in mx21_prepare_transfer()
873 if (spi->mode & SPI_CPOL) in mx21_prepare_transfer()
875 if (spi->mode & SPI_CS_HIGH) in mx21_prepare_transfer()
877 if (!spi->cs_gpiod) in mx21_prepare_transfer()
878 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT; in mx21_prepare_transfer()
880 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_prepare_transfer()
887 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; in mx21_rx_available()
892 writel(1, spi_imx->base + MXC_RESET); in mx21_reset()
915 writel(val, spi_imx->base + MXC_CSPIINT); in mx1_intctrl()
922 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
924 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
934 struct spi_device *spi) in mx1_prepare_transfer() argument
939 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx1_prepare_transfer()
941 spi_imx->spi_bus_clk = clk; in mx1_prepare_transfer()
943 reg |= spi_imx->bits_per_word - 1; in mx1_prepare_transfer()
945 if (spi->mode & SPI_CPHA) in mx1_prepare_transfer()
947 if (spi->mode & SPI_CPOL) in mx1_prepare_transfer()
950 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_prepare_transfer()
957 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; in mx1_rx_available()
962 writel(1, spi_imx->base + MXC_RESET); in mx1_reset()
1087 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1088 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1089 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1090 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1091 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1092 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1093 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1094 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1103 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1105 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); in spi_imx_set_burst_len()
1106 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1118 if (!spi_imx->remainder) { in spi_imx_push()
1119 if (spi_imx->dynamic_burst) { in spi_imx_push()
1122 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; in spi_imx_push()
1129 spi_imx->remainder = burst_len; in spi_imx_push()
1131 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_push()
1135 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { in spi_imx_push()
1136 if (!spi_imx->count) in spi_imx_push()
1138 if (spi_imx->dynamic_burst && in spi_imx_push()
1139 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4)) in spi_imx_push()
1141 spi_imx->tx(spi_imx); in spi_imx_push()
1142 spi_imx->txfifo++; in spi_imx_push()
1145 if (!spi_imx->slave_mode) in spi_imx_push()
1146 spi_imx->devtype_data->trigger(spi_imx); in spi_imx_push()
1153 while (spi_imx->txfifo && in spi_imx_isr()
1154 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_isr()
1155 spi_imx->rx(spi_imx); in spi_imx_isr()
1156 spi_imx->txfifo--; in spi_imx_isr()
1159 if (spi_imx->count) { in spi_imx_isr()
1164 if (spi_imx->txfifo) { in spi_imx_isr()
1165 /* No data left to push, but still waiting for rx data, in spi_imx_isr()
1168 spi_imx->devtype_data->intctrl( in spi_imx_isr()
1173 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_isr()
1174 complete(&spi_imx->xfer_done); in spi_imx_isr()
1183 struct dma_slave_config rx = {}, tx = {}; in spi_imx_dma_configure() local
1186 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { in spi_imx_dma_configure()
1197 return -EINVAL; in spi_imx_dma_configure()
1201 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; in spi_imx_dma_configure()
1203 tx.dst_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1204 ret = dmaengine_slave_config(controller->dma_tx, &tx); in spi_imx_dma_configure()
1206 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1210 rx.direction = DMA_DEV_TO_MEM; in spi_imx_dma_configure()
1211 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; in spi_imx_dma_configure()
1212 rx.src_addr_width = buswidth; in spi_imx_dma_configure()
1213 rx.src_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1214 ret = dmaengine_slave_config(controller->dma_rx, &rx); in spi_imx_dma_configure()
1216 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1223 static int spi_imx_setupxfer(struct spi_device *spi, in spi_imx_setupxfer() argument
1226 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_setupxfer()
1231 if (!t->speed_hz) { in spi_imx_setupxfer()
1232 if (!spi->max_speed_hz) { in spi_imx_setupxfer()
1233 dev_err(&spi->dev, "no speed_hz provided!\n"); in spi_imx_setupxfer()
1234 return -EINVAL; in spi_imx_setupxfer()
1236 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); in spi_imx_setupxfer()
1237 spi_imx->spi_bus_clk = spi->max_speed_hz; in spi_imx_setupxfer()
1239 spi_imx->spi_bus_clk = t->speed_hz; in spi_imx_setupxfer()
1241 spi_imx->bits_per_word = t->bits_per_word; in spi_imx_setupxfer()
1244 * Initialize the functions for transfer. To transfer non byte-aligned in spi_imx_setupxfer()
1245 * words, we have to use multiple word-size bursts, we can't use in spi_imx_setupxfer()
1248 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode && in spi_imx_setupxfer()
1249 !(spi->mode & SPI_CS_WORD) && in spi_imx_setupxfer()
1250 (spi_imx->bits_per_word == 8 || in spi_imx_setupxfer()
1251 spi_imx->bits_per_word == 16 || in spi_imx_setupxfer()
1252 spi_imx->bits_per_word == 32)) { in spi_imx_setupxfer()
1254 spi_imx->rx = spi_imx_buf_rx_swap; in spi_imx_setupxfer()
1255 spi_imx->tx = spi_imx_buf_tx_swap; in spi_imx_setupxfer()
1256 spi_imx->dynamic_burst = 1; in spi_imx_setupxfer()
1259 if (spi_imx->bits_per_word <= 8) { in spi_imx_setupxfer()
1260 spi_imx->rx = spi_imx_buf_rx_u8; in spi_imx_setupxfer()
1261 spi_imx->tx = spi_imx_buf_tx_u8; in spi_imx_setupxfer()
1262 } else if (spi_imx->bits_per_word <= 16) { in spi_imx_setupxfer()
1263 spi_imx->rx = spi_imx_buf_rx_u16; in spi_imx_setupxfer()
1264 spi_imx->tx = spi_imx_buf_tx_u16; in spi_imx_setupxfer()
1266 spi_imx->rx = spi_imx_buf_rx_u32; in spi_imx_setupxfer()
1267 spi_imx->tx = spi_imx_buf_tx_u32; in spi_imx_setupxfer()
1269 spi_imx->dynamic_burst = 0; in spi_imx_setupxfer()
1272 if (spi_imx_can_dma(spi_imx->controller, spi, t)) in spi_imx_setupxfer()
1273 spi_imx->usedma = true; in spi_imx_setupxfer()
1275 spi_imx->usedma = false; in spi_imx_setupxfer()
1277 spi_imx->rx_only = ((t->tx_buf == NULL) in spi_imx_setupxfer()
1278 || (t->tx_buf == spi->controller->dummy_tx)); in spi_imx_setupxfer()
1280 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) { in spi_imx_setupxfer()
1281 spi_imx->rx = mx53_ecspi_rx_slave; in spi_imx_setupxfer()
1282 spi_imx->tx = mx53_ecspi_tx_slave; in spi_imx_setupxfer()
1283 spi_imx->slave_burst = t->len; in spi_imx_setupxfer()
1286 spi_imx->devtype_data->prepare_transfer(spi_imx, spi); in spi_imx_setupxfer()
1293 struct spi_controller *controller = spi_imx->controller; in spi_imx_sdma_exit()
1295 if (controller->dma_rx) { in spi_imx_sdma_exit()
1296 dma_release_channel(controller->dma_rx); in spi_imx_sdma_exit()
1297 controller->dma_rx = NULL; in spi_imx_sdma_exit()
1300 if (controller->dma_tx) { in spi_imx_sdma_exit()
1301 dma_release_channel(controller->dma_tx); in spi_imx_sdma_exit()
1302 controller->dma_tx = NULL; in spi_imx_sdma_exit()
1311 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; in spi_imx_sdma_init()
1314 controller->dma_tx = dma_request_chan(dev, "tx"); in spi_imx_sdma_init()
1315 if (IS_ERR(controller->dma_tx)) { in spi_imx_sdma_init()
1316 ret = PTR_ERR(controller->dma_tx); in spi_imx_sdma_init()
1318 controller->dma_tx = NULL; in spi_imx_sdma_init()
1322 /* Prepare for RX : */ in spi_imx_sdma_init()
1323 controller->dma_rx = dma_request_chan(dev, "rx"); in spi_imx_sdma_init()
1324 if (IS_ERR(controller->dma_rx)) { in spi_imx_sdma_init()
1325 ret = PTR_ERR(controller->dma_rx); in spi_imx_sdma_init()
1326 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); in spi_imx_sdma_init()
1327 controller->dma_rx = NULL; in spi_imx_sdma_init()
1331 init_completion(&spi_imx->dma_rx_completion); in spi_imx_sdma_init()
1332 init_completion(&spi_imx->dma_tx_completion); in spi_imx_sdma_init()
1333 controller->can_dma = spi_imx_can_dma; in spi_imx_sdma_init()
1334 controller->max_dma_len = MAX_SDMA_BD_BYTES; in spi_imx_sdma_init()
1335 spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX | in spi_imx_sdma_init()
1348 complete(&spi_imx->dma_rx_completion); in spi_imx_dma_rx_callback()
1355 complete(&spi_imx->dma_tx_completion); in spi_imx_dma_tx_callback()
1362 /* Time with actual data transfer and CS change delay related to HW */ in spi_imx_calculate_timeout()
1363 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; in spi_imx_calculate_timeout()
1378 struct spi_controller *controller = spi_imx->controller; in spi_imx_dma_transfer()
1379 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in spi_imx_dma_transfer() local
1380 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); in spi_imx_dma_transfer()
1385 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); in spi_imx_dma_transfer()
1386 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { in spi_imx_dma_transfer()
1394 spi_imx->wml = i; in spi_imx_dma_transfer()
1400 if (!spi_imx->devtype_data->setup_wml) { in spi_imx_dma_transfer()
1401 dev_err(spi_imx->dev, "No setup_wml()?\n"); in spi_imx_dma_transfer()
1402 ret = -EINVAL; in spi_imx_dma_transfer()
1405 spi_imx->devtype_data->setup_wml(spi_imx); in spi_imx_dma_transfer()
1408 * The TX DMA setup starts the transfer, so make sure RX is configured in spi_imx_dma_transfer()
1411 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, in spi_imx_dma_transfer()
1412 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in spi_imx_dma_transfer()
1415 ret = -EINVAL; in spi_imx_dma_transfer()
1419 desc_rx->callback = spi_imx_dma_rx_callback; in spi_imx_dma_transfer()
1420 desc_rx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1422 reinit_completion(&spi_imx->dma_rx_completion); in spi_imx_dma_transfer()
1423 dma_async_issue_pending(controller->dma_rx); in spi_imx_dma_transfer()
1425 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, in spi_imx_dma_transfer()
1426 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in spi_imx_dma_transfer()
1429 dmaengine_terminate_all(controller->dma_tx); in spi_imx_dma_transfer()
1430 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1431 return -EINVAL; in spi_imx_dma_transfer()
1434 desc_tx->callback = spi_imx_dma_tx_callback; in spi_imx_dma_transfer()
1435 desc_tx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1437 reinit_completion(&spi_imx->dma_tx_completion); in spi_imx_dma_transfer()
1438 dma_async_issue_pending(controller->dma_tx); in spi_imx_dma_transfer()
1440 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_dma_transfer()
1443 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, in spi_imx_dma_transfer()
1446 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); in spi_imx_dma_transfer()
1447 dmaengine_terminate_all(controller->dma_tx); in spi_imx_dma_transfer()
1448 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1449 return -ETIMEDOUT; in spi_imx_dma_transfer()
1452 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion, in spi_imx_dma_transfer()
1455 dev_err(&controller->dev, "I/O Error in DMA RX\n"); in spi_imx_dma_transfer()
1456 spi_imx->devtype_data->reset(spi_imx); in spi_imx_dma_transfer()
1457 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1458 return -ETIMEDOUT; in spi_imx_dma_transfer()
1464 transfer->error |= SPI_TRANS_FAIL_NO_START; in spi_imx_dma_transfer()
1468 static int spi_imx_pio_transfer(struct spi_device *spi, in spi_imx_pio_transfer() argument
1471 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_pio_transfer()
1475 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer()
1476 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer()
1477 spi_imx->count = transfer->len; in spi_imx_pio_transfer()
1478 spi_imx->txfifo = 0; in spi_imx_pio_transfer()
1479 spi_imx->remainder = 0; in spi_imx_pio_transfer()
1481 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer()
1485 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); in spi_imx_pio_transfer()
1487 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_pio_transfer()
1489 timeout = wait_for_completion_timeout(&spi_imx->xfer_done, in spi_imx_pio_transfer()
1492 dev_err(&spi->dev, "I/O Error in PIO\n"); in spi_imx_pio_transfer()
1493 spi_imx->devtype_data->reset(spi_imx); in spi_imx_pio_transfer()
1494 return -ETIMEDOUT; in spi_imx_pio_transfer()
1500 static int spi_imx_poll_transfer(struct spi_device *spi, in spi_imx_poll_transfer() argument
1503 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_poll_transfer()
1506 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_poll_transfer()
1507 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_poll_transfer()
1508 spi_imx->count = transfer->len; in spi_imx_poll_transfer()
1509 spi_imx->txfifo = 0; in spi_imx_poll_transfer()
1510 spi_imx->remainder = 0; in spi_imx_poll_transfer()
1518 timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies; in spi_imx_poll_transfer()
1519 while (spi_imx->txfifo) { in spi_imx_poll_transfer()
1520 /* RX */ in spi_imx_poll_transfer()
1521 while (spi_imx->txfifo && in spi_imx_poll_transfer()
1522 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_poll_transfer()
1523 spi_imx->rx(spi_imx); in spi_imx_poll_transfer()
1524 spi_imx->txfifo--; in spi_imx_poll_transfer()
1528 if (spi_imx->count) { in spi_imx_poll_transfer()
1533 if (spi_imx->txfifo && in spi_imx_poll_transfer()
1536 dev_err_ratelimited(&spi->dev, in spi_imx_poll_transfer()
1537 "timeout period reached: jiffies: %lu- falling back to interrupt mode\n", in spi_imx_poll_transfer()
1538 jiffies - timeout); in spi_imx_poll_transfer()
1541 return spi_imx_pio_transfer(spi, transfer); in spi_imx_poll_transfer()
1548 static int spi_imx_pio_transfer_slave(struct spi_device *spi, in spi_imx_pio_transfer_slave() argument
1551 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_pio_transfer_slave()
1555 transfer->len > MX53_MAX_TRANSFER_BYTES) { in spi_imx_pio_transfer_slave()
1556 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", in spi_imx_pio_transfer_slave()
1558 return -EMSGSIZE; in spi_imx_pio_transfer_slave()
1561 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer_slave()
1562 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer_slave()
1563 spi_imx->count = transfer->len; in spi_imx_pio_transfer_slave()
1564 spi_imx->txfifo = 0; in spi_imx_pio_transfer_slave()
1565 spi_imx->remainder = 0; in spi_imx_pio_transfer_slave()
1567 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer_slave()
1568 spi_imx->slave_aborted = false; in spi_imx_pio_transfer_slave()
1572 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); in spi_imx_pio_transfer_slave()
1574 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || in spi_imx_pio_transfer_slave()
1575 spi_imx->slave_aborted) { in spi_imx_pio_transfer_slave()
1576 dev_dbg(&spi->dev, "interrupted\n"); in spi_imx_pio_transfer_slave()
1577 ret = -EINTR; in spi_imx_pio_transfer_slave()
1586 if (spi_imx->devtype_data->disable) in spi_imx_pio_transfer_slave()
1587 spi_imx->devtype_data->disable(spi_imx); in spi_imx_pio_transfer_slave()
1593 struct spi_device *spi, in spi_imx_transfer_one() argument
1596 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_transfer_one()
1599 spi_imx_setupxfer(spi, transfer); in spi_imx_transfer_one()
1600 transfer->effective_speed_hz = spi_imx->spi_bus_clk; in spi_imx_transfer_one()
1603 while (spi_imx->devtype_data->rx_available(spi_imx)) in spi_imx_transfer_one()
1604 readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_transfer_one()
1606 if (spi_imx->slave_mode) in spi_imx_transfer_one()
1607 return spi_imx_pio_transfer_slave(spi, transfer); in spi_imx_transfer_one()
1611 * transfer, the SPI transfer has already been mapped, so we in spi_imx_transfer_one()
1614 if (spi_imx->usedma) in spi_imx_transfer_one()
1617 * Calculate the estimated time in us the transfer runs. Find in spi_imx_transfer_one()
1621 byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1; in spi_imx_transfer_one()
1624 if (transfer->len < byte_limit) in spi_imx_transfer_one()
1625 return spi_imx_poll_transfer(spi, transfer); in spi_imx_transfer_one()
1627 return spi_imx_pio_transfer(spi, transfer); in spi_imx_transfer_one()
1630 static int spi_imx_setup(struct spi_device *spi) in spi_imx_setup() argument
1632 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, in spi_imx_setup()
1633 spi->mode, spi->bits_per_word, spi->max_speed_hz); in spi_imx_setup()
1638 static void spi_imx_cleanup(struct spi_device *spi) in spi_imx_cleanup() argument
1648 ret = pm_runtime_resume_and_get(spi_imx->dev); in spi_imx_prepare_message()
1650 dev_err(spi_imx->dev, "failed to enable clock\n"); in spi_imx_prepare_message()
1654 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); in spi_imx_prepare_message()
1656 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_prepare_message()
1657 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_prepare_message()
1668 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_unprepare_message()
1669 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_unprepare_message()
1677 spi_imx->slave_aborted = true; in spi_imx_slave_abort()
1678 complete(&spi_imx->xfer_done); in spi_imx_slave_abort()
1685 struct device_node *np = pdev->dev.of_node; in spi_imx_probe()
1691 of_device_get_match_data(&pdev->dev); in spi_imx_probe()
1695 slave_mode = devtype_data->has_slavemode && in spi_imx_probe()
1696 of_property_read_bool(np, "spi-slave"); in spi_imx_probe()
1698 controller = spi_alloc_slave(&pdev->dev, in spi_imx_probe()
1701 controller = spi_alloc_master(&pdev->dev, in spi_imx_probe()
1704 return -ENOMEM; in spi_imx_probe()
1706 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); in spi_imx_probe()
1714 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); in spi_imx_probe()
1715 controller->bus_num = np ? -1 : pdev->id; in spi_imx_probe()
1716 controller->use_gpio_descriptors = true; in spi_imx_probe()
1719 spi_imx->controller = controller; in spi_imx_probe()
1720 spi_imx->dev = &pdev->dev; in spi_imx_probe()
1721 spi_imx->slave_mode = slave_mode; in spi_imx_probe()
1723 spi_imx->devtype_data = devtype_data; in spi_imx_probe()
1731 if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) in spi_imx_probe()
1732 controller->num_chipselect = val; in spi_imx_probe()
1734 controller->num_chipselect = 3; in spi_imx_probe()
1736 spi_imx->controller->transfer_one = spi_imx_transfer_one; in spi_imx_probe()
1737 spi_imx->controller->setup = spi_imx_setup; in spi_imx_probe()
1738 spi_imx->controller->cleanup = spi_imx_cleanup; in spi_imx_probe()
1739 spi_imx->controller->prepare_message = spi_imx_prepare_message; in spi_imx_probe()
1740 spi_imx->controller->unprepare_message = spi_imx_unprepare_message; in spi_imx_probe()
1741 spi_imx->controller->slave_abort = spi_imx_slave_abort; in spi_imx_probe()
1742 spi_imx->controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; in spi_imx_probe()
1746 spi_imx->controller->mode_bits |= SPI_LOOP | SPI_READY; in spi_imx_probe()
1749 spi_imx->controller->mode_bits |= SPI_RX_CPHA_FLIP; in spi_imx_probe()
1752 device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) in spi_imx_probe()
1754 * When using HW-CS implementing SPI_CS_WORD can be done by just in spi_imx_probe()
1758 spi_imx->controller->mode_bits |= SPI_CS_WORD; in spi_imx_probe()
1760 spi_imx->spi_drctl = spi_drctl; in spi_imx_probe()
1762 init_completion(&spi_imx->xfer_done); in spi_imx_probe()
1765 spi_imx->base = devm_ioremap_resource(&pdev->dev, res); in spi_imx_probe()
1766 if (IS_ERR(spi_imx->base)) { in spi_imx_probe()
1767 ret = PTR_ERR(spi_imx->base); in spi_imx_probe()
1770 spi_imx->base_phys = res->start; in spi_imx_probe()
1778 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, in spi_imx_probe()
1779 dev_name(&pdev->dev), spi_imx); in spi_imx_probe()
1781 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in spi_imx_probe()
1785 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in spi_imx_probe()
1786 if (IS_ERR(spi_imx->clk_ipg)) { in spi_imx_probe()
1787 ret = PTR_ERR(spi_imx->clk_ipg); in spi_imx_probe()
1791 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); in spi_imx_probe()
1792 if (IS_ERR(spi_imx->clk_per)) { in spi_imx_probe()
1793 ret = PTR_ERR(spi_imx->clk_per); in spi_imx_probe()
1797 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_probe()
1801 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_probe()
1805 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); in spi_imx_probe()
1806 pm_runtime_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1807 pm_runtime_get_noresume(spi_imx->dev); in spi_imx_probe()
1808 pm_runtime_set_active(spi_imx->dev); in spi_imx_probe()
1809 pm_runtime_enable(spi_imx->dev); in spi_imx_probe()
1811 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); in spi_imx_probe()
1816 if (spi_imx->devtype_data->has_dmamode) { in spi_imx_probe()
1817 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller); in spi_imx_probe()
1818 if (ret == -EPROBE_DEFER) in spi_imx_probe()
1822 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", in spi_imx_probe()
1826 spi_imx->devtype_data->reset(spi_imx); in spi_imx_probe()
1828 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_probe()
1830 controller->dev.of_node = pdev->dev.of_node; in spi_imx_probe()
1833 dev_err_probe(&pdev->dev, ret, "register controller failed\n"); in spi_imx_probe()
1837 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_probe()
1838 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_probe()
1843 if (spi_imx->devtype_data->has_dmamode) in spi_imx_probe()
1846 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1847 pm_runtime_set_suspended(&pdev->dev); in spi_imx_probe()
1848 pm_runtime_disable(spi_imx->dev); in spi_imx_probe()
1850 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_probe()
1852 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_probe()
1867 ret = pm_runtime_resume_and_get(spi_imx->dev); in spi_imx_remove()
1869 dev_err(spi_imx->dev, "failed to enable clock\n"); in spi_imx_remove()
1873 writel(0, spi_imx->base + MXC_CSPICTRL); in spi_imx_remove()
1875 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_remove()
1876 pm_runtime_put_sync(spi_imx->dev); in spi_imx_remove()
1877 pm_runtime_disable(spi_imx->dev); in spi_imx_remove()
1892 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_runtime_resume()
1896 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_runtime_resume()
1898 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_resume()
1912 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_suspend()
1913 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_runtime_suspend()
1947 MODULE_DESCRIPTION("i.MX SPI Controller driver");