Lines Matching +full:gpi +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
15 #include <linux/qcom-geni-se.h>
109 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
110 speed_hz * mas->oversampling, in get_spi_clk_cfg()
113 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", in get_spi_clk_cfg()
118 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); in get_spi_clk_cfg()
119 actual_hz = sclk_freq / (mas->oversampling * *clk_div); in get_spi_clk_cfg()
121 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, in get_spi_clk_cfg()
123 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); in get_spi_clk_cfg()
125 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); in get_spi_clk_cfg()
127 mas->cur_sclk_hz = sclk_freq; in get_spi_clk_cfg()
137 struct geni_se *se = &mas->se; in handle_fifo_timeout()
139 spin_lock_irq(&mas->lock); in handle_fifo_timeout()
140 reinit_completion(&mas->cancel_done); in handle_fifo_timeout()
141 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in handle_fifo_timeout()
142 mas->cur_xfer = NULL; in handle_fifo_timeout()
144 spin_unlock_irq(&mas->lock); in handle_fifo_timeout()
146 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); in handle_fifo_timeout()
150 spin_lock_irq(&mas->lock); in handle_fifo_timeout()
151 reinit_completion(&mas->abort_done); in handle_fifo_timeout()
153 spin_unlock_irq(&mas->lock); in handle_fifo_timeout()
155 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); in handle_fifo_timeout()
157 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); in handle_fifo_timeout()
163 mas->abort_failed = true; in handle_fifo_timeout()
171 dmaengine_terminate_sync(mas->tx); in handle_gpi_timeout()
172 dmaengine_terminate_sync(mas->rx); in handle_gpi_timeout()
179 switch (mas->cur_xfer_mode) { in spi_geni_handle_err()
187 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode); in spi_geni_handle_err()
193 struct geni_se *se = &mas->se; in spi_geni_is_abort_still_pending()
196 if (!mas->abort_failed) in spi_geni_is_abort_still_pending()
205 spin_lock_irq(&mas->lock); in spi_geni_is_abort_still_pending()
206 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in spi_geni_is_abort_still_pending()
207 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); in spi_geni_is_abort_still_pending()
208 spin_unlock_irq(&mas->lock); in spi_geni_is_abort_still_pending()
211 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", in spi_geni_is_abort_still_pending()
220 mas->abort_failed = false; in spi_geni_is_abort_still_pending()
227 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); in spi_geni_set_cs()
228 struct spi_master *spi = dev_get_drvdata(mas->dev); in spi_geni_set_cs()
229 struct geni_se *se = &mas->se; in spi_geni_set_cs()
232 if (!(slv->mode & SPI_CS_HIGH)) in spi_geni_set_cs()
235 if (set_flag == mas->cs_flag) in spi_geni_set_cs()
238 pm_runtime_get_sync(mas->dev); in spi_geni_set_cs()
241 dev_err(mas->dev, "Can't set chip select\n"); in spi_geni_set_cs()
245 spin_lock_irq(&mas->lock); in spi_geni_set_cs()
246 if (mas->cur_xfer) { in spi_geni_set_cs()
247 dev_err(mas->dev, "Can't set CS when prev xfer running\n"); in spi_geni_set_cs()
248 spin_unlock_irq(&mas->lock); in spi_geni_set_cs()
252 mas->cs_flag = set_flag; in spi_geni_set_cs()
253 reinit_completion(&mas->cs_done); in spi_geni_set_cs()
258 spin_unlock_irq(&mas->lock); in spi_geni_set_cs()
260 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); in spi_geni_set_cs()
262 dev_warn(mas->dev, "Timeout setting chip select\n"); in spi_geni_set_cs()
267 pm_runtime_put(mas->dev); in spi_geni_set_cs()
275 struct geni_se *se = &mas->se; in spi_setup_word_len()
282 if (!(mas->fifo_width_bits % bits_per_word)) in spi_setup_word_len()
283 pack_words = mas->fifo_width_bits / bits_per_word; in spi_setup_word_len()
286 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, in spi_setup_word_len()
288 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; in spi_setup_word_len()
289 writel(word_len, se->base + SE_SPI_WORD_LEN); in spi_setup_word_len()
296 struct geni_se *se = &mas->se; in geni_spi_set_clock_and_bw()
299 if (clk_hz == mas->cur_speed_hz) in geni_spi_set_clock_and_bw()
304 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); in geni_spi_set_clock_and_bw()
315 mas->cur_speed_hz = clk_hz; in geni_spi_set_clock_and_bw()
319 writel(clk_sel, se->base + SE_GENI_CLK_SEL); in geni_spi_set_clock_and_bw()
320 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); in geni_spi_set_clock_and_bw()
323 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); in geni_spi_set_clock_and_bw()
335 struct geni_se *se = &mas->se; in setup_fifo_params()
339 if (mas->last_mode != spi_slv->mode) { in setup_fifo_params()
340 if (spi_slv->mode & SPI_LOOP) in setup_fifo_params()
343 if (spi_slv->mode & SPI_CPOL) in setup_fifo_params()
346 if (spi_slv->mode & SPI_CPHA) in setup_fifo_params()
349 if (spi_slv->mode & SPI_CS_HIGH) in setup_fifo_params()
350 demux_output_inv = BIT(spi_slv->chip_select); in setup_fifo_params()
352 demux_sel = spi_slv->chip_select; in setup_fifo_params()
353 mas->cur_bits_per_word = spi_slv->bits_per_word; in setup_fifo_params()
355 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); in setup_fifo_params()
356 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); in setup_fifo_params()
357 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); in setup_fifo_params()
358 writel(cpha, se->base + SE_SPI_CPHA); in setup_fifo_params()
359 writel(cpol, se->base + SE_SPI_CPOL); in setup_fifo_params()
360 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); in setup_fifo_params()
362 mas->last_mode = spi_slv->mode; in setup_fifo_params()
365 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); in setup_fifo_params()
373 spi->cur_msg->status = -EIO; in spi_gsi_callback_result()
374 if (result->result != DMA_TRANS_NOERROR) { in spi_gsi_callback_result()
375 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result); in spi_gsi_callback_result()
380 if (!result->residue) { in spi_gsi_callback_result()
381 spi->cur_msg->status = 0; in spi_gsi_callback_result()
382 dev_dbg(&spi->dev, "DMA txn completed\n"); in spi_gsi_callback_result()
384 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue); in spi_gsi_callback_result()
394 struct dma_slave_config config = {}; in setup_gsi_xfer() local
399 config.peripheral_config = &peripheral; in setup_gsi_xfer()
400 config.peripheral_size = sizeof(peripheral); in setup_gsi_xfer()
403 if (xfer->bits_per_word != mas->cur_bits_per_word || in setup_gsi_xfer()
404 xfer->speed_hz != mas->cur_speed_hz) { in setup_gsi_xfer()
405 mas->cur_bits_per_word = xfer->bits_per_word; in setup_gsi_xfer()
406 mas->cur_speed_hz = xfer->speed_hz; in setup_gsi_xfer()
409 if (xfer->tx_buf && xfer->rx_buf) { in setup_gsi_xfer()
411 } else if (xfer->tx_buf) { in setup_gsi_xfer()
414 } else if (xfer->rx_buf) { in setup_gsi_xfer()
416 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { in setup_gsi_xfer()
417 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); in setup_gsi_xfer()
419 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; in setup_gsi_xfer()
421 peripheral.rx_len = (xfer->len / bytes_per_word); in setup_gsi_xfer()
425 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); in setup_gsi_xfer()
426 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); in setup_gsi_xfer()
427 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); in setup_gsi_xfer()
428 peripheral.cs = spi_slv->chip_select; in setup_gsi_xfer()
430 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN; in setup_gsi_xfer()
432 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, in setup_gsi_xfer()
435 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret); in setup_gsi_xfer()
439 if (!xfer->cs_change) { in setup_gsi_xfer()
440 if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) in setup_gsi_xfer()
445 dmaengine_slave_config(mas->rx, &config); in setup_gsi_xfer()
446 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, in setup_gsi_xfer()
449 dev_err(mas->dev, "Err setting up rx desc\n"); in setup_gsi_xfer()
450 return -EIO; in setup_gsi_xfer()
458 dmaengine_slave_config(mas->tx, &config); in setup_gsi_xfer()
459 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, in setup_gsi_xfer()
462 dev_err(mas->dev, "Err setting up tx desc\n"); in setup_gsi_xfer()
463 return -EIO; in setup_gsi_xfer()
466 tx_desc->callback_result = spi_gsi_callback_result; in setup_gsi_xfer()
467 tx_desc->callback_param = spi; in setup_gsi_xfer()
474 dma_async_issue_pending(mas->rx); in setup_gsi_xfer()
476 dma_async_issue_pending(mas->tx); in setup_gsi_xfer()
483 struct spi_geni_master *mas = spi_master_get_devdata(slv->master); in geni_can_dma()
486 return mas->cur_xfer_mode != GENI_SE_FIFO; in geni_can_dma()
495 switch (mas->cur_xfer_mode) { in spi_geni_prepare_message()
498 return -EBUSY; in spi_geni_prepare_message()
499 ret = setup_fifo_params(spi_msg->spi, spi); in spi_geni_prepare_message()
501 dev_err(mas->dev, "Couldn't select mode %d\n", ret); in spi_geni_prepare_message()
505 /* nothing to do for GPI DMA */ in spi_geni_prepare_message()
509 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode); in spi_geni_prepare_message()
510 return -EINVAL; in spi_geni_prepare_message()
517 mas->tx = dma_request_chan(mas->dev, "tx"); in spi_geni_grab_gpi_chan()
518 if (IS_ERR(mas->tx)) { in spi_geni_grab_gpi_chan()
519 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx), in spi_geni_grab_gpi_chan()
524 mas->rx = dma_request_chan(mas->dev, "rx"); in spi_geni_grab_gpi_chan()
525 if (IS_ERR(mas->rx)) { in spi_geni_grab_gpi_chan()
526 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx), in spi_geni_grab_gpi_chan()
534 mas->rx = NULL; in spi_geni_grab_gpi_chan()
535 dma_release_channel(mas->tx); in spi_geni_grab_gpi_chan()
537 mas->tx = NULL; in spi_geni_grab_gpi_chan()
543 if (mas->rx) { in spi_geni_release_dma_chan()
544 dma_release_channel(mas->rx); in spi_geni_release_dma_chan()
545 mas->rx = NULL; in spi_geni_release_dma_chan()
548 if (mas->tx) { in spi_geni_release_dma_chan()
549 dma_release_channel(mas->tx); in spi_geni_release_dma_chan()
550 mas->tx = NULL; in spi_geni_release_dma_chan()
556 struct geni_se *se = &mas->se; in spi_geni_init()
559 int ret = -ENXIO; in spi_geni_init()
561 pm_runtime_get_sync(mas->dev); in spi_geni_init()
565 dev_err(mas->dev, "Invalid proto %d\n", proto); in spi_geni_init()
568 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); in spi_geni_init()
571 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); in spi_geni_init()
575 * RX FIFO RFR level to fifo_depth-2. in spi_geni_init()
577 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); in spi_geni_init()
579 mas->tx_wm = 1; in spi_geni_init()
585 mas->oversampling = 2; in spi_geni_init()
587 mas->oversampling = 1; in spi_geni_init()
589 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; in spi_geni_init()
594 mas->cur_xfer_mode = GENI_GPI_DMA; in spi_geni_init()
596 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n"); in spi_geni_init()
603 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); in spi_geni_init()
607 mas->cur_xfer_mode = GENI_SE_FIFO; in spi_geni_init()
614 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
616 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
619 pm_runtime_put(mas->dev); in spi_geni_init()
630 if (mas->fifo_width_bits % mas->cur_bits_per_word) in geni_byte_per_fifo_word()
631 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, in geni_byte_per_fifo_word()
634 return mas->fifo_width_bits / BITS_PER_BYTE; in geni_byte_per_fifo_word()
639 struct geni_se *se = &mas->se; in geni_spi_handle_tx()
646 if (!mas->cur_xfer) { in geni_spi_handle_tx()
647 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
651 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; in geni_spi_handle_tx()
652 if (mas->tx_rem_bytes < max_bytes) in geni_spi_handle_tx()
653 max_bytes = mas->tx_rem_bytes; in geni_spi_handle_tx()
655 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; in geni_spi_handle_tx()
662 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); in geni_spi_handle_tx()
665 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); in geni_spi_handle_tx()
667 mas->tx_rem_bytes -= max_bytes; in geni_spi_handle_tx()
668 if (!mas->tx_rem_bytes) { in geni_spi_handle_tx()
669 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
677 struct geni_se *se = &mas->se; in geni_spi_handle_rx()
685 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); in geni_spi_handle_rx()
691 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; in geni_spi_handle_rx()
695 if (!mas->cur_xfer) { in geni_spi_handle_rx()
697 readl(se->base + SE_GENI_RX_FIFOn); in geni_spi_handle_rx()
701 if (mas->rx_rem_bytes < rx_bytes) in geni_spi_handle_rx()
702 rx_bytes = mas->rx_rem_bytes; in geni_spi_handle_rx()
704 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; in geni_spi_handle_rx()
711 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); in geni_spi_handle_rx()
712 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); in geni_spi_handle_rx()
716 mas->rx_rem_bytes -= rx_bytes; in geni_spi_handle_rx()
725 struct geni_se *se = &mas->se; in setup_fifo_xfer()
740 spin_lock_irq(&mas->lock); in setup_fifo_xfer()
741 spin_unlock_irq(&mas->lock); in setup_fifo_xfer()
743 if (xfer->bits_per_word != mas->cur_bits_per_word) { in setup_fifo_xfer()
744 spi_setup_word_len(mas, mode, xfer->bits_per_word); in setup_fifo_xfer()
745 mas->cur_bits_per_word = xfer->bits_per_word; in setup_fifo_xfer()
749 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); in setup_fifo_xfer()
753 mas->tx_rem_bytes = 0; in setup_fifo_xfer()
754 mas->rx_rem_bytes = 0; in setup_fifo_xfer()
756 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) in setup_fifo_xfer()
757 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; in setup_fifo_xfer()
759 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); in setup_fifo_xfer()
762 mas->cur_xfer = xfer; in setup_fifo_xfer()
763 if (xfer->tx_buf) { in setup_fifo_xfer()
765 mas->tx_rem_bytes = xfer->len; in setup_fifo_xfer()
766 writel(len, se->base + SE_SPI_TX_TRANS_LEN); in setup_fifo_xfer()
769 if (xfer->rx_buf) { in setup_fifo_xfer()
771 writel(len, se->base + SE_SPI_RX_TRANS_LEN); in setup_fifo_xfer()
772 mas->rx_rem_bytes = xfer->len; in setup_fifo_xfer()
779 spin_lock_irq(&mas->lock); in setup_fifo_xfer()
783 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); in setup_fifo_xfer()
785 spin_unlock_irq(&mas->lock); in setup_fifo_xfer()
795 return -EBUSY; in spi_geni_transfer_one()
798 if (!xfer->len) in spi_geni_transfer_one()
801 if (mas->cur_xfer_mode == GENI_SE_FIFO) { in spi_geni_transfer_one()
802 setup_fifo_xfer(xfer, mas, slv->mode, spi); in spi_geni_transfer_one()
812 struct geni_se *se = &mas->se; in geni_spi_isr()
815 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in geni_spi_isr()
822 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); in geni_spi_isr()
824 spin_lock(&mas->lock); in geni_spi_isr()
833 if (mas->cur_xfer) { in geni_spi_isr()
835 mas->cur_xfer = NULL; in geni_spi_isr()
849 if (mas->tx_rem_bytes) { in geni_spi_isr()
850 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_isr()
851 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", in geni_spi_isr()
852 mas->tx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
854 if (mas->rx_rem_bytes) in geni_spi_isr()
855 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", in geni_spi_isr()
856 mas->rx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
858 complete(&mas->cs_done); in geni_spi_isr()
863 complete(&mas->cancel_done); in geni_spi_isr()
865 complete(&mas->abort_done); in geni_spi_isr()
870 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and in geni_spi_isr()
875 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear in geni_spi_isr()
878 * since they'll re-assert if they're still happening. in geni_spi_isr()
880 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); in geni_spi_isr()
882 spin_unlock(&mas->lock); in geni_spi_isr()
894 struct device *dev = &pdev->dev; in spi_geni_probe()
914 return -ENOMEM; in spi_geni_probe()
918 mas->irq = irq; in spi_geni_probe()
919 mas->dev = dev; in spi_geni_probe()
920 mas->se.dev = dev; in spi_geni_probe()
921 mas->se.wrapper = dev_get_drvdata(dev->parent); in spi_geni_probe()
922 mas->se.base = base; in spi_geni_probe()
923 mas->se.clk = clk; in spi_geni_probe()
925 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); in spi_geni_probe()
929 ret = devm_pm_opp_of_add_table(&pdev->dev); in spi_geni_probe()
930 if (ret && ret != -ENODEV) { in spi_geni_probe()
931 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); in spi_geni_probe()
935 spi->bus_num = -1; in spi_geni_probe()
936 spi->dev.of_node = dev->of_node; in spi_geni_probe()
937 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; in spi_geni_probe()
938 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in spi_geni_probe()
939 spi->num_chipselect = 4; in spi_geni_probe()
940 spi->max_speed_hz = 50000000; in spi_geni_probe()
941 spi->prepare_message = spi_geni_prepare_message; in spi_geni_probe()
942 spi->transfer_one = spi_geni_transfer_one; in spi_geni_probe()
943 spi->can_dma = geni_can_dma; in spi_geni_probe()
944 spi->dma_map_dev = dev->parent; in spi_geni_probe()
945 spi->auto_runtime_pm = true; in spi_geni_probe()
946 spi->handle_err = spi_geni_handle_err; in spi_geni_probe()
947 spi->use_gpio_descriptors = true; in spi_geni_probe()
949 init_completion(&mas->cs_done); in spi_geni_probe()
950 init_completion(&mas->cancel_done); in spi_geni_probe()
951 init_completion(&mas->abort_done); in spi_geni_probe()
952 spin_lock_init(&mas->lock); in spi_geni_probe()
953 pm_runtime_use_autosuspend(&pdev->dev); in spi_geni_probe()
954 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); in spi_geni_probe()
957 ret = geni_icc_get(&mas->se, NULL); in spi_geni_probe()
961 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); in spi_geni_probe()
962 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in spi_geni_probe()
964 ret = geni_icc_set_bw(&mas->se); in spi_geni_probe()
977 if (mas->cur_xfer_mode == GENI_SE_FIFO) in spi_geni_probe()
978 spi->set_cs = spi_geni_set_cs; in spi_geni_probe()
980 ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); in spi_geni_probe()
990 free_irq(mas->irq, spi); in spi_geni_probe()
1008 free_irq(mas->irq, spi); in spi_geni_remove()
1009 pm_runtime_disable(&pdev->dev); in spi_geni_remove()
1022 ret = geni_se_resources_off(&mas->se); in spi_geni_runtime_suspend()
1026 return geni_icc_disable(&mas->se); in spi_geni_runtime_suspend()
1035 ret = geni_icc_enable(&mas->se); in spi_geni_runtime_resume()
1039 ret = geni_se_resources_on(&mas->se); in spi_geni_runtime_resume()
1043 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); in spi_geni_runtime_resume()
1085 { .compatible = "qcom,geni-spi" },