Lines Matching +full:spi +full:- +full:only +full:- +full:use +full:- +full:cs1 +full:- +full:sel
1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
23 #include <linux/dma/imx-dma.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/spi_bitbang.h>
35 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
126 { .compatible = "fsl,imx7ulp-spi", },
134 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
136 if (fsl_lpspi->rx_buf) { \
137 *(type *)fsl_lpspi->rx_buf = val; \
138 fsl_lpspi->rx_buf += sizeof(type); \
147 if (fsl_lpspi->tx_buf) { \
148 val = *(type *)fsl_lpspi->tx_buf; \
149 fsl_lpspi->tx_buf += sizeof(type); \
152 fsl_lpspi->remain -= sizeof(type); \
153 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
166 writel(enable, fsl_lpspi->base + IMX7ULP_IER); in LPSPI_BUF_TX()
175 struct spi_device *spi, in fsl_lpspi_can_dma() argument
180 if (!controller->dma_rx) in fsl_lpspi_can_dma()
183 bytes_per_word = fsl_lpspi_bytes_per_word(transfer->bits_per_word); in fsl_lpspi_can_dma()
203 ret = pm_runtime_resume_and_get(fsl_lpspi->dev); in lpspi_prepare_xfer_hardware()
205 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); in lpspi_prepare_xfer_hardware()
217 pm_runtime_mark_last_busy(fsl_lpspi->dev); in lpspi_unprepare_xfer_hardware()
218 pm_runtime_put_autosuspend(fsl_lpspi->dev); in lpspi_unprepare_xfer_hardware()
228 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff; in fsl_lpspi_write_tx_fifo()
230 while (txfifo_cnt < fsl_lpspi->txfifosize) { in fsl_lpspi_write_tx_fifo()
231 if (!fsl_lpspi->remain) in fsl_lpspi_write_tx_fifo()
233 fsl_lpspi->tx(fsl_lpspi); in fsl_lpspi_write_tx_fifo()
237 if (txfifo_cnt < fsl_lpspi->txfifosize) { in fsl_lpspi_write_tx_fifo()
238 if (!fsl_lpspi->is_slave) { in fsl_lpspi_write_tx_fifo()
239 temp = readl(fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_write_tx_fifo()
241 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_write_tx_fifo()
251 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY)) in fsl_lpspi_read_rx_fifo()
252 fsl_lpspi->rx(fsl_lpspi); in fsl_lpspi_read_rx_fifo()
259 temp |= fsl_lpspi->config.bpw - 1; in fsl_lpspi_set_cmd()
260 temp |= (fsl_lpspi->config.mode & 0x3) << 30; in fsl_lpspi_set_cmd()
261 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24; in fsl_lpspi_set_cmd()
262 if (!fsl_lpspi->is_slave) { in fsl_lpspi_set_cmd()
263 temp |= fsl_lpspi->config.prescale << 27; in fsl_lpspi_set_cmd()
269 if (!fsl_lpspi->usedma) { in fsl_lpspi_set_cmd()
271 if (fsl_lpspi->is_first_byte) in fsl_lpspi_set_cmd()
277 writel(temp, fsl_lpspi->base + IMX7ULP_TCR); in fsl_lpspi_set_cmd()
279 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp); in fsl_lpspi_set_cmd()
286 if (!fsl_lpspi->usedma) in fsl_lpspi_set_watermark()
287 temp = fsl_lpspi->watermark >> 1 | in fsl_lpspi_set_watermark()
288 (fsl_lpspi->watermark >> 1) << 16; in fsl_lpspi_set_watermark()
290 temp = fsl_lpspi->watermark >> 1; in fsl_lpspi_set_watermark()
292 writel(temp, fsl_lpspi->base + IMX7ULP_FCR); in fsl_lpspi_set_watermark()
294 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp); in fsl_lpspi_set_watermark()
299 struct lpspi_config config = fsl_lpspi->config; in fsl_lpspi_set_bitrate()
303 perclk_rate = clk_get_rate(fsl_lpspi->clk_per); in fsl_lpspi_set_bitrate()
306 dev_err(fsl_lpspi->dev, in fsl_lpspi_set_bitrate()
307 "per-clk should be at least two times of transfer speed"); in fsl_lpspi_set_bitrate()
308 return -EINVAL; in fsl_lpspi_set_bitrate()
312 scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2; in fsl_lpspi_set_bitrate()
314 fsl_lpspi->config.prescale = prescale; in fsl_lpspi_set_bitrate()
320 return -EINVAL; in fsl_lpspi_set_bitrate()
323 fsl_lpspi->base + IMX7ULP_CCR); in fsl_lpspi_set_bitrate()
325 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n", in fsl_lpspi_set_bitrate()
339 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) { in fsl_lpspi_dma_configure()
350 return -EINVAL; in fsl_lpspi_dma_configure()
354 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR; in fsl_lpspi_dma_configure()
357 ret = dmaengine_slave_config(controller->dma_tx, &tx); in fsl_lpspi_dma_configure()
359 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n", in fsl_lpspi_dma_configure()
365 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR; in fsl_lpspi_dma_configure()
368 ret = dmaengine_slave_config(controller->dma_rx, &rx); in fsl_lpspi_dma_configure()
370 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n", in fsl_lpspi_dma_configure()
383 if (!fsl_lpspi->is_slave) { in fsl_lpspi_config()
391 if (!fsl_lpspi->is_slave) in fsl_lpspi_config()
395 if (fsl_lpspi->config.mode & SPI_CS_HIGH) in fsl_lpspi_config()
397 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1); in fsl_lpspi_config()
399 temp = readl(fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_config()
401 writel(temp, fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_config()
404 if (fsl_lpspi->usedma) in fsl_lpspi_config()
406 writel(temp, fsl_lpspi->base + IMX7ULP_DER); in fsl_lpspi_config()
412 struct spi_device *spi, in fsl_lpspi_setup_transfer() argument
416 spi_controller_get_devdata(spi->controller); in fsl_lpspi_setup_transfer()
419 return -EINVAL; in fsl_lpspi_setup_transfer()
421 fsl_lpspi->config.mode = spi->mode; in fsl_lpspi_setup_transfer()
422 fsl_lpspi->config.bpw = t->bits_per_word; in fsl_lpspi_setup_transfer()
423 fsl_lpspi->config.speed_hz = t->speed_hz; in fsl_lpspi_setup_transfer()
424 if (fsl_lpspi->is_only_cs1) in fsl_lpspi_setup_transfer()
425 fsl_lpspi->config.chip_select = 1; in fsl_lpspi_setup_transfer()
427 fsl_lpspi->config.chip_select = spi->chip_select; in fsl_lpspi_setup_transfer()
429 if (!fsl_lpspi->config.speed_hz) in fsl_lpspi_setup_transfer()
430 fsl_lpspi->config.speed_hz = spi->max_speed_hz; in fsl_lpspi_setup_transfer()
431 if (!fsl_lpspi->config.bpw) in fsl_lpspi_setup_transfer()
432 fsl_lpspi->config.bpw = spi->bits_per_word; in fsl_lpspi_setup_transfer()
435 if (fsl_lpspi->config.bpw <= 8) { in fsl_lpspi_setup_transfer()
436 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8; in fsl_lpspi_setup_transfer()
437 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8; in fsl_lpspi_setup_transfer()
438 } else if (fsl_lpspi->config.bpw <= 16) { in fsl_lpspi_setup_transfer()
439 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16; in fsl_lpspi_setup_transfer()
440 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16; in fsl_lpspi_setup_transfer()
442 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32; in fsl_lpspi_setup_transfer()
443 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32; in fsl_lpspi_setup_transfer()
446 if (t->len <= fsl_lpspi->txfifosize) in fsl_lpspi_setup_transfer()
447 fsl_lpspi->watermark = t->len; in fsl_lpspi_setup_transfer()
449 fsl_lpspi->watermark = fsl_lpspi->txfifosize; in fsl_lpspi_setup_transfer()
451 if (fsl_lpspi_can_dma(controller, spi, t)) in fsl_lpspi_setup_transfer()
452 fsl_lpspi->usedma = true; in fsl_lpspi_setup_transfer()
454 fsl_lpspi->usedma = false; in fsl_lpspi_setup_transfer()
464 fsl_lpspi->slave_aborted = true; in fsl_lpspi_slave_abort()
465 if (!fsl_lpspi->usedma) in fsl_lpspi_slave_abort()
466 complete(&fsl_lpspi->xfer_done); in fsl_lpspi_slave_abort()
468 complete(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_slave_abort()
469 complete(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_slave_abort()
480 if (fsl_lpspi->is_slave) { in fsl_lpspi_wait_for_completion()
481 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) || in fsl_lpspi_wait_for_completion()
482 fsl_lpspi->slave_aborted) { in fsl_lpspi_wait_for_completion()
483 dev_dbg(fsl_lpspi->dev, "interrupted\n"); in fsl_lpspi_wait_for_completion()
484 return -EINTR; in fsl_lpspi_wait_for_completion()
487 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) { in fsl_lpspi_wait_for_completion()
488 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n"); in fsl_lpspi_wait_for_completion()
489 return -ETIMEDOUT; in fsl_lpspi_wait_for_completion()
500 if (!fsl_lpspi->usedma) { in fsl_lpspi_reset()
507 writel(temp, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_reset()
511 writel(temp, fsl_lpspi->base + IMX7ULP_CR); in fsl_lpspi_reset()
520 complete(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_rx_callback()
527 complete(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_tx_callback()
536 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz; in fsl_lpspi_calculate_timeout()
552 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in fsl_lpspi_dma_transfer()
559 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, in fsl_lpspi_dma_transfer()
560 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in fsl_lpspi_dma_transfer()
563 return -EINVAL; in fsl_lpspi_dma_transfer()
565 desc_rx->callback = fsl_lpspi_dma_rx_callback; in fsl_lpspi_dma_transfer()
566 desc_rx->callback_param = (void *)fsl_lpspi; in fsl_lpspi_dma_transfer()
568 reinit_completion(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_transfer()
569 dma_async_issue_pending(controller->dma_rx); in fsl_lpspi_dma_transfer()
571 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, in fsl_lpspi_dma_transfer()
572 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in fsl_lpspi_dma_transfer()
575 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
576 return -EINVAL; in fsl_lpspi_dma_transfer()
579 desc_tx->callback = fsl_lpspi_dma_tx_callback; in fsl_lpspi_dma_transfer()
580 desc_tx->callback_param = (void *)fsl_lpspi; in fsl_lpspi_dma_transfer()
582 reinit_completion(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_transfer()
583 dma_async_issue_pending(controller->dma_tx); in fsl_lpspi_dma_transfer()
585 fsl_lpspi->slave_aborted = false; in fsl_lpspi_dma_transfer()
587 if (!fsl_lpspi->is_slave) { in fsl_lpspi_dma_transfer()
589 transfer->len); in fsl_lpspi_dma_transfer()
592 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion, in fsl_lpspi_dma_transfer()
595 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n"); in fsl_lpspi_dma_transfer()
596 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
597 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
599 return -ETIMEDOUT; in fsl_lpspi_dma_transfer()
602 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion, in fsl_lpspi_dma_transfer()
605 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n"); in fsl_lpspi_dma_transfer()
606 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
607 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
609 return -ETIMEDOUT; in fsl_lpspi_dma_transfer()
612 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) || in fsl_lpspi_dma_transfer()
613 fsl_lpspi->slave_aborted) { in fsl_lpspi_dma_transfer()
614 dev_dbg(fsl_lpspi->dev, in fsl_lpspi_dma_transfer()
616 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
617 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
619 return -EINTR; in fsl_lpspi_dma_transfer()
622 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) || in fsl_lpspi_dma_transfer()
623 fsl_lpspi->slave_aborted) { in fsl_lpspi_dma_transfer()
624 dev_dbg(fsl_lpspi->dev, in fsl_lpspi_dma_transfer()
626 dmaengine_terminate_all(controller->dma_tx); in fsl_lpspi_dma_transfer()
627 dmaengine_terminate_all(controller->dma_rx); in fsl_lpspi_dma_transfer()
629 return -EINTR; in fsl_lpspi_dma_transfer()
640 if (controller->dma_rx) { in fsl_lpspi_dma_exit()
641 dma_release_channel(controller->dma_rx); in fsl_lpspi_dma_exit()
642 controller->dma_rx = NULL; in fsl_lpspi_dma_exit()
645 if (controller->dma_tx) { in fsl_lpspi_dma_exit()
646 dma_release_channel(controller->dma_tx); in fsl_lpspi_dma_exit()
647 controller->dma_tx = NULL; in fsl_lpspi_dma_exit()
658 controller->dma_tx = dma_request_chan(dev, "tx"); in fsl_lpspi_dma_init()
659 if (IS_ERR(controller->dma_tx)) { in fsl_lpspi_dma_init()
660 ret = PTR_ERR(controller->dma_tx); in fsl_lpspi_dma_init()
662 controller->dma_tx = NULL; in fsl_lpspi_dma_init()
667 controller->dma_rx = dma_request_chan(dev, "rx"); in fsl_lpspi_dma_init()
668 if (IS_ERR(controller->dma_rx)) { in fsl_lpspi_dma_init()
669 ret = PTR_ERR(controller->dma_rx); in fsl_lpspi_dma_init()
671 controller->dma_rx = NULL; in fsl_lpspi_dma_init()
675 init_completion(&fsl_lpspi->dma_rx_completion); in fsl_lpspi_dma_init()
676 init_completion(&fsl_lpspi->dma_tx_completion); in fsl_lpspi_dma_init()
677 controller->can_dma = fsl_lpspi_can_dma; in fsl_lpspi_dma_init()
678 controller->max_dma_len = FSL_LPSPI_MAX_EDMA_BYTES; in fsl_lpspi_dma_init()
693 fsl_lpspi->tx_buf = t->tx_buf; in fsl_lpspi_pio_transfer()
694 fsl_lpspi->rx_buf = t->rx_buf; in fsl_lpspi_pio_transfer()
695 fsl_lpspi->remain = t->len; in fsl_lpspi_pio_transfer()
697 reinit_completion(&fsl_lpspi->xfer_done); in fsl_lpspi_pio_transfer()
698 fsl_lpspi->slave_aborted = false; in fsl_lpspi_pio_transfer()
712 struct spi_device *spi, in fsl_lpspi_transfer_one() argument
719 fsl_lpspi->is_first_byte = true; in fsl_lpspi_transfer_one()
720 ret = fsl_lpspi_setup_transfer(controller, spi, t); in fsl_lpspi_transfer_one()
725 fsl_lpspi->is_first_byte = false; in fsl_lpspi_transfer_one()
727 if (fsl_lpspi->usedma) in fsl_lpspi_transfer_one()
742 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER); in fsl_lpspi_isr()
744 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
754 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) { in fsl_lpspi_isr()
755 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
761 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); in fsl_lpspi_isr()
762 complete(&fsl_lpspi->xfer_done); in fsl_lpspi_isr()
778 ret = clk_prepare_enable(fsl_lpspi->clk_per); in fsl_lpspi_runtime_resume()
782 ret = clk_prepare_enable(fsl_lpspi->clk_ipg); in fsl_lpspi_runtime_resume()
784 clk_disable_unprepare(fsl_lpspi->clk_per); in fsl_lpspi_runtime_resume()
798 clk_disable_unprepare(fsl_lpspi->clk_per); in fsl_lpspi_runtime_suspend()
799 clk_disable_unprepare(fsl_lpspi->clk_ipg); in fsl_lpspi_runtime_suspend()
807 struct device *dev = fsl_lpspi->dev; in fsl_lpspi_init_rpm()
825 is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave"); in fsl_lpspi_probe()
827 controller = spi_alloc_slave(&pdev->dev, in fsl_lpspi_probe()
830 controller = spi_alloc_master(&pdev->dev, in fsl_lpspi_probe()
834 return -ENOMEM; in fsl_lpspi_probe()
839 fsl_lpspi->dev = &pdev->dev; in fsl_lpspi_probe()
840 fsl_lpspi->is_slave = is_slave; in fsl_lpspi_probe()
841 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node, in fsl_lpspi_probe()
842 "fsl,spi-only-use-cs1-sel"); in fsl_lpspi_probe()
844 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); in fsl_lpspi_probe()
845 controller->transfer_one = fsl_lpspi_transfer_one; in fsl_lpspi_probe()
846 controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; in fsl_lpspi_probe()
847 controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; in fsl_lpspi_probe()
848 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; in fsl_lpspi_probe()
849 controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; in fsl_lpspi_probe()
850 controller->dev.of_node = pdev->dev.of_node; in fsl_lpspi_probe()
851 controller->bus_num = pdev->id; in fsl_lpspi_probe()
852 controller->slave_abort = fsl_lpspi_slave_abort; in fsl_lpspi_probe()
853 if (!fsl_lpspi->is_slave) in fsl_lpspi_probe()
854 controller->use_gpio_descriptors = true; in fsl_lpspi_probe()
856 init_completion(&fsl_lpspi->xfer_done); in fsl_lpspi_probe()
858 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in fsl_lpspi_probe()
859 if (IS_ERR(fsl_lpspi->base)) { in fsl_lpspi_probe()
860 ret = PTR_ERR(fsl_lpspi->base); in fsl_lpspi_probe()
863 fsl_lpspi->base_phys = res->start; in fsl_lpspi_probe()
871 ret = devm_request_irq(&pdev->dev, irq, fsl_lpspi_isr, 0, in fsl_lpspi_probe()
872 dev_name(&pdev->dev), fsl_lpspi); in fsl_lpspi_probe()
874 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in fsl_lpspi_probe()
878 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per"); in fsl_lpspi_probe()
879 if (IS_ERR(fsl_lpspi->clk_per)) { in fsl_lpspi_probe()
880 ret = PTR_ERR(fsl_lpspi->clk_per); in fsl_lpspi_probe()
884 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in fsl_lpspi_probe()
885 if (IS_ERR(fsl_lpspi->clk_ipg)) { in fsl_lpspi_probe()
886 ret = PTR_ERR(fsl_lpspi->clk_ipg); in fsl_lpspi_probe()
895 ret = pm_runtime_get_sync(fsl_lpspi->dev); in fsl_lpspi_probe()
897 dev_err(fsl_lpspi->dev, "failed to enable clock\n"); in fsl_lpspi_probe()
901 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM); in fsl_lpspi_probe()
902 fsl_lpspi->txfifosize = 1 << (temp & 0x0f); in fsl_lpspi_probe()
903 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f); in fsl_lpspi_probe()
905 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller); in fsl_lpspi_probe()
906 if (ret == -EPROBE_DEFER) in fsl_lpspi_probe()
910 dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret); in fsl_lpspi_probe()
912 ret = devm_spi_register_controller(&pdev->dev, controller); in fsl_lpspi_probe()
914 dev_err_probe(&pdev->dev, ret, "spi_register_controller error\n"); in fsl_lpspi_probe()
918 pm_runtime_mark_last_busy(fsl_lpspi->dev); in fsl_lpspi_probe()
919 pm_runtime_put_autosuspend(fsl_lpspi->dev); in fsl_lpspi_probe()
926 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev); in fsl_lpspi_probe()
927 pm_runtime_put_sync(fsl_lpspi->dev); in fsl_lpspi_probe()
928 pm_runtime_disable(fsl_lpspi->dev); in fsl_lpspi_probe()
943 pm_runtime_disable(fsl_lpspi->dev); in fsl_lpspi_remove()