1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2010-2011 Mika Westerberg
7  * Explicit FIFO handling code was inspired by amba-pl022 driver.
9  * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
30 #include <linux/platform_data/dma-ep93xx.h>
31 #include <linux/platform_data/spi-ep93xx.h>
65 /* maximum depth of RX/TX FIFO */
69  * struct ep93xx_spi - EP93xx SPI controller structure
74  * @rx: current byte in transfer to receive
75  * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
77  * @dma_rx: RX DMA channel
79  * @dma_rx_data: RX parameters passed to the DMA engine
81  * @rx_sgt: sg table for RX transfers
83  * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
91 	size_t				rx;  member
103 #define bits_per_word_to_dss(bpw)	((bpw) - 1)
106  * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
109  * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
116 	unsigned long spi_clk_rate = clk_get_rate(espi->clk);  in ep93xx_spi_calc_divisors()
123 	rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);  in ep93xx_spi_calc_divisors()
143 	return -EINVAL;  in ep93xx_spi_calc_divisors()
151 	u8 dss = bits_per_word_to_dss(xfer->bits_per_word);  in ep93xx_spi_chip_setup()
157 	err = ep93xx_spi_calc_divisors(master, xfer->speed_hz,  in ep93xx_spi_chip_setup()
163 	if (spi->mode & SPI_CPOL)  in ep93xx_spi_chip_setup()
165 	if (spi->mode & SPI_CPHA)  in ep93xx_spi_chip_setup()
169 	dev_dbg(&master->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",  in ep93xx_spi_chip_setup()
170 		spi->mode, div_cpsr, div_scr, dss);  in ep93xx_spi_chip_setup()
171 	dev_dbg(&master->dev, "setup: cr0 %#x\n", cr0);  in ep93xx_spi_chip_setup()
173 	writel(div_cpsr, espi->mmio + SSPCPSR);  in ep93xx_spi_chip_setup()
174 	writel(cr0, espi->mmio + SSPCR0);  in ep93xx_spi_chip_setup()
182 	struct spi_transfer *xfer = master->cur_msg->state;  in ep93xx_do_write()
185 	if (xfer->bits_per_word > 8) {  in ep93xx_do_write()
186 		if (xfer->tx_buf)  in ep93xx_do_write()
187 			val = ((u16 *)xfer->tx_buf)[espi->tx];  in ep93xx_do_write()
188 		espi->tx += 2;  in ep93xx_do_write()
190 		if (xfer->tx_buf)  in ep93xx_do_write()
191 			val = ((u8 *)xfer->tx_buf)[espi->tx];  in ep93xx_do_write()
192 		espi->tx += 1;  in ep93xx_do_write()
194 	writel(val, espi->mmio + SSPDR);  in ep93xx_do_write()
200 	struct spi_transfer *xfer = master->cur_msg->state;  in ep93xx_do_read()
203 	val = readl(espi->mmio + SSPDR);  in ep93xx_do_read()
204 	if (xfer->bits_per_word > 8) {  in ep93xx_do_read()
205 		if (xfer->rx_buf)  in ep93xx_do_read()
206 			((u16 *)xfer->rx_buf)[espi->rx] = val;  in ep93xx_do_read()
207 		espi->rx += 2;  in ep93xx_do_read()
209 		if (xfer->rx_buf)  in ep93xx_do_read()
210 			((u8 *)xfer->rx_buf)[espi->rx] = val;  in ep93xx_do_read()
211 		espi->rx += 1;  in ep93xx_do_read()
216  * ep93xx_spi_read_write() - perform next RX/TX transfer
219  * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
221  * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
223  * When this function is finished, RX FIFO should be empty and TX FIFO should be
229 	struct spi_transfer *xfer = master->cur_msg->state;  in ep93xx_spi_read_write()
231 	/* read as long as RX FIFO has frames in it */  in ep93xx_spi_read_write()
232 	while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) {  in ep93xx_spi_read_write()
234 		espi->fifo_level--;  in ep93xx_spi_read_write()
238 	while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < xfer->len) {  in ep93xx_spi_read_write()
240 		espi->fifo_level++;  in ep93xx_spi_read_write()
243 	if (espi->rx == xfer->len)  in ep93xx_spi_read_write()
246 	return -EINPROGRESS;  in ep93xx_spi_read_write()
263  * ep93xx_spi_dma_prepare() - prepares a DMA transfer
276 	struct spi_transfer *xfer = master->cur_msg->state;  in ep93xx_spi_dma_prepare()
279 	struct dma_slave_config conf;  in ep93xx_spi_dma_prepare()  local
284 	size_t len = xfer->len;  in ep93xx_spi_dma_prepare()
287 	if (xfer->bits_per_word > 8)  in ep93xx_spi_dma_prepare()
292 	memset(&conf, 0, sizeof(conf));  in ep93xx_spi_dma_prepare()
293 	conf.direction = ep93xx_dma_data_to_trans_dir(dir);  in ep93xx_spi_dma_prepare()
296 		chan = espi->dma_rx;  in ep93xx_spi_dma_prepare()
297 		buf = xfer->rx_buf;  in ep93xx_spi_dma_prepare()
298 		sgt = &espi->rx_sgt;  in ep93xx_spi_dma_prepare()
300 		conf.src_addr = espi->sspdr_phys;  in ep93xx_spi_dma_prepare()
301 		conf.src_addr_width = buswidth;  in ep93xx_spi_dma_prepare()
303 		chan = espi->dma_tx;  in ep93xx_spi_dma_prepare()
304 		buf = xfer->tx_buf;  in ep93xx_spi_dma_prepare()
305 		sgt = &espi->tx_sgt;  in ep93xx_spi_dma_prepare()
307 		conf.dst_addr = espi->sspdr_phys;  in ep93xx_spi_dma_prepare()
308 		conf.dst_addr_width = buswidth;  in ep93xx_spi_dma_prepare()
311 	ret = dmaengine_slave_config(chan, &conf);  in ep93xx_spi_dma_prepare()
317 	 * because we are using @espi->zeropage to provide a zero RX buffer  in ep93xx_spi_dma_prepare()
321 	 * needed. Otherwise we will re-use the current one. Eventually the  in ep93xx_spi_dma_prepare()
326 	if (nents != sgt->nents) {  in ep93xx_spi_dma_prepare()
335 	for_each_sg(sgt->sgl, sg, sgt->nents, i) {  in ep93xx_spi_dma_prepare()
342 			sg_set_page(sg, virt_to_page(espi->zeropage),  in ep93xx_spi_dma_prepare()
347 		len -= bytes;  in ep93xx_spi_dma_prepare()
351 		dev_warn(&master->dev, "len = %zu expected 0!\n", len);  in ep93xx_spi_dma_prepare()
352 		return ERR_PTR(-EINVAL);  in ep93xx_spi_dma_prepare()
355 	nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);  in ep93xx_spi_dma_prepare()
357 		return ERR_PTR(-ENOMEM);  in ep93xx_spi_dma_prepare()
359 	txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, conf.direction,  in ep93xx_spi_dma_prepare()
362 		dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);  in ep93xx_spi_dma_prepare()
363 		return ERR_PTR(-ENOMEM);  in ep93xx_spi_dma_prepare()
369  * ep93xx_spi_dma_finish() - finishes with a DMA transfer
384 		chan = espi->dma_rx;  in ep93xx_spi_dma_finish()
385 		sgt = &espi->rx_sgt;  in ep93xx_spi_dma_finish()
387 		chan = espi->dma_tx;  in ep93xx_spi_dma_finish()
388 		sgt = &espi->tx_sgt;  in ep93xx_spi_dma_finish()
391 	dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);  in ep93xx_spi_dma_finish()
411 		dev_err(&master->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));  in ep93xx_spi_dma_transfer()
418 		dev_err(&master->dev, "DMA TX failed: %ld\n", PTR_ERR(txd));  in ep93xx_spi_dma_transfer()
422 	/* We are ready when RX is done */  in ep93xx_spi_dma_transfer()
423 	rxd->callback = ep93xx_spi_dma_callback;  in ep93xx_spi_dma_transfer()
424 	rxd->callback_param = master;  in ep93xx_spi_dma_transfer()
430 	dma_async_issue_pending(espi->dma_rx);  in ep93xx_spi_dma_transfer()
431 	dma_async_issue_pending(espi->dma_tx);  in ep93xx_spi_dma_transfer()
447 	if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) {  in ep93xx_spi_interrupt()
449 		writel(0, espi->mmio + SSPICR);  in ep93xx_spi_interrupt()
450 		dev_warn(&master->dev,  in ep93xx_spi_interrupt()
452 		master->cur_msg->status = -EIO;  in ep93xx_spi_interrupt()
455 		 * Interrupt is either RX (RIS) or TX (TIS). For both cases we  in ep93xx_spi_interrupt()
471 	 * any post-processing of the message.  in ep93xx_spi_interrupt()
473 	val = readl(espi->mmio + SSPCR1);  in ep93xx_spi_interrupt()
475 	writel(val, espi->mmio + SSPCR1);  in ep93xx_spi_interrupt()
492 		dev_err(&master->dev, "failed to setup chip for transfer\n");  in ep93xx_spi_transfer_one()
496 	master->cur_msg->state = xfer;  in ep93xx_spi_transfer_one()
497 	espi->rx = 0;  in ep93xx_spi_transfer_one()
498 	espi->tx = 0;  in ep93xx_spi_transfer_one()
505 	if (espi->dma_rx && xfer->len > SPI_FIFO_SIZE)  in ep93xx_spi_transfer_one()
511 	val = readl(espi->mmio + SSPCR1);  in ep93xx_spi_transfer_one()
513 	writel(val, espi->mmio + SSPCR1);  in ep93xx_spi_transfer_one()
526 	 * Just to be sure: flush any data from RX FIFO.  in ep93xx_spi_prepare_message()
529 	while (readl(espi->mmio + SSPSR) & SSPSR_RNE) {  in ep93xx_spi_prepare_message()
531 			dev_warn(&master->dev,  in ep93xx_spi_prepare_message()
532 				 "timeout while flushing RX FIFO\n");  in ep93xx_spi_prepare_message()
533 			return -ETIMEDOUT;  in ep93xx_spi_prepare_message()
535 		readl(espi->mmio + SSPDR);  in ep93xx_spi_prepare_message()
540 	 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.  in ep93xx_spi_prepare_message()
542 	espi->fifo_level = 0;  in ep93xx_spi_prepare_message()
553 	ret = clk_prepare_enable(espi->clk);  in ep93xx_spi_prepare_hardware()
557 	val = readl(espi->mmio + SSPCR1);  in ep93xx_spi_prepare_hardware()
559 	writel(val, espi->mmio + SSPCR1);  in ep93xx_spi_prepare_hardware()
569 	val = readl(espi->mmio + SSPCR1);  in ep93xx_spi_unprepare_hardware()
571 	writel(val, espi->mmio + SSPCR1);  in ep93xx_spi_unprepare_hardware()
573 	clk_disable_unprepare(espi->clk);  in ep93xx_spi_unprepare_hardware()
583 	chan->private = filter_param;  in ep93xx_spi_dma_filter()
592 	espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);  in ep93xx_spi_setup_dma()
593 	if (!espi->zeropage)  in ep93xx_spi_setup_dma()
594 		return -ENOMEM;  in ep93xx_spi_setup_dma()
599 	espi->dma_rx_data.port = EP93XX_DMA_SSP;  in ep93xx_spi_setup_dma()
600 	espi->dma_rx_data.direction = DMA_DEV_TO_MEM;  in ep93xx_spi_setup_dma()
601 	espi->dma_rx_data.name = "ep93xx-spi-rx";  in ep93xx_spi_setup_dma()
603 	espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,  in ep93xx_spi_setup_dma()
604 					   &espi->dma_rx_data);  in ep93xx_spi_setup_dma()
605 	if (!espi->dma_rx) {  in ep93xx_spi_setup_dma()
606 		ret = -ENODEV;  in ep93xx_spi_setup_dma()
610 	espi->dma_tx_data.port = EP93XX_DMA_SSP;  in ep93xx_spi_setup_dma()
611 	espi->dma_tx_data.direction = DMA_MEM_TO_DEV;  in ep93xx_spi_setup_dma()
612 	espi->dma_tx_data.name = "ep93xx-spi-tx";  in ep93xx_spi_setup_dma()
614 	espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,  in ep93xx_spi_setup_dma()
615 					   &espi->dma_tx_data);  in ep93xx_spi_setup_dma()
616 	if (!espi->dma_tx) {  in ep93xx_spi_setup_dma()
617 		ret = -ENODEV;  in ep93xx_spi_setup_dma()
624 	dma_release_channel(espi->dma_rx);  in ep93xx_spi_setup_dma()
625 	espi->dma_rx = NULL;  in ep93xx_spi_setup_dma()
627 	free_page((unsigned long)espi->zeropage);  in ep93xx_spi_setup_dma()
634 	if (espi->dma_rx) {  in ep93xx_spi_release_dma()
635 		dma_release_channel(espi->dma_rx);  in ep93xx_spi_release_dma()
636 		sg_free_table(&espi->rx_sgt);  in ep93xx_spi_release_dma()
638 	if (espi->dma_tx) {  in ep93xx_spi_release_dma()
639 		dma_release_channel(espi->dma_tx);  in ep93xx_spi_release_dma()
640 		sg_free_table(&espi->tx_sgt);  in ep93xx_spi_release_dma()
643 	if (espi->zeropage)  in ep93xx_spi_release_dma()
644 		free_page((unsigned long)espi->zeropage);  in ep93xx_spi_release_dma()
656 	info = dev_get_platdata(&pdev->dev);  in ep93xx_spi_probe()
658 		dev_err(&pdev->dev, "missing platform data\n");  in ep93xx_spi_probe()
659 		return -EINVAL;  in ep93xx_spi_probe()
664 		return -EBUSY;  in ep93xx_spi_probe()
668 		dev_err(&pdev->dev, "unable to get iomem resource\n");  in ep93xx_spi_probe()
669 		return -ENODEV;  in ep93xx_spi_probe()
672 	master = spi_alloc_master(&pdev->dev, sizeof(*espi));  in ep93xx_spi_probe()
674 		return -ENOMEM;  in ep93xx_spi_probe()
676 	master->use_gpio_descriptors = true;  in ep93xx_spi_probe()
677 	master->prepare_transfer_hardware = ep93xx_spi_prepare_hardware;  in ep93xx_spi_probe()
678 	master->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware;  in ep93xx_spi_probe()
679 	master->prepare_message = ep93xx_spi_prepare_message;  in ep93xx_spi_probe()
680 	master->transfer_one = ep93xx_spi_transfer_one;  in ep93xx_spi_probe()
681 	master->bus_num = pdev->id;  in ep93xx_spi_probe()
682 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;  in ep93xx_spi_probe()
683 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);  in ep93xx_spi_probe()
688 	master->num_chipselect = 0;  in ep93xx_spi_probe()
694 	espi->clk = devm_clk_get(&pdev->dev, NULL);  in ep93xx_spi_probe()
695 	if (IS_ERR(espi->clk)) {  in ep93xx_spi_probe()
696 		dev_err(&pdev->dev, "unable to get spi clock\n");  in ep93xx_spi_probe()
697 		error = PTR_ERR(espi->clk);  in ep93xx_spi_probe()
705 	master->max_speed_hz = clk_get_rate(espi->clk) / 2;  in ep93xx_spi_probe()
706 	master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);  in ep93xx_spi_probe()
708 	espi->sspdr_phys = res->start + SSPDR;  in ep93xx_spi_probe()
710 	espi->mmio = devm_ioremap_resource(&pdev->dev, res);  in ep93xx_spi_probe()
711 	if (IS_ERR(espi->mmio)) {  in ep93xx_spi_probe()
712 		error = PTR_ERR(espi->mmio);  in ep93xx_spi_probe()
716 	error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,  in ep93xx_spi_probe()
717 				0, "ep93xx-spi", master);  in ep93xx_spi_probe()
719 		dev_err(&pdev->dev, "failed to request irq\n");  in ep93xx_spi_probe()
723 	if (info->use_dma && ep93xx_spi_setup_dma(espi))  in ep93xx_spi_probe()
724 		dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");  in ep93xx_spi_probe()
727 	writel(0, espi->mmio + SSPCR1);  in ep93xx_spi_probe()
729 	error = devm_spi_register_master(&pdev->dev, master);  in ep93xx_spi_probe()
731 		dev_err(&pdev->dev, "failed to register SPI master\n");  in ep93xx_spi_probe()
735 	dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",  in ep93xx_spi_probe()
736 		 (unsigned long)res->start, irq);  in ep93xx_spi_probe()
760 		.name	= "ep93xx-spi",
770 MODULE_ALIAS("platform:ep93xx-spi");