224 #define spi_readl(port, reg) \  macro
354 		mr = spi_readl(as, MR);  in cs_activate()
362 			csr = spi_readl(as, CSR0 + 4 * i);  in cs_activate()
368 		mr = spi_readl(as, MR);  in cs_activate()
389 	mr = spi_readl(as, MR);  in cs_deactivate()
583 	spi_readl(as, RDR);  in atmel_spi_next_xfer_single()
584 	while (spi_readl(as, SR) & SPI_BIT(RDRF)) {  in atmel_spi_next_xfer_single()
585 		spi_readl(as, RDR);  in atmel_spi_next_xfer_single()
627 	while (spi_readl(as, FLR))  in atmel_spi_next_xfer_fifo()
631 	fifomr = spi_readl(as, FMR);  in atmel_spi_next_xfer_fifo()
635 	(void)spi_readl(as, SR);  in atmel_spi_next_xfer_fifo()
835 	csr = spi_readl(as, CSR0 + 4 * chip_select);  in atmel_spi_set_xfer_speed()
972 		*rxp16 = spi_readl(as, RDR);  in atmel_spi_pump_single_data()
975 		*rxp = spi_readl(as, RDR);  in atmel_spi_pump_single_data()
990 	u32 fifolr = spi_readl(as, FLR);  in atmel_spi_pump_fifo_data()
1013 		rd = spi_readl(as, RDR);  in atmel_spi_pump_fifo_data()
1048 	imr = spi_readl(as, IMR);  in atmel_spi_pio_interrupt()
1049 	status = spi_readl(as, SR);  in atmel_spi_pio_interrupt()
1070 		spi_readl(as, SR);  in atmel_spi_pio_interrupt()
1105 	imr = spi_readl(as, IMR);  in atmel_spi_pdc_interrupt()
1106 	status = spi_readl(as, SR);  in atmel_spi_pdc_interrupt()
1117 		spi_readl(as, SR);  in atmel_spi_pdc_interrupt()
1351 				spi_readl(as, TCR), spi_readl(as, RCR));  in atmel_spi_one_transfer()
1362 				if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))  in atmel_spi_one_transfer()
1367 			while (spi_readl(as, SR) & SPI_BIT(RDRF))  in atmel_spi_one_transfer()
1368 				spi_readl(as, RDR);  in atmel_spi_one_transfer()
1371 			spi_readl(as, SR);  in atmel_spi_one_transfer()
1401 	return spi_readl(as, VERSION) & 0x00000fff;  in atmel_get_version()
1623 	spi_readl(as, SR);  in atmel_spi_remove()