174 	int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);  member
351 	swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val);  in qcom_swrm_cmd_fifo_wr_cmd()
391 	swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);  in qcom_swrm_cmd_fifo_rd_cmd()
407 				swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD,  in qcom_swrm_cmd_fifo_rd_cmd()
409 				swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val);  in qcom_swrm_cmd_fifo_rd_cmd()
601 				swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask);  in qcom_swrm_irq_handler()
620 				swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);  in qcom_swrm_irq_handler()
627 				swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);  in qcom_swrm_irq_handler()
634 				swrm->reg_write(swrm,  in qcom_swrm_irq_handler()
643 				swrm->reg_write(swrm,  in qcom_swrm_irq_handler()
663 		swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts);  in qcom_swrm_irq_handler()
682 	ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);  in qcom_swrm_init()
685 	ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);  in qcom_swrm_init()
689 	ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,  in qcom_swrm_init()
695 	ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);  in qcom_swrm_init()
697 	ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);  in qcom_swrm_init()
701 		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,  in qcom_swrm_init()
705 		ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,  in qcom_swrm_init()
710 	ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,  in qcom_swrm_init()
716 		ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,  in qcom_swrm_init()
772 	return ctrl->reg_write(ctrl, reg, val);  in qcom_swrm_pre_bank_switch()
781 	return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),  in qcom_swrm_port_params()
802 	ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
809 		ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
817 		ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
826 		ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
830 		ret = ctrl->reg_write(ctrl, reg, value);  in qcom_swrm_transport_params()
838 		ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);  in qcom_swrm_transport_params()
860 	return ctrl->reg_write(ctrl, reg, val);  in qcom_swrm_port_enable()
1321 		ctrl->reg_write = qcom_swrm_ahb_reg_write;
1327 		ctrl->reg_write = qcom_swrm_cpu_reg_write;
1505 		ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1522 		ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1523 		ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
1527 		ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1528 		ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1550 		ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1551 		ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);