Lines Matching +full:pcfg +full:-
1 // SPDX-License-Identifier: GPL-2.0
87 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
88 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
89 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
90 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
91 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
92 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
93 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
208 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_read()
228 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_write()
248 *val = readl(ctrl->mmio + reg); in qcom_swrm_cpu_reg_read()
255 writel(val, ctrl->mmio + reg); in qcom_swrm_cpu_reg_write()
284 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in swrm_wait_for_rd_fifo_avail()
292 } while (fifo_retry_count--); in swrm_wait_for_rd_fifo_avail()
295 dev_err_ratelimited(swrm->dev, "%s err read underflow\n", __func__); in swrm_wait_for_rd_fifo_avail()
296 return -EIO; in swrm_wait_for_rd_fifo_avail()
309 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in swrm_wait_for_wr_fifo_avail()
313 if (fifo_outstanding_cmds < swrm->wr_fifo_depth) in swrm_wait_for_wr_fifo_avail()
317 } while (fifo_retry_count--); in swrm_wait_for_wr_fifo_avail()
319 if (fifo_outstanding_cmds == swrm->wr_fifo_depth) { in swrm_wait_for_wr_fifo_avail()
320 dev_err_ratelimited(swrm->dev, "%s err write overflow\n", __func__); in swrm_wait_for_wr_fifo_avail()
321 return -EIO; in swrm_wait_for_wr_fifo_avail()
340 val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, in qcom_swrm_cmd_fifo_wr_cmd()
348 reinit_completion(&swrm->broadcast); in qcom_swrm_cmd_fifo_wr_cmd()
351 swrm->reg_write(swrm, SWRM_CMD_FIFO_WR_CMD, val); in qcom_swrm_cmd_fifo_wr_cmd()
354 if (swrm->version <= 0x01030000) in qcom_swrm_cmd_fifo_wr_cmd()
362 ret = wait_for_completion_timeout(&swrm->broadcast, in qcom_swrm_cmd_fifo_wr_cmd()
381 val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); in qcom_swrm_cmd_fifo_rd_cmd()
391 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); in qcom_swrm_cmd_fifo_rd_cmd()
399 swrm->reg_read(swrm, SWRM_CMD_FIFO_RD_FIFO_ADDR, &cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
403 if (cmd_id != swrm->rcmd_id) { in qcom_swrm_cmd_fifo_rd_cmd()
404 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { in qcom_swrm_cmd_fifo_rd_cmd()
407 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, in qcom_swrm_cmd_fifo_rd_cmd()
409 swrm->reg_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); in qcom_swrm_cmd_fifo_rd_cmd()
418 dev_err(swrm->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ in qcom_swrm_cmd_fifo_rd_cmd()
420 reg_addr, swrm->rcmd_id, dev_addr, cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
430 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_alert_slave_dev_num()
436 ctrl->status[dev_num] = status; in qcom_swrm_get_alert_slave_dev_num()
441 return -EINVAL; in qcom_swrm_get_alert_slave_dev_num()
449 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_device_status()
450 ctrl->slave_status = val; in qcom_swrm_get_device_status()
457 ctrl->status[i] = s; in qcom_swrm_get_device_status()
467 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); in qcom_swrm_set_slave_dev_num()
473 slave->dev_num = devnum; in qcom_swrm_set_slave_dev_num()
474 mutex_lock(&bus->bus_lock); in qcom_swrm_set_slave_dev_num()
475 set_bit(devnum, bus->assigned); in qcom_swrm_set_slave_dev_num()
476 mutex_unlock(&bus->bus_lock); in qcom_swrm_set_slave_dev_num()
493 if (!ctrl->status[i]) in qcom_swrm_enumerate()
496 /*SCP_Devid5 - Devid 4*/ in qcom_swrm_enumerate()
497 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); in qcom_swrm_enumerate()
499 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ in qcom_swrm_enumerate()
500 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); in qcom_swrm_enumerate()
512 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { in qcom_swrm_enumerate()
526 complete(&ctrl->enumeration); in qcom_swrm_enumerate()
535 ret = pm_runtime_resume_and_get(swrm->dev); in qcom_swrm_wake_irq_handler()
536 if (ret < 0 && ret != -EACCES) { in qcom_swrm_wake_irq_handler()
537 dev_err_ratelimited(swrm->dev, in qcom_swrm_wake_irq_handler()
543 if (swrm->wake_irq > 0) { in qcom_swrm_wake_irq_handler()
544 if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq))) in qcom_swrm_wake_irq_handler()
545 disable_irq_nosync(swrm->wake_irq); in qcom_swrm_wake_irq_handler()
548 pm_runtime_mark_last_busy(swrm->dev); in qcom_swrm_wake_irq_handler()
549 pm_runtime_put_autosuspend(swrm->dev); in qcom_swrm_wake_irq_handler()
561 clk_prepare_enable(swrm->hclk); in qcom_swrm_irq_handler()
563 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); in qcom_swrm_irq_handler()
564 intr_sts_masked = intr_sts & swrm->intr_mask; in qcom_swrm_irq_handler()
576 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
579 sdw_handle_slave_status(&swrm->bus, swrm->status); in qcom_swrm_irq_handler()
585 dev_dbg_ratelimited(swrm->dev, "SWR new slave attached\n"); in qcom_swrm_irq_handler()
586 swrm->reg_read(swrm, SWRM_MCP_SLV_STATUS, &slave_status); in qcom_swrm_irq_handler()
587 if (swrm->slave_status == slave_status) { in qcom_swrm_irq_handler()
588 dev_dbg(swrm->dev, "Slave status not changed %x\n", in qcom_swrm_irq_handler()
592 qcom_swrm_enumerate(&swrm->bus); in qcom_swrm_irq_handler()
593 sdw_handle_slave_status(&swrm->bus, swrm->status); in qcom_swrm_irq_handler()
597 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
600 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; in qcom_swrm_irq_handler()
601 swrm->reg_write(swrm, SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); in qcom_swrm_irq_handler()
604 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in qcom_swrm_irq_handler()
605 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
610 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in qcom_swrm_irq_handler()
611 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
616 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in qcom_swrm_irq_handler()
617 dev_err(swrm->dev, in qcom_swrm_irq_handler()
620 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
623 swrm->reg_read(swrm, SWRM_CMD_FIFO_STATUS, &value); in qcom_swrm_irq_handler()
624 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
627 swrm->reg_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
630 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
633 swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; in qcom_swrm_irq_handler()
634 swrm->reg_write(swrm, in qcom_swrm_irq_handler()
635 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); in qcom_swrm_irq_handler()
638 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
641 swrm->intr_mask &= in qcom_swrm_irq_handler()
643 swrm->reg_write(swrm, in qcom_swrm_irq_handler()
644 SWRM_INTERRUPT_CPU_EN, swrm->intr_mask); in qcom_swrm_irq_handler()
647 complete(&swrm->broadcast); in qcom_swrm_irq_handler()
656 dev_err_ratelimited(swrm->dev, in qcom_swrm_irq_handler()
663 swrm->reg_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts); in qcom_swrm_irq_handler()
664 swrm->reg_read(swrm, SWRM_INTERRUPT_STATUS, &intr_sts); in qcom_swrm_irq_handler()
665 intr_sts_masked = intr_sts & swrm->intr_mask; in qcom_swrm_irq_handler()
668 clk_disable_unprepare(swrm->hclk); in qcom_swrm_irq_handler()
677 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); in qcom_swrm_init()
678 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); in qcom_swrm_init()
680 reset_control_reset(ctrl->audio_cgcr); in qcom_swrm_init()
682 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); in qcom_swrm_init()
685 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); in qcom_swrm_init()
687 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; in qcom_swrm_init()
689 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, in qcom_swrm_init()
693 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); in qcom_swrm_init()
695 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); in qcom_swrm_init()
697 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); in qcom_swrm_init()
699 if (ctrl->version > 0x01050001) { in qcom_swrm_init()
701 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
705 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
710 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
715 if (ctrl->mmio) { in qcom_swrm_init()
716 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, in qcom_swrm_init()
719 ctrl->slave_status = 0; in qcom_swrm_init()
720 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_init()
721 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); in qcom_swrm_init()
722 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); in qcom_swrm_init()
733 if (msg->flags == SDW_MSG_FLAG_READ) { in qcom_swrm_xfer_msg()
734 for (i = 0; i < msg->len;) { in qcom_swrm_xfer_msg()
735 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) in qcom_swrm_xfer_msg()
736 len = msg->len - i; in qcom_swrm_xfer_msg()
740 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, in qcom_swrm_xfer_msg()
741 msg->addr + i, len, in qcom_swrm_xfer_msg()
742 &msg->buf[i]); in qcom_swrm_xfer_msg()
748 } else if (msg->flags == SDW_MSG_FLAG_WRITE) { in qcom_swrm_xfer_msg()
749 for (i = 0; i < msg->len; i++) { in qcom_swrm_xfer_msg()
750 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], in qcom_swrm_xfer_msg()
751 msg->dev_num, in qcom_swrm_xfer_msg()
752 msg->addr + i); in qcom_swrm_xfer_msg()
763 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); in qcom_swrm_pre_bank_switch()
767 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_pre_bank_switch()
769 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
770 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
772 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_pre_bank_switch()
781 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), in qcom_swrm_port_params()
782 p_params->bps - 1); in qcom_swrm_port_params()
791 struct qcom_swrm_port_config *pcfg; in qcom_swrm_transport_params() local
793 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); in qcom_swrm_transport_params()
796 pcfg = &ctrl->pconfig[params->port_num]; in qcom_swrm_transport_params()
798 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; in qcom_swrm_transport_params()
799 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; in qcom_swrm_transport_params()
800 value |= pcfg->si; in qcom_swrm_transport_params()
802 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
806 if (pcfg->lane_control != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
807 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
808 value = pcfg->lane_control; in qcom_swrm_transport_params()
809 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
814 if (pcfg->blk_group_count != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
815 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
816 value = pcfg->blk_group_count; in qcom_swrm_transport_params()
817 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
822 if (pcfg->hstart != SWR_INVALID_PARAM in qcom_swrm_transport_params()
823 && pcfg->hstop != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
824 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); in qcom_swrm_transport_params()
825 value = (pcfg->hstop << 4) | pcfg->hstart; in qcom_swrm_transport_params()
826 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
828 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); in qcom_swrm_transport_params()
830 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
836 if (pcfg->bp_mode != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
837 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); in qcom_swrm_transport_params()
838 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); in qcom_swrm_transport_params()
849 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); in qcom_swrm_port_enable()
853 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_port_enable()
855 if (enable_ch->enable) in qcom_swrm_port_enable()
856 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); in qcom_swrm_port_enable()
860 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_port_enable()
880 struct qcom_swrm_port_config *pcfg; in qcom_swrm_compute_params() local
885 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in qcom_swrm_compute_params()
886 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in qcom_swrm_compute_params()
887 pcfg = &ctrl->pconfig[p_rt->num]; in qcom_swrm_compute_params()
888 p_rt->transport_params.port_num = p_rt->num; in qcom_swrm_compute_params()
889 if (pcfg->word_length != SWR_INVALID_PARAM) { in qcom_swrm_compute_params()
890 sdw_fill_port_params(&p_rt->port_params, in qcom_swrm_compute_params()
891 p_rt->num, pcfg->word_length + 1, in qcom_swrm_compute_params()
898 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in qcom_swrm_compute_params()
899 slave = s_rt->slave; in qcom_swrm_compute_params()
900 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in qcom_swrm_compute_params()
901 m_port = slave->m_port_map[p_rt->num]; in qcom_swrm_compute_params()
902 /* port config starts at offset 0 so -1 from actual port number */ in qcom_swrm_compute_params()
904 pcfg = &ctrl->pconfig[m_port]; in qcom_swrm_compute_params()
906 pcfg = &ctrl->pconfig[i]; in qcom_swrm_compute_params()
907 p_rt->transport_params.port_num = p_rt->num; in qcom_swrm_compute_params()
908 p_rt->transport_params.sample_interval = in qcom_swrm_compute_params()
909 pcfg->si + 1; in qcom_swrm_compute_params()
910 p_rt->transport_params.offset1 = pcfg->off1; in qcom_swrm_compute_params()
911 p_rt->transport_params.offset2 = pcfg->off2; in qcom_swrm_compute_params()
912 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; in qcom_swrm_compute_params()
913 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; in qcom_swrm_compute_params()
915 p_rt->transport_params.hstart = pcfg->hstart; in qcom_swrm_compute_params()
916 p_rt->transport_params.hstop = pcfg->hstop; in qcom_swrm_compute_params()
917 p_rt->transport_params.lane_ctrl = pcfg->lane_control; in qcom_swrm_compute_params()
918 if (pcfg->word_length != SWR_INVALID_PARAM) { in qcom_swrm_compute_params()
919 sdw_fill_port_params(&p_rt->port_params, in qcom_swrm_compute_params()
920 p_rt->num, in qcom_swrm_compute_params()
921 pcfg->word_length + 1, in qcom_swrm_compute_params()
944 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
946 list_for_each_entry(m_rt, &stream->master_list, stream_node) { in qcom_swrm_stream_free_ports()
947 if (m_rt->direction == SDW_DATA_DIR_RX) in qcom_swrm_stream_free_ports()
948 port_mask = &ctrl->dout_port_mask; in qcom_swrm_stream_free_ports()
950 port_mask = &ctrl->din_port_mask; in qcom_swrm_stream_free_ports()
952 list_for_each_entry(p_rt, &m_rt->port_list, port_node) in qcom_swrm_stream_free_ports()
953 clear_bit(p_rt->num, port_mask); in qcom_swrm_stream_free_ports()
956 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
974 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
975 list_for_each_entry(m_rt, &stream->master_list, stream_node) { in qcom_swrm_stream_alloc_ports()
976 if (m_rt->direction == SDW_DATA_DIR_RX) { in qcom_swrm_stream_alloc_ports()
977 maxport = ctrl->num_dout_ports; in qcom_swrm_stream_alloc_ports()
978 port_mask = &ctrl->dout_port_mask; in qcom_swrm_stream_alloc_ports()
980 maxport = ctrl->num_din_ports; in qcom_swrm_stream_alloc_ports()
981 port_mask = &ctrl->din_port_mask; in qcom_swrm_stream_alloc_ports()
984 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in qcom_swrm_stream_alloc_ports()
985 slave = s_rt->slave; in qcom_swrm_stream_alloc_ports()
986 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in qcom_swrm_stream_alloc_ports()
987 m_port = slave->m_port_map[p_rt->num]; in qcom_swrm_stream_alloc_ports()
988 /* Port numbers start from 1 - 14*/ in qcom_swrm_stream_alloc_ports()
995 dev_err(ctrl->dev, "All ports busy\n"); in qcom_swrm_stream_alloc_ports()
996 ret = -EBUSY; in qcom_swrm_stream_alloc_ports()
1001 pconfig[nports].ch_mask = p_rt->ch_mask; in qcom_swrm_stream_alloc_ports()
1015 sconfig.type = stream->type; in qcom_swrm_stream_alloc_ports()
1017 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, in qcom_swrm_stream_alloc_ports()
1025 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1034 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_params()
1035 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_params()
1039 substream->stream); in qcom_swrm_hw_params()
1049 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_free()
1050 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_free()
1053 sdw_stream_remove_master(&ctrl->bus, sruntime); in qcom_swrm_hw_free()
1061 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_set_sdw_stream()
1063 ctrl->sruntime[dai->id] = stream; in qcom_swrm_set_sdw_stream()
1070 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_get_sdw_stream()
1072 return ctrl->sruntime[dai->id]; in qcom_swrm_get_sdw_stream()
1078 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_startup()
1079 struct snd_soc_pcm_runtime *rtd = substream->private_data; in qcom_swrm_startup()
1084 ret = pm_runtime_resume_and_get(ctrl->dev); in qcom_swrm_startup()
1085 if (ret < 0 && ret != -EACCES) { in qcom_swrm_startup()
1086 dev_err_ratelimited(ctrl->dev, in qcom_swrm_startup()
1092 sruntime = sdw_alloc_stream(dai->name); in qcom_swrm_startup()
1094 return -ENOMEM; in qcom_swrm_startup()
1096 ctrl->sruntime[dai->id] = sruntime; in qcom_swrm_startup()
1100 substream->stream); in qcom_swrm_startup()
1101 if (ret < 0 && ret != -ENOTSUPP) { in qcom_swrm_startup()
1102 dev_err(dai->dev, "Failed to set sdw stream on %s\n", in qcom_swrm_startup()
1103 codec_dai->name); in qcom_swrm_startup()
1115 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_shutdown()
1117 sdw_release_stream(ctrl->sruntime[dai->id]); in qcom_swrm_shutdown()
1118 ctrl->sruntime[dai->id] = NULL; in qcom_swrm_shutdown()
1119 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_shutdown()
1120 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_shutdown()
1139 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_register_dais()
1142 struct device *dev = ctrl->dev; in qcom_swrm_register_dais()
1148 return -ENOMEM; in qcom_swrm_register_dais()
1153 return -ENOMEM; in qcom_swrm_register_dais()
1155 if (i < ctrl->num_dout_ports) in qcom_swrm_register_dais()
1160 stream->channels_min = 1; in qcom_swrm_register_dais()
1161 stream->channels_max = 1; in qcom_swrm_register_dais()
1162 stream->rates = SNDRV_PCM_RATE_48000; in qcom_swrm_register_dais()
1163 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; in qcom_swrm_register_dais()
1169 return devm_snd_soc_register_component(ctrl->dev, in qcom_swrm_register_dais()
1176 struct device_node *np = ctrl->dev->of_node; in qcom_swrm_get_port_config()
1188 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_get_port_config()
1190 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); in qcom_swrm_get_port_config()
1191 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); in qcom_swrm_get_port_config()
1193 ret = of_property_read_u32(np, "qcom,din-ports", &val); in qcom_swrm_get_port_config()
1197 if (val > ctrl->num_din_ports) in qcom_swrm_get_port_config()
1198 return -EINVAL; in qcom_swrm_get_port_config()
1200 ctrl->num_din_ports = val; in qcom_swrm_get_port_config()
1202 ret = of_property_read_u32(np, "qcom,dout-ports", &val); in qcom_swrm_get_port_config()
1206 if (val > ctrl->num_dout_ports) in qcom_swrm_get_port_config()
1207 return -EINVAL; in qcom_swrm_get_port_config()
1209 ctrl->num_dout_ports = val; in qcom_swrm_get_port_config()
1211 nports = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_get_port_config()
1212 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ in qcom_swrm_get_port_config()
1213 set_bit(0, &ctrl->dout_port_mask); in qcom_swrm_get_port_config()
1214 set_bit(0, &ctrl->din_port_mask); in qcom_swrm_get_port_config()
1216 ret = of_property_read_u8_array(np, "qcom,ports-offset1", in qcom_swrm_get_port_config()
1221 ret = of_property_read_u8_array(np, "qcom,ports-offset2", in qcom_swrm_get_port_config()
1226 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", in qcom_swrm_get_port_config()
1231 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", in qcom_swrm_get_port_config()
1234 if (ctrl->version <= 0x01030000) in qcom_swrm_get_port_config()
1241 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); in qcom_swrm_get_port_config()
1244 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); in qcom_swrm_get_port_config()
1247 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); in qcom_swrm_get_port_config()
1250 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); in qcom_swrm_get_port_config()
1253 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); in qcom_swrm_get_port_config()
1256 /* Valid port number range is from 1-14 */ in qcom_swrm_get_port_config()
1257 ctrl->pconfig[i + 1].si = si[i]; in qcom_swrm_get_port_config()
1258 ctrl->pconfig[i + 1].off1 = off1[i]; in qcom_swrm_get_port_config()
1259 ctrl->pconfig[i + 1].off2 = off2[i]; in qcom_swrm_get_port_config()
1260 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; in qcom_swrm_get_port_config()
1261 ctrl->pconfig[i + 1].hstart = hstart[i]; in qcom_swrm_get_port_config()
1262 ctrl->pconfig[i + 1].hstop = hstop[i]; in qcom_swrm_get_port_config()
1263 ctrl->pconfig[i + 1].word_length = word_length[i]; in qcom_swrm_get_port_config()
1264 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; in qcom_swrm_get_port_config()
1265 ctrl->pconfig[i + 1].lane_control = lane_control[i]; in qcom_swrm_get_port_config()
1274 struct qcom_swrm_ctrl *swrm = s_file->private; in swrm_reg_show()
1277 ret = pm_runtime_resume_and_get(swrm->dev); in swrm_reg_show()
1278 if (ret < 0 && ret != -EACCES) { in swrm_reg_show()
1279 dev_err_ratelimited(swrm->dev, in swrm_reg_show()
1286 swrm->reg_read(swrm, reg, ®_val); in swrm_reg_show()
1289 pm_runtime_mark_last_busy(swrm->dev); in swrm_reg_show()
1290 pm_runtime_put_autosuspend(swrm->dev); in swrm_reg_show()
1300 struct device *dev = &pdev->dev;
1310 return -ENOMEM;
1313 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1314 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1316 if (dev->parent->bus == &slimbus_bus) {
1320 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1321 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1322 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1323 if (!ctrl->regmap)
1324 return -EINVAL;
1326 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1327 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1328 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1329 if (IS_ERR(ctrl->mmio))
1330 return PTR_ERR(ctrl->mmio);
1333 if (data->sw_clk_gate_required) {
1334 ctrl->audio_cgcr = devm_reset_control_get_exclusive(dev, "swr_audio_cgcr");
1335 if (IS_ERR_OR_NULL(ctrl->audio_cgcr)) {
1337 ret = PTR_ERR(ctrl->audio_cgcr);
1342 ctrl->irq = of_irq_get(dev->of_node, 0);
1343 if (ctrl->irq < 0) {
1344 ret = ctrl->irq;
1348 ctrl->hclk = devm_clk_get(dev, "iface");
1349 if (IS_ERR(ctrl->hclk)) {
1350 ret = PTR_ERR(ctrl->hclk);
1354 clk_prepare_enable(ctrl->hclk);
1356 ctrl->dev = dev;
1357 dev_set_drvdata(&pdev->dev, ctrl);
1358 mutex_init(&ctrl->port_lock);
1359 init_completion(&ctrl->broadcast);
1360 init_completion(&ctrl->enumeration);
1362 ctrl->bus.ops = &qcom_swrm_ops;
1363 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1364 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1365 ctrl->bus.clk_stop_timeout = 300;
1371 params = &ctrl->bus.params;
1372 params->max_dr_freq = DEFAULT_CLK_FREQ;
1373 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1374 params->col = data->default_cols;
1375 params->row = data->default_rows;
1376 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1377 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1378 params->next_bank = !params->curr_bank;
1380 prop = &ctrl->bus.prop;
1381 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1382 prop->num_clk_gears = 0;
1383 prop->num_clk_freq = MAX_FREQ_NUM;
1384 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1385 prop->default_col = data->default_cols;
1386 prop->default_row = data->default_rows;
1388 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1390 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1400 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1401 if (ctrl->wake_irq > 0) {
1402 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1412 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1420 wait_for_completion_timeout(&ctrl->enumeration,
1427 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1428 ctrl->version & 0xffff);
1437 if (ctrl->version <= 0x01030000) {
1438 ctrl->clock_stop_not_supported = true;
1440 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1442 ctrl->clock_stop_not_supported = true;
1446 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1447 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1454 sdw_bus_master_delete(&ctrl->bus);
1456 clk_disable_unprepare(ctrl->hclk);
1463 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1465 sdw_bus_master_delete(&ctrl->bus);
1466 clk_disable_unprepare(ctrl->hclk);
1477 swrm->reg_read(swrm, SWRM_COMP_STATUS, &comp_sts);
1483 } while (retry--);
1485 dev_err(swrm->dev, "%s: link status not %s\n", __func__,
1496 if (ctrl->wake_irq > 0) {
1497 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1498 disable_irq_nosync(ctrl->wake_irq);
1501 clk_prepare_enable(ctrl->hclk);
1503 if (ctrl->clock_stop_not_supported) {
1504 reinit_completion(&ctrl->enumeration);
1505 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1512 dev_err(ctrl->dev, "link failed to connect\n");
1515 wait_for_completion_timeout(&ctrl->enumeration,
1518 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1520 reset_control_reset(ctrl->audio_cgcr);
1522 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1523 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR,
1526 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1527 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1528 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1532 dev_err(ctrl->dev, "link failed to connect\n");
1534 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1536 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1547 if (!ctrl->clock_stop_not_supported) {
1549 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1550 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, ctrl->intr_mask);
1551 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN, ctrl->intr_mask);
1553 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1554 if (ret < 0 && ret != -ENODATA) {
1559 ret = sdw_bus_clk_stop(&ctrl->bus);
1560 if (ret < 0 && ret != -ENODATA) {
1566 clk_disable_unprepare(ctrl->hclk);
1570 if (ctrl->wake_irq > 0) {
1571 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1572 enable_irq(ctrl->wake_irq);
1583 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1584 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1585 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1595 .name = "qcom-soundwire",