Lines Matching +full:combined +full:- +full:power +full:- +full:req
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
36 #include <linux/pinctrl/pinconf-generic.h>
54 #include <dt-bindings/interrupt-controller/arm-gic.h>
55 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
56 #include <dt-bindings/gpio/tegra186-gpio.h>
57 #include <dt-bindings/gpio/tegra194-gpio.h>
58 #include <dt-bindings/gpio/tegra234-gpio.h>
59 #include <dt-bindings/soc/tegra-pmc.h>
63 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
64 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
381 * struct tegra_pmc - NVIDIA Tegra PMC
393 * @cpu_good_time: CPU power good time (in microseconds)
394 * @cpu_off_time: CPU power off time (in microsecends)
395 * @core_osc_time: core power good OSC time (in microseconds)
396 * @core_pmu_time: core power good PMU time (in microseconds)
397 * @core_off_time: core power off time (in microseconds)
398 * @corereq_high: core power request is active-high
399 * @sysclkreq_high: system clock request is active-high
400 * @combined_req: combined power request for CPU & core
401 * @cpu_pwr_good_en: CPU power good signal is enabled
404 * @powergates_available: Bitmap of available power gates
405 * @powergates_lock: mutex for power gate register access
469 if (pmc->tz_only) { in tegra_pmc_readl()
473 if (pmc->dev) in tegra_pmc_readl()
474 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
484 return readl(pmc->base + offset); in tegra_pmc_readl()
492 if (pmc->tz_only) { in tegra_pmc_writel()
496 if (pmc->dev) in tegra_pmc_writel()
497 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
504 writel(value, pmc->base + offset); in tegra_pmc_writel()
510 if (pmc->tz_only) in tegra_pmc_scratch_readl()
513 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
519 if (pmc->tz_only) in tegra_pmc_scratch_writel()
522 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
532 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
540 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
545 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
552 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
553 return -EINVAL; in tegra_powergate_lookup()
555 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
559 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
563 return -ENODEV; in tegra_powergate_lookup()
575 * if there is contention with a HW-initiated toggling (i.e. CPU core in tegra20_powergate_set()
576 * power-gated), the command should be retried in that case. in tegra20_powergate_set()
584 } while (ret == -ETIMEDOUT && retries--); in tegra20_powergate_set()
600 /* wait while PMC power gating is contended */ in tegra114_powergate_set()
624 * tegra_powergate_set() - set the state of a partition
625 * @pmc: power management controller
634 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
635 return -EINVAL; in tegra_powergate_set()
637 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
640 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
644 err = pmc->soc->powergate_set(pmc, id, new_state); in tegra_powergate_set()
646 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
656 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
663 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
683 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
694 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_prepare_clocks()
695 pg->clk_rates[i] = clk_get_rate(pg->clks[i]); in tegra_powergate_prepare_clocks()
697 if (!pg->clk_rates[i]) { in tegra_powergate_prepare_clocks()
698 err = -EINVAL; in tegra_powergate_prepare_clocks()
702 if (pg->clk_rates[i] <= safe_rate) in tegra_powergate_prepare_clocks()
711 err = clk_set_rate(pg->clks[i], safe_rate); in tegra_powergate_prepare_clocks()
719 while (i--) in tegra_powergate_prepare_clocks()
720 clk_set_rate(pg->clks[i], pg->clk_rates[i]); in tegra_powergate_prepare_clocks()
730 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_unprepare_clocks()
731 err = clk_set_rate(pg->clks[i], pg->clk_rates[i]); in tegra_powergate_unprepare_clocks()
743 for (i = 0; i < pg->num_clks; i++) in tegra_powergate_disable_clocks()
744 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_disable_clocks()
752 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_enable_clocks()
753 err = clk_prepare_enable(pg->clks[i]); in tegra_powergate_enable_clocks()
761 while (i--) in tegra_powergate_enable_clocks()
762 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_enable_clocks()
772 err = reset_control_assert(pg->reset); in tegra_powergate_power_up()
778 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
794 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
800 err = reset_control_deassert(pg->reset); in tegra_powergate_power_up()
806 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
807 err = tegra210_clk_handle_mbist_war(pg->id); in tegra_powergate_power_up()
828 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
847 err = reset_control_assert(pg->reset); in tegra_powergate_power_down()
857 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
870 reset_control_deassert(pg->reset); in tegra_powergate_power_down()
885 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
891 pg->genpd.name, err); in tegra_genpd_power_on()
895 reset_control_release(pg->reset); in tegra_genpd_power_on()
904 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
907 err = reset_control_acquire(pg->reset); in tegra_genpd_power_off()
910 pg->genpd.name, err); in tegra_genpd_power_off()
917 pg->genpd.name, err); in tegra_genpd_power_off()
918 reset_control_release(pg->reset); in tegra_genpd_power_off()
925 * tegra_powergate_power_on() - power on partition
931 return -EINVAL; in tegra_powergate_power_on()
938 * tegra_powergate_power_off() - power off partition
944 return -EINVAL; in tegra_powergate_power_off()
951 * tegra_powergate_is_powered() - check if partition is powered
952 * @pmc: power management controller
958 return -EINVAL; in tegra_powergate_is_powered()
964 * tegra_powergate_remove_clamping() - remove power clamps for partition
970 return -EINVAL; in tegra_powergate_remove_clamping()
977 * tegra_powergate_sequence_power_up() - power up partition
991 return -EINVAL; in tegra_powergate_sequence_power_up()
995 return -ENOMEM; in tegra_powergate_sequence_power_up()
997 pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL); in tegra_powergate_sequence_power_up()
998 if (!pg->clk_rates) { in tegra_powergate_sequence_power_up()
999 kfree(pg->clks); in tegra_powergate_sequence_power_up()
1000 return -ENOMEM; in tegra_powergate_sequence_power_up()
1003 pg->id = id; in tegra_powergate_sequence_power_up()
1004 pg->clks = &clk; in tegra_powergate_sequence_power_up()
1005 pg->num_clks = 1; in tegra_powergate_sequence_power_up()
1006 pg->reset = rst; in tegra_powergate_sequence_power_up()
1007 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
1011 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
1014 kfree(pg->clk_rates); in tegra_powergate_sequence_power_up()
1022 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
1023 * @pmc: power management controller
1032 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
1033 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
1035 return -EINVAL; in tegra_get_cpu_powergate_id()
1039 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
1054 * tegra_pmc_cpu_power_on() - power on CPU partition
1069 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
1087 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1097 if (strcmp(cmd, "forced-recovery") == 0) in tegra_pmc_program_reboot_reason()
1101 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_program_reboot_reason()
1138 * connected in order to display battery status and power off. in tegra_pmc_power_off_handler()
1157 seq_printf(s, "------------------\n"); in powergate_show()
1159 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1164 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
1175 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, in tegra_powergate_debugfs_init()
1177 if (!pmc->debugfs) in tegra_powergate_debugfs_init()
1178 return -ENOMEM; in tegra_powergate_debugfs_init()
1192 return -ENODEV; in tegra_powergate_of_get_clks()
1194 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); in tegra_powergate_of_get_clks()
1195 if (!pg->clks) in tegra_powergate_of_get_clks()
1196 return -ENOMEM; in tegra_powergate_of_get_clks()
1198 pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL); in tegra_powergate_of_get_clks()
1199 if (!pg->clk_rates) { in tegra_powergate_of_get_clks()
1200 kfree(pg->clks); in tegra_powergate_of_get_clks()
1201 return -ENOMEM; in tegra_powergate_of_get_clks()
1205 pg->clks[i] = of_clk_get(np, i); in tegra_powergate_of_get_clks()
1206 if (IS_ERR(pg->clks[i])) { in tegra_powergate_of_get_clks()
1207 err = PTR_ERR(pg->clks[i]); in tegra_powergate_of_get_clks()
1212 pg->num_clks = count; in tegra_powergate_of_get_clks()
1217 while (i--) in tegra_powergate_of_get_clks()
1218 clk_put(pg->clks[i]); in tegra_powergate_of_get_clks()
1220 kfree(pg->clk_rates); in tegra_powergate_of_get_clks()
1221 kfree(pg->clks); in tegra_powergate_of_get_clks()
1229 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1232 pg->reset = of_reset_control_array_get_exclusive_released(np); in tegra_powergate_of_get_resets()
1233 if (IS_ERR(pg->reset)) { in tegra_powergate_of_get_resets()
1234 err = PTR_ERR(pg->reset); in tegra_powergate_of_get_resets()
1239 err = reset_control_acquire(pg->reset); in tegra_powergate_of_get_resets()
1246 err = reset_control_assert(pg->reset); in tegra_powergate_of_get_resets()
1248 err = reset_control_deassert(pg->reset); in tegra_powergate_of_get_resets()
1252 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1257 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1258 reset_control_put(pg->reset); in tegra_powergate_of_get_resets()
1266 struct device *dev = pmc->dev; in tegra_powergate_add()
1273 return -ENOMEM; in tegra_powergate_add()
1275 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1278 err = -ENODEV; in tegra_powergate_add()
1286 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1288 pg->id = id; in tegra_powergate_add()
1289 pg->genpd.name = np->name; in tegra_powergate_add()
1290 pg->genpd.power_off = tegra_genpd_power_off; in tegra_powergate_add()
1291 pg->genpd.power_on = tegra_genpd_power_on; in tegra_powergate_add()
1292 pg->pmc = pmc; in tegra_powergate_add()
1294 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1315 err = pm_genpd_init(&pg->genpd, NULL, off); in tegra_powergate_add()
1322 err = of_genpd_add_provider_simple(np, &pg->genpd); in tegra_powergate_add()
1329 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); in tegra_powergate_add()
1334 pm_genpd_remove(&pg->genpd); in tegra_powergate_add()
1337 reset_control_put(pg->reset); in tegra_powergate_add()
1340 while (pg->num_clks--) in tegra_powergate_add()
1341 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_add()
1343 kfree(pg->clks); in tegra_powergate_add()
1346 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1356 return pmc->core_domain_state_synced; in tegra_pmc_core_domain_state_synced()
1366 opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level); in tegra_pmc_core_pd_set_performance_state()
1368 dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n", in tegra_pmc_core_pd_set_performance_state()
1373 mutex_lock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1374 err = dev_pm_opp_set_opp(pmc->dev, opp); in tegra_pmc_core_pd_set_performance_state()
1375 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_core_pd_set_performance_state()
1380 dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n", in tegra_pmc_core_pd_set_performance_state()
1401 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL); in tegra_pmc_core_pd_add()
1403 return -ENOMEM; in tegra_pmc_core_pd_add()
1405 genpd->name = "core"; in tegra_pmc_core_pd_add()
1406 genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; in tegra_pmc_core_pd_add()
1407 genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state; in tegra_pmc_core_pd_add()
1409 err = devm_pm_opp_set_regulators(pmc->dev, rname); in tegra_pmc_core_pd_add()
1411 return dev_err_probe(pmc->dev, err, in tegra_pmc_core_pd_add()
1416 dev_err(pmc->dev, "failed to init core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1422 dev_err(pmc->dev, "failed to add core genpd: %d\n", err); in tegra_pmc_core_pd_add()
1426 pmc->core_domain_registered = true; in tegra_pmc_core_pd_add()
1444 * Core power domain is the parent of powergate domains, hence it in tegra_powergate_init()
1447 np = of_get_child_by_name(parent, "core-domain"); in tegra_powergate_init()
1466 if (of_parse_phandle_with_args(child, "power-domains", in tegra_powergate_init()
1467 "#power-domain-cells", in tegra_powergate_init()
1491 reset_control_put(pg->reset); in tegra_powergate_remove()
1493 while (pg->num_clks--) in tegra_powergate_remove()
1494 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_remove()
1496 kfree(pg->clks); in tegra_powergate_remove()
1498 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1524 np = of_get_child_by_name(parent, "core-domain"); in tegra_powergate_remove_all()
1536 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1537 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1538 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1553 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_get_dpd_register_bit()
1554 return -ENOENT; in tegra_io_pad_get_dpd_register_bit()
1557 if (pad->dpd == UINT_MAX) in tegra_io_pad_get_dpd_register_bit()
1558 return -ENOTSUPP; in tegra_io_pad_get_dpd_register_bit()
1560 *mask = BIT(pad->dpd % 32); in tegra_io_pad_get_dpd_register_bit()
1562 if (pad->dpd < 32) { in tegra_io_pad_get_dpd_register_bit()
1563 *status = pmc->soc->regs->dpd_status; in tegra_io_pad_get_dpd_register_bit()
1564 *request = pmc->soc->regs->dpd_req; in tegra_io_pad_get_dpd_register_bit()
1566 *status = pmc->soc->regs->dpd2_status; in tegra_io_pad_get_dpd_register_bit()
1567 *request = pmc->soc->regs->dpd2_req; in tegra_io_pad_get_dpd_register_bit()
1584 if (pmc->clk) { in tegra_io_pad_prepare()
1585 rate = pmc->rate; in tegra_io_pad_prepare()
1587 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1588 return -ENODEV; in tegra_io_pad_prepare()
1617 return -ETIMEDOUT; in tegra_io_pad_poll()
1622 if (pmc->clk) in tegra_io_pad_unprepare()
1627 * tegra_io_pad_power_enable() - enable power to I/O pad
1628 * @id: Tegra I/O pad ID for which to enable power
1638 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1642 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1650 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1657 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1663 * tegra_io_pad_power_disable() - disable power to I/O pad
1664 * @id: Tegra I/O pad ID for which to disable power
1674 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1678 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1686 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1693 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1722 return -ENOENT; in tegra_io_pad_set_voltage()
1724 if (pad->voltage == UINT_MAX) in tegra_io_pad_set_voltage()
1725 return -ENOTSUPP; in tegra_io_pad_set_voltage()
1727 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1729 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1733 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1735 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1739 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ in tegra_io_pad_set_voltage()
1741 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1748 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1750 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1755 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1769 return -ENOENT; in tegra_io_pad_get_voltage()
1771 if (pad->voltage == UINT_MAX) in tegra_io_pad_get_voltage()
1772 return -ENOTSUPP; in tegra_io_pad_get_voltage()
1774 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1779 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1786 * tegra_io_rail_power_on() - enable power to I/O rail
1787 * @id: Tegra I/O pad ID for which to enable power
1798 * tegra_io_rail_power_off() - disable power to I/O rail
1799 * @id: Tegra I/O pad ID for which to disable power
1812 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1820 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1835 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1845 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1849 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1864 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { in tegra_pmc_parse_dt()
1865 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1869 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1873 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1877 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1881 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1886 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1888 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) in tegra_pmc_parse_dt()
1889 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1891 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1893 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1894 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1896 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1898 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", in tegra_pmc_parse_dt()
1900 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1902 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1903 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1905 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1906 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1908 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1910 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1911 "nvidia,core-power-req-active-high"); in tegra_pmc_parse_dt()
1913 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1914 "nvidia,sys-clock-req-active-high"); in tegra_pmc_parse_dt()
1916 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1917 "nvidia,combined-power-req"); in tegra_pmc_parse_dt()
1919 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1920 "nvidia,cpu-pwr-good-en"); in tegra_pmc_parse_dt()
1922 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
1924 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1925 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1927 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1928 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1935 if (pmc->soc->init) in tegra_pmc_init()
1936 pmc->soc->init(pmc); in tegra_pmc_init()
1943 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1947 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1950 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1952 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1956 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { in tegra_pmc_init_tsense_reset()
1961 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { in tegra_pmc_init_tsense_reset()
1962 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1966 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { in tegra_pmc_init_tsense_reset()
1967 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1971 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { in tegra_pmc_init_tsense_reset()
1972 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1976 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) in tegra_pmc_init_tsense_reset()
1999 checksum = 0x100 - checksum; in tegra_pmc_init_tsense_reset()
2009 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
2019 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
2027 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
2037 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
2062 return -EINVAL; in tegra_io_pad_pinconf_get()
2066 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
2074 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
2082 return -EINVAL; in tegra_io_pad_pinconf_get()
2103 return -EINVAL; in tegra_io_pad_pinconf_set()
2112 err = tegra_io_pad_power_disable(pad->id); in tegra_io_pad_pinconf_set()
2114 err = tegra_io_pad_power_enable(pad->id); in tegra_io_pad_pinconf_set()
2121 return -EINVAL; in tegra_io_pad_pinconf_set()
2122 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
2127 return -EINVAL; in tegra_io_pad_pinconf_set()
2149 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
2152 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
2153 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
2154 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
2156 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
2158 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
2159 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
2160 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
2173 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
2174 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
2175 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
2177 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
2180 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
2190 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
2191 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
2192 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
2194 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
2197 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
2204 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
2207 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
2215 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
2229 if (WARN_ON(fwspec->param_count < 2)) in tegra_pmc_irq_translate()
2230 return -EINVAL; in tegra_pmc_irq_translate()
2232 *hwirq = fwspec->param[0]; in tegra_pmc_irq_translate()
2233 *type = fwspec->param[1]; in tegra_pmc_irq_translate()
2241 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc()
2242 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
2248 return -EINVAL; in tegra_pmc_irq_alloc()
2250 for (i = 0; i < soc->num_wake_events; i++) { in tegra_pmc_irq_alloc()
2251 const struct tegra_wake_event *event = &soc->wake_events[i]; in tegra_pmc_irq_alloc()
2254 if (fwspec->param_count == 2) { in tegra_pmc_irq_alloc()
2257 if (event->id != fwspec->param[0]) in tegra_pmc_irq_alloc()
2261 event->id, in tegra_pmc_irq_alloc()
2262 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2267 if (event->irq == 0) { in tegra_pmc_irq_alloc()
2268 err = irq_domain_disconnect_hierarchy(domain->parent, virq); in tegra_pmc_irq_alloc()
2272 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
2275 spec.param[1] = event->irq; in tegra_pmc_irq_alloc()
2276 spec.param[2] = fwspec->param[1]; in tegra_pmc_irq_alloc()
2285 if (fwspec->param_count == 3) { in tegra_pmc_irq_alloc()
2286 if (event->gpio.instance != fwspec->param[0] || in tegra_pmc_irq_alloc()
2287 event->gpio.pin != fwspec->param[1]) in tegra_pmc_irq_alloc()
2291 event->id, in tegra_pmc_irq_alloc()
2292 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2295 if (!err && domain->parent) in tegra_pmc_irq_alloc()
2296 err = irq_domain_disconnect_hierarchy(domain->parent, in tegra_pmc_irq_alloc()
2302 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
2303 if (i == soc->num_wake_events) in tegra_pmc_irq_alloc()
2320 offset = data->hwirq / 32; in tegra210_pmc_irq_set_wake()
2321 bit = data->hwirq % 32; in tegra210_pmc_irq_set_wake()
2331 if (data->hwirq >= 32) in tegra210_pmc_irq_set_wake()
2354 offset = data->hwirq / 32; in tegra210_pmc_irq_set_type()
2355 bit = data->hwirq % 32; in tegra210_pmc_irq_set_type()
2357 if (data->hwirq >= 32) in tegra210_pmc_irq_set_type()
2380 return -EINVAL; in tegra210_pmc_irq_set_type()
2394 offset = data->hwirq / 32; in tegra186_pmc_irq_set_wake()
2395 bit = data->hwirq % 32; in tegra186_pmc_irq_set_wake()
2398 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2401 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2408 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2411 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2421 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2439 return -EINVAL; in tegra186_pmc_irq_set_type()
2442 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2449 if (data->parent_data) in tegra_irq_mask_parent()
2455 if (data->parent_data) in tegra_irq_unmask_parent()
2461 if (data->parent_data) in tegra_irq_eoi_parent()
2469 if (data->parent_data) in tegra_irq_set_affinity_parent()
2472 return -EINVAL; in tegra_irq_set_affinity_parent()
2480 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2489 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2490 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2491 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2492 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2493 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2494 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2495 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2497 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2499 if (!pmc->domain) { in tegra_pmc_irq_init()
2500 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2501 return -ENOMEM; in tegra_pmc_irq_init()
2515 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2519 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2523 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2528 return notifier_from_errno(-EINVAL); in tegra_pmc_clk_notify_cb()
2546 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2557 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2558 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); in pmc_clk_mux_set_parent()
2559 val |= index << clk->mux_shift; in pmc_clk_mux_set_parent()
2560 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2561 pmc_clk_fence_udelay(clk->offs); in pmc_clk_mux_set_parent()
2571 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2590 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); in pmc_clk_enable()
2599 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); in pmc_clk_disable()
2619 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2621 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_out_register()
2623 init.name = data->name; in tegra_pmc_clk_out_register()
2625 init.parent_names = data->parents; in tegra_pmc_clk_out_register()
2626 init.num_parents = data->num_parents; in tegra_pmc_clk_out_register()
2630 pmc_clk->hw.init = &init; in tegra_pmc_clk_out_register()
2631 pmc_clk->offs = offset; in tegra_pmc_clk_out_register()
2632 pmc_clk->mux_shift = data->mux_shift; in tegra_pmc_clk_out_register()
2633 pmc_clk->force_en_shift = data->force_en_shift; in tegra_pmc_clk_out_register()
2635 return clk_register(NULL, &pmc_clk->hw); in tegra_pmc_clk_out_register()
2642 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2649 pmc_clk_set_state(gate->offs, gate->shift, 1); in pmc_clk_gate_enable()
2658 pmc_clk_set_state(gate->offs, gate->shift, 0); in pmc_clk_gate_disable()
2675 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2677 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_gate_register()
2685 gate->hw.init = &init; in tegra_pmc_clk_gate_register()
2686 gate->offs = offset; in tegra_pmc_clk_gate_register()
2687 gate->shift = shift; in tegra_pmc_clk_gate_register()
2689 return clk_register(NULL, &gate->hw); in tegra_pmc_clk_gate_register()
2700 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2701 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2707 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2711 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2712 sizeof(*clk_data->clks), GFP_KERNEL); in tegra_pmc_clock_register()
2713 if (!clk_data->clks) in tegra_pmc_clock_register()
2716 clk_data->clk_num = TEGRA_PMC_CLK_MAX; in tegra_pmc_clock_register()
2719 clk_data->clks[i] = ERR_PTR(-ENOENT); in tegra_pmc_clock_register()
2721 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2724 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2728 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2729 data->name, PTR_ERR_OR_ZERO(clk)); in tegra_pmc_clock_register()
2733 err = clk_register_clkdev(clk, data->name, NULL); in tegra_pmc_clock_register()
2735 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2737 data->name, err); in tegra_pmc_clock_register()
2741 clk_data->clks[data->clk_id] = clk; in tegra_pmc_clock_register()
2744 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2752 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2763 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2771 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2777 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; in tegra_pmc_clock_register()
2782 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2835 if (pmc->soc->has_usb_sleepwalk) { in tegra_pmc_regmap_init()
2836 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config); in tegra_pmc_regmap_init()
2839 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err); in tegra_pmc_regmap_init()
2849 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; in tegra_pmc_reset_suspend_mode()
2863 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2864 return -ENODEV; in tegra_pmc_probe()
2866 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2870 err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, in tegra_pmc_probe()
2882 pmc->wake = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2883 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2884 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2886 pmc->wake = base; in tegra_pmc_probe()
2891 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2892 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2893 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2895 pmc->aotag = base; in tegra_pmc_probe()
2900 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2901 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2902 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2904 pmc->scratch = base; in tegra_pmc_probe()
2907 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk"); in tegra_pmc_probe()
2908 if (IS_ERR(pmc->clk)) in tegra_pmc_probe()
2909 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk), in tegra_pmc_probe()
2913 * PMC should be last resort for restarting since it soft-resets in tegra_pmc_probe()
2916 err = devm_register_reboot_notifier(&pdev->dev, in tegra_pmc_probe()
2919 dev_err(&pdev->dev, "unable to register reboot notifier, %d\n", in tegra_pmc_probe()
2924 err = devm_register_sys_off_handler(&pdev->dev, in tegra_pmc_probe()
2929 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", in tegra_pmc_probe()
2935 * PMC should be primary power-off method if it soft-resets CPU, in tegra_pmc_probe()
2938 err = devm_register_sys_off_handler(&pdev->dev, in tegra_pmc_probe()
2943 dev_err(&pdev->dev, "failed to register sys-off handler: %d\n", in tegra_pmc_probe()
2953 if (pmc->clk) { in tegra_pmc_probe()
2954 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2955 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2957 dev_err(&pdev->dev, in tegra_pmc_probe()
2962 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2965 pmc->dev = &pdev->dev; in tegra_pmc_probe()
2987 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2995 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
2996 iounmap(pmc->base); in tegra_pmc_probe()
2997 pmc->base = base; in tegra_pmc_probe()
2998 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
3000 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
3007 tegra_powergate_remove_all(pdev->dev.of_node); in tegra_pmc_probe()
3009 debugfs_remove(pmc->debugfs); in tegra_pmc_probe()
3011 device_remove_file(&pdev->dev, &dev_attr_reset_reason); in tegra_pmc_probe()
3012 device_remove_file(&pdev->dev, &dev_attr_reset_level); in tegra_pmc_probe()
3013 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
3068 /* Always enable CPU power request */ in tegra20_pmc_init()
3075 if (pmc->sysclkreq_high) in tegra20_pmc_init()
3080 if (pmc->corereq_high) in tegra20_pmc_init()
3094 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
3095 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
3096 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
3097 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
3331 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3333 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3334 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3335 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3336 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3421 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3430 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3443 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3444 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3445 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3446 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3447 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3451 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3457 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3519 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3520 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3521 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3522 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3523 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3527 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3532 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3533 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3534 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3535 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3547 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3549 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3550 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3552 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3553 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3585 index = of_property_match_string(np, "reg-names", "wake"); in tegra186_pmc_setup_irq_polarity()
3587 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3595 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3635 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3675 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3676 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3677 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3678 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3679 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3681 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3682 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3686 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3687 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3689 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3690 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3691 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3692 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3693 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3697 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3698 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3699 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3700 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3701 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3702 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3703 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3704 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3706 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3717 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3718 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3720 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3721 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3770 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
3772 TEGRA_WAKE_SIMPLE("usb3-port-0", 76),
3773 TEGRA_WAKE_SIMPLE("usb3-port-1", 77),
3774 TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78),
3775 TEGRA_WAKE_SIMPLE("usb2-port-0", 79),
3776 TEGRA_WAKE_SIMPLE("usb2-port-1", 80),
3777 TEGRA_WAKE_SIMPLE("usb2-port-2", 81),
3778 TEGRA_WAKE_SIMPLE("usb2-port-3", 82),
3868 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)),
3904 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3905 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3906 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3907 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3908 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3909 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3910 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3911 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3912 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3921 * Newer device-trees have power domains, but we need to prepare all in tegra_pmc_sync_state()
3925 if (!pmc->soc->supports_core_domain) in tegra_pmc_sync_state()
3929 * Older device-trees don't have core PD, and thus, there are in tegra_pmc_sync_state()
3933 if (!pmc->core_domain_registered) in tegra_pmc_sync_state()
3936 pmc->core_domain_state_synced = true; in tegra_pmc_sync_state()
3938 /* this is a no-op if core regulator isn't used */ in tegra_pmc_sync_state()
3939 mutex_lock(&pmc->powergates_lock); in tegra_pmc_sync_state()
3941 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_sync_state()
3949 .name = "tegra-pmc",
3965 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3972 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3973 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3975 /* if we read all-zeroes, access is restricted to TZ only */ in tegra_pmc_detect_tz_only()
3982 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3999 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
4004 * Fall back to legacy initialization for 32-bit ARM only. All in tegra_pmc_early_init()
4005 * 64-bit ARM device tree files for Tegra are required to have in tegra_pmc_early_init()
4008 * This is for backwards-compatibility with old device trees in tegra_pmc_early_init()
4024 * nice with multi-platform kernels. in tegra_pmc_early_init()
4036 return -ENXIO; in tegra_pmc_early_init()
4040 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
4041 if (!pmc->base) { in tegra_pmc_early_init()
4044 return -ENXIO; in tegra_pmc_early_init()
4048 pmc->soc = match->data; in tegra_pmc_early_init()
4050 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
4051 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
4054 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
4055 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
4056 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
4060 * exists and contains the nvidia,invert-interrupt property. in tegra_pmc_early_init()
4062 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); in tegra_pmc_early_init()
4064 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()