8  * Error types supported by CBB2.0 are:
31 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0	0x0
32 #define FABRIC_EN_CFG_STATUS_0_0		0x40
33 #define FABRIC_EN_CFG_ADDR_INDEX_0_0		0x60
34 #define FABRIC_EN_CFG_ADDR_LOW_0		0x80
35 #define FABRIC_EN_CFG_ADDR_HI_0			0x84
37 #define FABRIC_MN_MASTER_ERR_EN_0		0x200
38 #define FABRIC_MN_MASTER_ERR_FORCE_0		0x204
39 #define FABRIC_MN_MASTER_ERR_STATUS_0		0x208
40 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0	0x20c
42 #define FABRIC_MN_MASTER_LOG_ERR_STATUS_0	0x300
43 #define FABRIC_MN_MASTER_LOG_ADDR_LOW_0		0x304
44 #define FABRIC_MN_MASTER_LOG_ADDR_HIGH_0	0x308
45 #define FABRIC_MN_MASTER_LOG_ATTRIBUTES0_0	0x30c
46 #define FABRIC_MN_MASTER_LOG_ATTRIBUTES1_0	0x310
47 #define FABRIC_MN_MASTER_LOG_ATTRIBUTES2_0	0x314
48 #define FABRIC_MN_MASTER_LOG_USER_BITS0_0	0x318
50 #define AXI_SLV_TIMEOUT_STATUS_0_0		0x8
51 #define APB_BLOCK_TMO_STATUS_0			0xc00
52 #define APB_BLOCK_NUM_TMO_OFFSET		0x20
57 #define FAB_EM_EL_FALCONSEC		GENMASK(1, 0)
60 #define FAB_EM_EL_SLAVEID		GENMASK(7, 0)
62 #define FAB_EM_EL_ACCESSID		GENMASK(7, 0)
69 #define FAB_EM_EL_ACCESSTYPE		GENMASK(0, 0)
137 	writel(0x1ff, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0);  in tegra234_cbb_fault_enable()
145 	writel(0x3f, priv->mon + FABRIC_MN_MASTER_ERR_STATUS_0);  in tegra234_cbb_error_clear()
164 	writel(0x1, cbb->regs + cbb->fabric->off_mask_erd);  in tegra234_cbb_mask_serror()
185 	unsigned int block = 0;  in tegra234_cbb_lookup_apbslv()
195 		if (status & BIT(0)) {  in tegra234_cbb_lookup_apbslv()
196 			u32 timeout, clients, client = 0;  in tegra234_cbb_lookup_apbslv()
203 				if (timeout & BIT(0)) {  in tegra234_cbb_lookup_apbslv()
204 					if (clients != 0xffffffff)  in tegra234_cbb_lookup_apbslv()
268 	unsigned int type = 0;  in tegra234_cbb_print_error()
274 		if (status & 0x1)  in tegra234_cbb_print_error()
282 	type = 0;  in tegra234_cbb_print_error()
285 		if (overflow & 0x1)  in tegra234_cbb_print_error()
319 			if ((mstr_id != 0x1) && (mstr_id != 0x2) && (mstr_id != 0xB))  in print_errlog_err()
395 	if (status == 0xffffffff) {  in print_errmonX_info()
410 	cbb->type = 0;  in print_errmonX_info()
413 		if (error & BIT(0)) {  in print_errmonX_info()
433 	return 0;  in print_errmonX_info()
438 	unsigned int index = 0;  in print_err_notifier()
446 		if (status & BIT(0)) {  in print_err_notifier()
473 	return 0;  in print_err_notifier()
481 	int err = 0;  in tegra234_cbb_debugfs_show()
531 			 * If illegal request is from CCPLEX(id:0x1) master then call BUG() to  in tegra234_cbb_isr()
534 			if ((mstr_id == 0x1) && priv->fabric->off_mask_erd)  in tegra234_cbb_isr()
553 		int err = devm_request_irq(cbb->dev, priv->sec_irq, tegra234_cbb_isr, 0,  in tegra234_cbb_interrupt_enable()
562 	return 0;  in tegra234_cbb_interrupt_enable()
582 	[0x00] = "TZ",
583 	[0x01] = "CCPLEX",
584 	[0x02] = "CCPMU",
585 	[0x03] = "BPMP_FW",
586 	[0x04] = "AON",
587 	[0x05] = "SCE",
588 	[0x06] = "GPCDMA_P",
589 	[0x07] = "TSECA_NONSECURE",
590 	[0x08] = "TSECA_LIGHTSECURE",
591 	[0x09] = "TSECA_HEAVYSECURE",
592 	[0x0a] = "CORESIGHT",
593 	[0x0b] = "APE",
594 	[0x0c] = "PEATRANS",
595 	[0x0d] = "JTAGM_DFT",
596 	[0x0e] = "RCE",
597 	[0x0f] = "DCE",
598 	[0x10] = "PSC_FW_USER",
599 	[0x11] = "PSC_FW_SUPERVISOR",
600 	[0x12] = "PSC_FW_MACHINE",
601 	[0x13] = "PSC_BOOT",
602 	[0x14] = "BPMP_BOOT",
603 	[0x15] = "NVDEC_NONSECURE",
604 	[0x16] = "NVDEC_LIGHTSECURE",
605 	[0x17] = "NVDEC_HEAVYSECURE",
606 	[0x18] = "CBB_INTERNAL",
607 	[0x19] = "RSVD"
633 	{ "AXI2APB", 0x00000 },
634 	{ "AST",     0x14000 },
635 	{ "CBB",     0x15000 },
636 	{ "CPU",     0x16000 },
644 	.notifier_offset = 0x17000,
648 	{ "AXI2APB", 0x00000 },
649 	{ "AST0",    0x15000 },
650 	{ "AST1",    0x16000 },
651 	{ "CBB",     0x17000 },
652 	{ "CPU",     0x18000 },
660 	.notifier_offset = 0x19000,
664 	{ "AON",        0x40000 },
665 	{ "BPMP",       0x41000 },
666 	{ "CBB",        0x42000 },
667 	{ "HOST1X",     0x43000 },
668 	{ "STM",        0x44000 },
669 	{ "FSI",        0x45000 },
670 	{ "PSC",        0x46000 },
671 	{ "PCIE_C1",    0x47000 },
672 	{ "PCIE_C2",    0x48000 },
673 	{ "PCIE_C3",    0x49000 },
674 	{ "PCIE_C0",    0x4a000 },
675 	{ "PCIE_C4",    0x4b000 },
676 	{ "GPU",        0x4c000 },
677 	{ "SMMU0",      0x4d000 },
678 	{ "SMMU1",      0x4e000 },
679 	{ "SMMU2",      0x4f000 },
680 	{ "SMMU3",      0x50000 },
681 	{ "SMMU4",      0x51000 },
682 	{ "PCIE_C10",   0x52000 },
683 	{ "PCIE_C7",    0x53000 },
684 	{ "PCIE_C8",    0x54000 },
685 	{ "PCIE_C9",    0x55000 },
686 	{ "PCIE_C5",    0x56000 },
687 	{ "PCIE_C6",    0x57000 },
688 	{ "DCE",        0x58000 },
689 	{ "RCE",        0x59000 },
690 	{ "SCE",        0x5a000 },
691 	{ "AXI2APB_1",  0x70000 },
692 	{ "AXI2APB_10", 0x71000 },
693 	{ "AXI2APB_11", 0x72000 },
694 	{ "AXI2APB_12", 0x73000 },
695 	{ "AXI2APB_13", 0x74000 },
696 	{ "AXI2APB_14", 0x75000 },
697 	{ "AXI2APB_15", 0x76000 },
698 	{ "AXI2APB_16", 0x77000 },
699 	{ "AXI2APB_17", 0x78000 },
700 	{ "AXI2APB_18", 0x79000 },
701 	{ "AXI2APB_19", 0x7a000 },
702 	{ "AXI2APB_2",  0x7b000 },
703 	{ "AXI2APB_20", 0x7c000 },
704 	{ "AXI2APB_21", 0x7d000 },
705 	{ "AXI2APB_22", 0x7e000 },
706 	{ "AXI2APB_23", 0x7f000 },
707 	{ "AXI2APB_25", 0x80000 },
708 	{ "AXI2APB_26", 0x81000 },
709 	{ "AXI2APB_27", 0x82000 },
710 	{ "AXI2APB_28", 0x83000 },
711 	{ "AXI2APB_29", 0x84000 },
712 	{ "AXI2APB_30", 0x85000 },
713 	{ "AXI2APB_31", 0x86000 },
714 	{ "AXI2APB_32", 0x87000 },
715 	{ "AXI2APB_33", 0x88000 },
716 	{ "AXI2APB_34", 0x89000 },
717 	{ "AXI2APB_35", 0x92000 },
718 	{ "AXI2APB_4",  0x8b000 },
719 	{ "AXI2APB_5",  0x8c000 },
720 	{ "AXI2APB_6",  0x8d000 },
721 	{ "AXI2APB_7",  0x8e000 },
722 	{ "AXI2APB_8",  0x8f000 },
723 	{ "AXI2APB_9",  0x90000 },
724 	{ "AXI2APB_3",  0x91000 },
732 	.notifier_offset = 0x60000,
733 	.off_mask_erd = 0x3a004
737 	{ "AXI2APB", 0x00000 },
738 	{ "AST0",    0x15000 },
739 	{ "AST1",    0x16000 },
740 	{ "CPU",     0x18000 },
748 	.notifier_offset = 0x19000,
752 	{ "AXI2APB", 0x00000 },
753 	{ "AST0",    0x15000 },
754 	{ "AST1",    0x16000 },
755 	{ "CPU",     0x18000 },
763 	.notifier_offset = 0x19000,
767 	{ "AXI2APB", 0x00000 },
768 	{ "AST0",    0x15000 },
769 	{ "AST1",    0x16000 },
770 	{ "CBB",     0x17000 },
771 	{ "CPU",     0x18000 },
779 	.notifier_offset = 0x19000,
783 	[0x0] = "TZ",
784 	[0x1] = "CCPLEX",
785 	[0x2] = "CCPMU",
786 	[0x3] = "BPMP_FW",
787 	[0x4] = "PSC_FW_USER",
788 	[0x5] = "PSC_FW_SUPERVISOR",
789 	[0x6] = "PSC_FW_MACHINE",
790 	[0x7] = "PSC_BOOT",
791 	[0x8] = "BPMP_BOOT",
792 	[0x9] = "JTAGM_DFT",
793 	[0xa] = "CORESIGHT",
794 	[0xb] = "GPU",
795 	[0xc] = "PEATRANS",
796 	[0xd ... 0x3f] = "RSVD"
892 	{ "CCPLEX",     0x50000 },
893 	{ "PCIE_C8",    0x51000 },
894 	{ "PCIE_C9",    0x52000 },
895 	{ "RSVD",       0x00000 },
896 	{ "RSVD",       0x00000 },
897 	{ "RSVD",       0x00000 },
898 	{ "RSVD",       0x00000 },
899 	{ "RSVD",       0x00000 },
900 	{ "RSVD",       0x00000 },
901 	{ "RSVD",       0x00000 },
902 	{ "RSVD",       0x00000 },
903 	{ "AON",        0x5b000 },
904 	{ "BPMP",       0x5c000 },
905 	{ "RSVD",       0x00000 },
906 	{ "RSVD",       0x00000 },
907 	{ "PSC",        0x5d000 },
908 	{ "STM",        0x5e000 },
909 	{ "AXI2APB_1",  0x70000 },
910 	{ "AXI2APB_10", 0x71000 },
911 	{ "AXI2APB_11", 0x72000 },
912 	{ "AXI2APB_12", 0x73000 },
913 	{ "AXI2APB_13", 0x74000 },
914 	{ "AXI2APB_14", 0x75000 },
915 	{ "AXI2APB_15", 0x76000 },
916 	{ "AXI2APB_16", 0x77000 },
917 	{ "AXI2APB_17", 0x78000 },
918 	{ "AXI2APB_18", 0x79000 },
919 	{ "AXI2APB_19", 0x7a000 },
920 	{ "AXI2APB_2",  0x7b000 },
921 	{ "AXI2APB_20", 0x7c000 },
922 	{ "AXI2APB_4",  0x87000 },
923 	{ "AXI2APB_5",  0x88000 },
924 	{ "AXI2APB_6",  0x89000 },
925 	{ "AXI2APB_7",  0x8a000 },
926 	{ "AXI2APB_8",  0x8b000 },
927 	{ "AXI2APB_9",  0x8c000 },
928 	{ "AXI2APB_3",  0x8d000 },
929 	{ "AXI2APB_21", 0x7d000 },
930 	{ "AXI2APB_22", 0x7e000 },
931 	{ "AXI2APB_23", 0x7f000 },
932 	{ "AXI2APB_24", 0x80000 },
933 	{ "AXI2APB_25", 0x81000 },
934 	{ "AXI2APB_26", 0x82000 },
935 	{ "AXI2APB_27", 0x83000 },
936 	{ "AXI2APB_28", 0x84000 },
937 	{ "PCIE_C4",    0x53000 },
938 	{ "PCIE_C5",    0x54000 },
939 	{ "PCIE_C6",    0x55000 },
940 	{ "PCIE_C7",    0x56000 },
941 	{ "PCIE_C2",    0x57000 },
942 	{ "PCIE_C3",    0x58000 },
943 	{ "PCIE_C0",    0x59000 },
944 	{ "PCIE_C1",    0x5a000 },
945 	{ "AXI2APB_29", 0x85000 },
946 	{ "AXI2APB_30", 0x86000 },
954 	.notifier_offset = 0x60000,
955 	.off_mask_erd = 0x40004,
959 	{ "RSVD",    0x00000 },
960 	{ "RSVD",    0x00000 },
961 	{ "CBB",     0x15000 },
962 	{ "CPU",     0x16000 },
963 	{ "AXI2APB", 0x00000 },
964 	{ "DBB0",    0x17000 },
965 	{ "DBB1",    0x18000 },
973 	.notifier_offset = 0x19000,
1022 	unsigned long flags = 0;  in tegra234_cbb_probe()
1048 	cbb->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &cbb->res);  in tegra234_cbb_probe()
1071 	return 0;  in tegra234_cbb_remove()
1082 	return 0;  in tegra234_cbb_resume_noirq()