1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <dt-bindings/power/px30-power.h>
22 #include <dt-bindings/power/rockchip,rv1126-power.h>
23 #include <dt-bindings/power/rk3036-power.h>
24 #include <dt-bindings/power/rk3066-power.h>
25 #include <dt-bindings/power/rk3128-power.h>
26 #include <dt-bindings/power/rk3188-power.h>
27 #include <dt-bindings/power/rk3228-power.h>
28 #include <dt-bindings/power/rk3288-power.h>
29 #include <dt-bindings/power/rk3328-power.h>
30 #include <dt-bindings/power/rk3366-power.h>
31 #include <dt-bindings/power/rk3368-power.h>
32 #include <dt-bindings/power/rk3399-power.h>
33 #include <dt-bindings/power/rk3568-power.h>
34 #include <dt-bindings/power/rk3588-power.h>
170  * Dynamic Memory Controller may need to coordinate with us -- see
173  * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
204 	mutex_lock(&pmu->mutex);  in rockchip_pmu_block()
208 	 * enabled for the duration of power-domain transitions. Most  in rockchip_pmu_block()
210 	 * particular, DRAM DVFS / memory-controller idle) must be handled by  in rockchip_pmu_block()
216 	for (i = 0; i < pmu->genpd_data.num_domains; i++) {  in rockchip_pmu_block()
217 		genpd = pmu->genpd_data.domains[i];  in rockchip_pmu_block()
220 			ret = clk_bulk_enable(pd->num_clks, pd->clks);  in rockchip_pmu_block()
222 				dev_err(pmu->dev,  in rockchip_pmu_block()
224 					genpd->name, ret);  in rockchip_pmu_block()
233 	for (i = i - 1; i >= 0; i--) {  in rockchip_pmu_block()
234 		genpd = pmu->genpd_data.domains[i];  in rockchip_pmu_block()
237 			clk_bulk_disable(pd->num_clks, pd->clks);  in rockchip_pmu_block()
240 	mutex_unlock(&pmu->mutex);  in rockchip_pmu_block()
257 		for (i = 0; i < pmu->genpd_data.num_domains; i++) {  in rockchip_pmu_unblock()
258 			genpd = pmu->genpd_data.domains[i];  in rockchip_pmu_unblock()
261 				clk_bulk_disable(pd->num_clks, pd->clks);  in rockchip_pmu_unblock()
265 		mutex_unlock(&pmu->mutex);  in rockchip_pmu_unblock()
277 	struct rockchip_pmu *pmu = pd->pmu;  in rockchip_pmu_domain_is_idle()
278 	const struct rockchip_domain_info *pd_info = pd->info;  in rockchip_pmu_domain_is_idle()
281 	regmap_read(pmu->regmap, pmu->info->idle_offset, &val);  in rockchip_pmu_domain_is_idle()
282 	return (val & pd_info->idle_mask) == pd_info->idle_mask;  in rockchip_pmu_domain_is_idle()
289 	regmap_read(pmu->regmap, pmu->info->ack_offset, &val);  in rockchip_pmu_read_ack()
296 	const struct rockchip_domain_info *pd_info = pd->info;  in rockchip_pmu_set_idle_request()
297 	struct generic_pm_domain *genpd = &pd->genpd;  in rockchip_pmu_set_idle_request()
298 	struct rockchip_pmu *pmu = pd->pmu;  in rockchip_pmu_set_idle_request()
299 	u32 pd_req_offset = pd_info->req_offset;  in rockchip_pmu_set_idle_request()
305 	if (pd_info->req_mask == 0)  in rockchip_pmu_set_idle_request()
307 	else if (pd_info->req_w_mask)  in rockchip_pmu_set_idle_request()
308 		regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset,  in rockchip_pmu_set_idle_request()
309 			     idle ? (pd_info->req_mask | pd_info->req_w_mask) :  in rockchip_pmu_set_idle_request()
310 			     pd_info->req_w_mask);  in rockchip_pmu_set_idle_request()
312 		regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset,  in rockchip_pmu_set_idle_request()
313 				   pd_info->req_mask, idle ? -1U : 0);  in rockchip_pmu_set_idle_request()
318 	target_ack = idle ? pd_info->ack_mask : 0;  in rockchip_pmu_set_idle_request()
320 					(val & pd_info->ack_mask) == target_ack,  in rockchip_pmu_set_idle_request()
323 		dev_err(pmu->dev,  in rockchip_pmu_set_idle_request()
325 			genpd->name, val);  in rockchip_pmu_set_idle_request()
332 		dev_err(pmu->dev,  in rockchip_pmu_set_idle_request()
334 			genpd->name, is_idle);  in rockchip_pmu_set_idle_request()
345 	for (i = 0; i < pd->num_qos; i++) {  in rockchip_pmu_save_qos()
346 		regmap_read(pd->qos_regmap[i],  in rockchip_pmu_save_qos()
348 			    &pd->qos_save_regs[0][i]);  in rockchip_pmu_save_qos()
349 		regmap_read(pd->qos_regmap[i],  in rockchip_pmu_save_qos()
351 			    &pd->qos_save_regs[1][i]);  in rockchip_pmu_save_qos()
352 		regmap_read(pd->qos_regmap[i],  in rockchip_pmu_save_qos()
354 			    &pd->qos_save_regs[2][i]);  in rockchip_pmu_save_qos()
355 		regmap_read(pd->qos_regmap[i],  in rockchip_pmu_save_qos()
357 			    &pd->qos_save_regs[3][i]);  in rockchip_pmu_save_qos()
358 		regmap_read(pd->qos_regmap[i],  in rockchip_pmu_save_qos()
360 			    &pd->qos_save_regs[4][i]);  in rockchip_pmu_save_qos()
369 	for (i = 0; i < pd->num_qos; i++) {  in rockchip_pmu_restore_qos()
370 		regmap_write(pd->qos_regmap[i],  in rockchip_pmu_restore_qos()
372 			     pd->qos_save_regs[0][i]);  in rockchip_pmu_restore_qos()
373 		regmap_write(pd->qos_regmap[i],  in rockchip_pmu_restore_qos()
375 			     pd->qos_save_regs[1][i]);  in rockchip_pmu_restore_qos()
376 		regmap_write(pd->qos_regmap[i],  in rockchip_pmu_restore_qos()
378 			     pd->qos_save_regs[2][i]);  in rockchip_pmu_restore_qos()
379 		regmap_write(pd->qos_regmap[i],  in rockchip_pmu_restore_qos()
381 			     pd->qos_save_regs[3][i]);  in rockchip_pmu_restore_qos()
382 		regmap_write(pd->qos_regmap[i],  in rockchip_pmu_restore_qos()
384 			     pd->qos_save_regs[4][i]);  in rockchip_pmu_restore_qos()
392 	struct rockchip_pmu *pmu = pd->pmu;  in rockchip_pmu_domain_is_on()
395 	if (pd->info->repair_status_mask) {  in rockchip_pmu_domain_is_on()
396 		regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);  in rockchip_pmu_domain_is_on()
398 		return val & pd->info->repair_status_mask;  in rockchip_pmu_domain_is_on()
401 	/* check idle status for idle-only domains */  in rockchip_pmu_domain_is_on()
402 	if (pd->info->status_mask == 0)  in rockchip_pmu_domain_is_on()
405 	regmap_read(pmu->regmap, pmu->info->status_offset, &val);  in rockchip_pmu_domain_is_on()
408 	return !(val & pd->info->status_mask);  in rockchip_pmu_domain_is_on()
414 	struct rockchip_pmu *pmu = pd->pmu;  in rockchip_do_pmu_set_power_domain()
415 	struct generic_pm_domain *genpd = &pd->genpd;  in rockchip_do_pmu_set_power_domain()
416 	u32 pd_pwr_offset = pd->info->pwr_offset;  in rockchip_do_pmu_set_power_domain()
419 	if (pd->info->pwr_mask == 0)  in rockchip_do_pmu_set_power_domain()
421 	else if (pd->info->pwr_w_mask)  in rockchip_do_pmu_set_power_domain()
422 		regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,  in rockchip_do_pmu_set_power_domain()
423 			     on ? pd->info->pwr_w_mask :  in rockchip_do_pmu_set_power_domain()
424 			     (pd->info->pwr_mask | pd->info->pwr_w_mask));  in rockchip_do_pmu_set_power_domain()
426 		regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,  in rockchip_do_pmu_set_power_domain()
427 				   pd->info->pwr_mask, on ? 0 : -1U);  in rockchip_do_pmu_set_power_domain()
433 		dev_err(pmu->dev,  in rockchip_do_pmu_set_power_domain()
435 			genpd->name, is_on);  in rockchip_do_pmu_set_power_domain()
442 	struct rockchip_pmu *pmu = pd->pmu;  in rockchip_pd_power()
445 	mutex_lock(&pmu->mutex);  in rockchip_pd_power()
448 		ret = clk_bulk_enable(pd->num_clks, pd->clks);  in rockchip_pd_power()
450 			dev_err(pmu->dev, "failed to enable clocks\n");  in rockchip_pd_power()
451 			mutex_unlock(&pmu->mutex);  in rockchip_pd_power()
471 		clk_bulk_disable(pd->num_clks, pd->clks);  in rockchip_pd_power()
474 	mutex_unlock(&pmu->mutex);  in rockchip_pd_power()
499 	dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);  in rockchip_pd_attach_dev()
508 	while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {  in rockchip_pd_attach_dev()
525 	dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);  in rockchip_pd_detach_dev()
542 		dev_err(pmu->dev,  in rockchip_pm_add_one_domain()
545 		return -EINVAL;  in rockchip_pm_add_one_domain()
548 	if (id >= pmu->info->num_domains) {  in rockchip_pm_add_one_domain()
549 		dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",  in rockchip_pm_add_one_domain()
551 		return -EINVAL;  in rockchip_pm_add_one_domain()
554 	if (pmu->genpd_data.domains[id])  in rockchip_pm_add_one_domain()
557 	pd_info = &pmu->info->domain_info[id];  in rockchip_pm_add_one_domain()
559 		dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",  in rockchip_pm_add_one_domain()
561 		return -EINVAL;  in rockchip_pm_add_one_domain()
564 	pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);  in rockchip_pm_add_one_domain()
566 		return -ENOMEM;  in rockchip_pm_add_one_domain()
568 	pd->info = pd_info;  in rockchip_pm_add_one_domain()
569 	pd->pmu = pmu;  in rockchip_pm_add_one_domain()
571 	pd->num_clks = of_clk_get_parent_count(node);  in rockchip_pm_add_one_domain()
572 	if (pd->num_clks > 0) {  in rockchip_pm_add_one_domain()
573 		pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,  in rockchip_pm_add_one_domain()
574 					sizeof(*pd->clks), GFP_KERNEL);  in rockchip_pm_add_one_domain()
575 		if (!pd->clks)  in rockchip_pm_add_one_domain()
576 			return -ENOMEM;  in rockchip_pm_add_one_domain()
578 		dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",  in rockchip_pm_add_one_domain()
579 			node, pd->num_clks);  in rockchip_pm_add_one_domain()
580 		pd->num_clks = 0;  in rockchip_pm_add_one_domain()
583 	for (i = 0; i < pd->num_clks; i++) {  in rockchip_pm_add_one_domain()
584 		pd->clks[i].clk = of_clk_get(node, i);  in rockchip_pm_add_one_domain()
585 		if (IS_ERR(pd->clks[i].clk)) {  in rockchip_pm_add_one_domain()
586 			error = PTR_ERR(pd->clks[i].clk);  in rockchip_pm_add_one_domain()
587 			dev_err(pmu->dev,  in rockchip_pm_add_one_domain()
594 	error = clk_bulk_prepare(pd->num_clks, pd->clks);  in rockchip_pm_add_one_domain()
598 	pd->num_qos = of_count_phandle_with_args(node, "pm_qos",  in rockchip_pm_add_one_domain()
601 	if (pd->num_qos > 0) {  in rockchip_pm_add_one_domain()
602 		pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,  in rockchip_pm_add_one_domain()
603 					      sizeof(*pd->qos_regmap),  in rockchip_pm_add_one_domain()
605 		if (!pd->qos_regmap) {  in rockchip_pm_add_one_domain()
606 			error = -ENOMEM;  in rockchip_pm_add_one_domain()
611 			pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,  in rockchip_pm_add_one_domain()
612 							    pd->num_qos,  in rockchip_pm_add_one_domain()
615 			if (!pd->qos_save_regs[j]) {  in rockchip_pm_add_one_domain()
616 				error = -ENOMEM;  in rockchip_pm_add_one_domain()
621 		for (j = 0; j < pd->num_qos; j++) {  in rockchip_pm_add_one_domain()
624 				error = -ENODEV;  in rockchip_pm_add_one_domain()
627 			pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);  in rockchip_pm_add_one_domain()
628 			if (IS_ERR(pd->qos_regmap[j])) {  in rockchip_pm_add_one_domain()
629 				error = -ENODEV;  in rockchip_pm_add_one_domain()
637 	if (pd->info->name)  in rockchip_pm_add_one_domain()
638 		pd->genpd.name = pd->info->name;  in rockchip_pm_add_one_domain()
640 		pd->genpd.name = kbasename(node->full_name);  in rockchip_pm_add_one_domain()
641 	pd->genpd.power_off = rockchip_pd_power_off;  in rockchip_pm_add_one_domain()
642 	pd->genpd.power_on = rockchip_pd_power_on;  in rockchip_pm_add_one_domain()
643 	pd->genpd.attach_dev = rockchip_pd_attach_dev;  in rockchip_pm_add_one_domain()
644 	pd->genpd.detach_dev = rockchip_pd_detach_dev;  in rockchip_pm_add_one_domain()
645 	pd->genpd.flags = GENPD_FLAG_PM_CLK;  in rockchip_pm_add_one_domain()
646 	if (pd_info->active_wakeup)  in rockchip_pm_add_one_domain()
647 		pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;  in rockchip_pm_add_one_domain()
648 	pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));  in rockchip_pm_add_one_domain()
650 	pmu->genpd_data.domains[id] = &pd->genpd;  in rockchip_pm_add_one_domain()
654 	clk_bulk_unprepare(pd->num_clks, pd->clks);  in rockchip_pm_add_one_domain()
656 	clk_bulk_put(pd->num_clks, pd->clks);  in rockchip_pm_add_one_domain()
668 	ret = pm_genpd_remove(&pd->genpd);  in rockchip_pm_remove_one_domain()
670 		dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",  in rockchip_pm_remove_one_domain()
671 			pd->genpd.name, ret);  in rockchip_pm_remove_one_domain()
673 	clk_bulk_unprepare(pd->num_clks, pd->clks);  in rockchip_pm_remove_one_domain()
674 	clk_bulk_put(pd->num_clks, pd->clks);  in rockchip_pm_remove_one_domain()
676 	/* protect the zeroing of pm->num_clks */  in rockchip_pm_remove_one_domain()
677 	mutex_lock(&pd->pmu->mutex);  in rockchip_pm_remove_one_domain()
678 	pd->num_clks = 0;  in rockchip_pm_remove_one_domain()
679 	mutex_unlock(&pd->pmu->mutex);  in rockchip_pm_remove_one_domain()
690 	for (i = 0; i < pmu->genpd_data.num_domains; i++) {  in rockchip_pm_domain_cleanup()
691 		genpd = pmu->genpd_data.domains[i];  in rockchip_pm_domain_cleanup()
706 	regmap_write(pmu->regmap, domain_reg_offset, count);  in rockchip_configure_pd_cnt()
708 	regmap_write(pmu->regmap, domain_reg_offset + 4, count);  in rockchip_configure_pd_cnt()
723 			dev_err(pmu->dev,  in rockchip_pm_add_subdomain()
728 		parent_domain = pmu->genpd_data.domains[idx];  in rockchip_pm_add_subdomain()
732 			dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",  in rockchip_pm_add_subdomain()
739 			dev_err(pmu->dev,  in rockchip_pm_add_subdomain()
744 		child_domain = pmu->genpd_data.domains[idx];  in rockchip_pm_add_subdomain()
748 			dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",  in rockchip_pm_add_subdomain()
749 				parent_domain->name, child_domain->name, error);  in rockchip_pm_add_subdomain()
752 			dev_dbg(pmu->dev, "%s add subdomain: %s\n",  in rockchip_pm_add_subdomain()
753 				parent_domain->name, child_domain->name);  in rockchip_pm_add_subdomain()
768 	struct device *dev = &pdev->dev;  in rockchip_pm_domain_probe()
769 	struct device_node *np = dev->of_node;  in rockchip_pm_domain_probe()
779 		return -ENODEV;  in rockchip_pm_domain_probe()
782 	match = of_match_device(dev->driver->of_match_table, dev);  in rockchip_pm_domain_probe()
783 	if (!match || !match->data) {  in rockchip_pm_domain_probe()
785 		return -EINVAL;  in rockchip_pm_domain_probe()
788 	pmu_info = match->data;  in rockchip_pm_domain_probe()
791 			   struct_size(pmu, domains, pmu_info->num_domains),  in rockchip_pm_domain_probe()
794 		return -ENOMEM;  in rockchip_pm_domain_probe()
796 	pmu->dev = &pdev->dev;  in rockchip_pm_domain_probe()
797 	mutex_init(&pmu->mutex);  in rockchip_pm_domain_probe()
799 	pmu->info = pmu_info;  in rockchip_pm_domain_probe()
801 	pmu->genpd_data.domains = pmu->domains;  in rockchip_pm_domain_probe()
802 	pmu->genpd_data.num_domains = pmu_info->num_domains;  in rockchip_pm_domain_probe()
804 	parent = dev->parent;  in rockchip_pm_domain_probe()
807 		return -ENODEV;  in rockchip_pm_domain_probe()
810 	pmu->regmap = syscon_node_to_regmap(parent->of_node);  in rockchip_pm_domain_probe()
811 	if (IS_ERR(pmu->regmap)) {  in rockchip_pm_domain_probe()
813 		return PTR_ERR(pmu->regmap);  in rockchip_pm_domain_probe()
820 	if (pmu_info->core_power_transition_time)  in rockchip_pm_domain_probe()
821 		rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,  in rockchip_pm_domain_probe()
822 					pmu_info->core_power_transition_time);  in rockchip_pm_domain_probe()
823 	if (pmu_info->gpu_pwrcnt_offset)  in rockchip_pm_domain_probe()
824 		rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,  in rockchip_pm_domain_probe()
825 					pmu_info->gpu_power_transition_time);  in rockchip_pm_domain_probe()
827 	error = -ENODEV;  in rockchip_pm_domain_probe()
858 	error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);  in rockchip_pm_domain_probe()
941 	[RK3228_PD_RKVDEC]	= DOMAIN_RK3036("vdec", BIT(7),  BIT(7),  BIT(23), false),
970 	[RK3366_PD_RKVDEC]	= DOMAIN_RK3368("vdec",   BIT(11), BIT(11), BIT(7), false),
1021 	[RK3568_PD_RKVDEC]	= DOMAIN_RK3568("vdec", BIT(4), BIT(8),  false),
1229 		.compatible = "rockchip,px30-power-controller",
1233 		.compatible = "rockchip,rk3036-power-controller",
1237 		.compatible = "rockchip,rk3066-power-controller",
1241 		.compatible = "rockchip,rk3128-power-controller",
1245 		.compatible = "rockchip,rk3188-power-controller",
1249 		.compatible = "rockchip,rk3228-power-controller",
1253 		.compatible = "rockchip,rk3288-power-controller",
1257 		.compatible = "rockchip,rk3328-power-controller",
1261 		.compatible = "rockchip,rk3366-power-controller",
1265 		.compatible = "rockchip,rk3368-power-controller",
1269 		.compatible = "rockchip,rk3399-power-controller",
1273 		.compatible = "rockchip,rk3568-power-controller",
1277 		.compatible = "rockchip,rk3588-power-controller",
1281 		.compatible = "rockchip,rv1126-power-controller",
1290 		.name   = "rockchip-pm-domain",