199 	writel_relaxed(val, base + SE_IRQ_EN);  in geni_se_io_set_mode()
203 	writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);  in geni_se_io_set_mode()
205 	writel_relaxed(0, base + SE_GSI_EVENT_EN);  in geni_se_io_set_mode()
214 	writel_relaxed(val, base + GENI_CGC_CTRL);  in geni_se_io_init()
219 	writel_relaxed(val, base + SE_DMA_GENERAL_CFG);  in geni_se_io_init()
221 	writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);  in geni_se_io_init()
222 	writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);  in geni_se_io_init()
227 	writel_relaxed(0, se->base + SE_GSI_EVENT_EN);  in geni_se_irq_clear()
228 	writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);  in geni_se_irq_clear()
229 	writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);  in geni_se_irq_clear()
230 	writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);  in geni_se_irq_clear()
231 	writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);  in geni_se_irq_clear()
232 	writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);  in geni_se_irq_clear()
252 	writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);  in geni_se_init()
253 	writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);  in geni_se_init()
257 	writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);  in geni_se_init()
261 	writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);  in geni_se_init()
287 			writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);  in geni_se_select_fifo_mode()
292 			writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);  in geni_se_select_fifo_mode()
298 		writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);  in geni_se_select_fifo_mode()
313 			writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);  in geni_se_select_dma_mode()
318 			writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);  in geni_se_select_dma_mode()
324 		writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);  in geni_se_select_dma_mode()
474 		writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);  in geni_se_config_packing()
475 		writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);  in geni_se_config_packing()
478 		writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);  in geni_se_config_packing()
479 		writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);  in geni_se_config_packing()
490 		writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);  in geni_se_config_packing()
703 	writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);  in geni_se_tx_dma_prep()
704 	writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L);  in geni_se_tx_dma_prep()
705 	writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H);  in geni_se_tx_dma_prep()
706 	writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);  in geni_se_tx_dma_prep()
739 	writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);  in geni_se_rx_dma_prep()
740 	writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L);  in geni_se_rx_dma_prep()
741 	writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H);  in geni_se_rx_dma_prep()
743 	writel_relaxed(0, se->base + SE_DMA_RX_ATTR);  in geni_se_rx_dma_prep()