Lines Matching +full:qup +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
10 #include <linux/dma-mapping.h>
17 #include <linux/qcom-geni-se.h>
23 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
24 * controller. QUP Wrapper is designed to support various serial bus protocols
31 * GENI based QUP is a highly-flexible and programmable module for supporting
33 * QUP module can provide upto 8 serial interfaces, using its internal
41 * +-----------------------------------------+
42 * |QUP Wrapper |
43 * | +----------------------------+ |
44 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
46 * <---Clock Perf.----+ +----+-----------------------+ | |
50 * <--------AHB-------> | | | |
51 * | | +----+ |
54 * <------SE IRQ------+ +----------------------------+ |
56 * +-----------------------------------------+
58 * Figure 1: GENI based QUP Wrapper
62 * master-slave model, primary sequencer drives both TX & RX operations. On
63 * serial interfaces that operate using peer-to-peer model, primary sequencer
72 * geni_wrapper represents QUP Wrapper controller. This part of the driver
73 * manages QUP Wrapper information such as hardware version, clock
77 * engine information such as clocks, containing QUP Wrapper, etc. This part
87 * struct geni_wrapper - Data structure to represent the QUP Wrapper Core
88 * @dev: Device pointer of the QUP wrapper core
89 * @base: Base address of this instance of QUP wrapper core
99 static const char * const icc_path_names[] = {"qup-core", "qup-config",
100 "qup-memory"};
179 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
186 struct geni_wrapper *wrapper = se->wrapper; in geni_se_get_qup_hw_version()
188 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); in geni_se_get_qup_hw_version()
227 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); in geni_se_irq_clear()
228 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); in geni_se_irq_clear()
229 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); in geni_se_irq_clear()
230 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); in geni_se_irq_clear()
231 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); in geni_se_irq_clear()
232 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); in geni_se_irq_clear()
236 * geni_se_init() - Initialize the GENI serial engine
239 * @rx_rfr: Ready-for-receive watermark, in units of FIFO words.
242 * receive watermark and ready-for-receive watermarks.
249 geni_se_io_init(se->base); in geni_se_init()
250 geni_se_io_set_mode(se->base); in geni_se_init()
252 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); in geni_se_init()
253 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); in geni_se_init()
255 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
257 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
259 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
261 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
277 * - The done and TX-related interrupts are managed manually. in geni_se_select_fifo_mode()
278 * - We don't RX from the main sequencer (we use the secondary) so in geni_se_select_fifo_mode()
279 * we don't need the RX-related interrupts enabled in the main in geni_se_select_fifo_mode()
283 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
287 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
289 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_select_fifo_mode()
292 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_fifo_mode()
295 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
298 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
309 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_dma_mode()
313 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_dma_mode()
315 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_select_dma_mode()
318 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_dma_mode()
321 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
324 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
333 writel(0, se->base + SE_IRQ_EN); in geni_se_select_gpi_mode()
335 val = readl(se->base + SE_GENI_S_IRQ_EN); in geni_se_select_gpi_mode()
337 writel(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_gpi_mode()
339 val = readl(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_gpi_mode()
342 writel(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_gpi_mode()
344 writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_gpi_mode()
346 val = readl(se->base + SE_GSI_EVENT_EN); in geni_se_select_gpi_mode()
348 writel(val, se->base + SE_GSI_EVENT_EN); in geni_se_select_gpi_mode()
352 * geni_se_select_mode() - Select the serial engine transfer mode
384 * Refer to below examples for detailed bit-field description.
388 * +-----------+-------+-------+-------+-------+
390 * +-----------+-------+-------+-------+-------+
395 * +-----------+-------+-------+-------+-------+
399 * +-----------+-------+-------+-------+-------+
401 * +-----------+-------+-------+-------+-------+
406 * +-----------+-------+-------+-------+-------+
410 * +-----------+-------+-------+-------+-------+
412 * +-----------+-------+-------+-------+-------+
417 * +-----------+-------+-------+-------+-------+
428 * geni_se_config_packing() - Packing configuration of the serial engine
432 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
445 int idx_start = msb_to_lsb ? bpw - 1 : 0; in geni_se_config_packing()
447 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; in geni_se_config_packing()
456 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; in geni_se_config_packing()
466 temp_bpw = temp_bpw - BITS_PER_BYTE; in geni_se_config_packing()
469 cfg[iter - 1] |= PACKING_STOP_BIT; in geni_se_config_packing()
474 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); in geni_se_config_packing()
475 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); in geni_se_config_packing()
478 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); in geni_se_config_packing()
479 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); in geni_se_config_packing()
484 * 0 - 4x8, four words in each entry, max word size of 8 bits in geni_se_config_packing()
485 * 1 - 2x16, two words in each entry, max word size of 16 bits in geni_se_config_packing()
486 * 2 - 1x32, one word in each entry, max word size of 32 bits in geni_se_config_packing()
487 * 3 - undefined in geni_se_config_packing()
490 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); in geni_se_config_packing()
496 struct geni_wrapper *wrapper = se->wrapper; in geni_se_clks_off()
498 clk_disable_unprepare(se->clk); in geni_se_clks_off()
499 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_off()
500 wrapper->ahb_clks); in geni_se_clks_off()
504 * geni_se_resources_off() - Turn off resources associated with the serial
514 if (has_acpi_companion(se->dev)) in geni_se_resources_off()
517 ret = pinctrl_pm_select_sleep_state(se->dev); in geni_se_resources_off()
529 struct geni_wrapper *wrapper = se->wrapper; in geni_se_clks_on()
531 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_on()
532 wrapper->ahb_clks); in geni_se_clks_on()
536 ret = clk_prepare_enable(se->clk); in geni_se_clks_on()
538 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_on()
539 wrapper->ahb_clks); in geni_se_clks_on()
544 * geni_se_resources_on() - Turn on resources associated with the serial
554 if (has_acpi_companion(se->dev)) in geni_se_resources_on()
561 ret = pinctrl_pm_select_default_state(se->dev); in geni_se_resources_on()
570 * geni_se_clk_tbl_get() - Get the clock table to program DFS
587 if (se->clk_perf_tbl) { in geni_se_clk_tbl_get()
588 *tbl = se->clk_perf_tbl; in geni_se_clk_tbl_get()
589 return se->num_clk_levels; in geni_se_clk_tbl_get()
592 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, in geni_se_clk_tbl_get()
593 sizeof(*se->clk_perf_tbl), in geni_se_clk_tbl_get()
595 if (!se->clk_perf_tbl) in geni_se_clk_tbl_get()
596 return -ENOMEM; in geni_se_clk_tbl_get()
599 freq = clk_round_rate(se->clk, freq + 1); in geni_se_clk_tbl_get()
600 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) in geni_se_clk_tbl_get()
602 se->clk_perf_tbl[i] = freq; in geni_se_clk_tbl_get()
604 se->num_clk_levels = i; in geni_se_clk_tbl_get()
605 *tbl = se->clk_perf_tbl; in geni_se_clk_tbl_get()
606 return se->num_clk_levels; in geni_se_clk_tbl_get()
611 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
624 * - if @exact is true then @res_freq / <an_integer> == @req_freq
625 * - if @exact is false then @res_freq / <an_integer> <= @req_freq
645 return -EINVAL; in geni_se_clk_freq_match()
650 new_delta = req_freq - tbl[i] / divider; in geni_se_clk_freq_match()
666 return -EINVAL; in geni_se_clk_freq_match()
677 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
690 struct geni_wrapper *wrapper = se->wrapper; in geni_se_tx_dma_prep()
694 return -EINVAL; in geni_se_tx_dma_prep()
696 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); in geni_se_tx_dma_prep()
697 if (dma_mapping_error(wrapper->dev, *iova)) in geni_se_tx_dma_prep()
698 return -EIO; in geni_se_tx_dma_prep()
703 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); in geni_se_tx_dma_prep()
704 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); in geni_se_tx_dma_prep()
705 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); in geni_se_tx_dma_prep()
706 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); in geni_se_tx_dma_prep()
707 writel(len, se->base + SE_DMA_TX_LEN); in geni_se_tx_dma_prep()
713 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
726 struct geni_wrapper *wrapper = se->wrapper; in geni_se_rx_dma_prep()
730 return -EINVAL; in geni_se_rx_dma_prep()
732 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); in geni_se_rx_dma_prep()
733 if (dma_mapping_error(wrapper->dev, *iova)) in geni_se_rx_dma_prep()
734 return -EIO; in geni_se_rx_dma_prep()
739 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); in geni_se_rx_dma_prep()
740 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); in geni_se_rx_dma_prep()
741 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); in geni_se_rx_dma_prep()
743 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); in geni_se_rx_dma_prep()
744 writel(len, se->base + SE_DMA_RX_LEN); in geni_se_rx_dma_prep()
750 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
759 struct geni_wrapper *wrapper = se->wrapper; in geni_se_tx_dma_unprep()
761 if (!dma_mapping_error(wrapper->dev, iova)) in geni_se_tx_dma_unprep()
762 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); in geni_se_tx_dma_unprep()
767 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
776 struct geni_wrapper *wrapper = se->wrapper; in geni_se_rx_dma_unprep()
778 if (!dma_mapping_error(wrapper->dev, iova)) in geni_se_rx_dma_unprep()
779 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); in geni_se_rx_dma_unprep()
786 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; in geni_icc_get()
788 if (has_acpi_companion(se->dev)) in geni_icc_get()
791 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_get()
795 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); in geni_icc_get()
796 if (IS_ERR(se->icc_paths[i].path)) in geni_icc_get()
803 err = PTR_ERR(se->icc_paths[i].path); in geni_icc_get()
804 if (err != -EPROBE_DEFER) in geni_icc_get()
805 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", in geni_icc_get()
816 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_set_bw()
817 ret = icc_set_bw(se->icc_paths[i].path, in geni_icc_set_bw()
818 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); in geni_icc_set_bw()
820 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", in geni_icc_set_bw()
834 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) in geni_icc_set_tag()
835 icc_set_tag(se->icc_paths[i].path, tag); in geni_icc_set_tag()
844 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_enable()
845 ret = icc_enable(se->icc_paths[i].path); in geni_icc_enable()
847 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", in geni_icc_enable()
861 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_disable()
862 ret = icc_disable(se->icc_paths[i].path); in geni_icc_disable()
864 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", in geni_icc_disable()
876 struct device *dev = &pdev->dev; in geni_se_probe()
882 return -ENOMEM; in geni_se_probe()
884 wrapper->dev = dev; in geni_se_probe()
885 wrapper->base = devm_platform_ioremap_resource(pdev, 0); in geni_se_probe()
886 if (IS_ERR(wrapper->base)) in geni_se_probe()
887 return PTR_ERR(wrapper->base); in geni_se_probe()
889 if (!has_acpi_companion(&pdev->dev)) { in geni_se_probe()
890 wrapper->ahb_clks[0].id = "m-ahb"; in geni_se_probe()
891 wrapper->ahb_clks[1].id = "s-ahb"; in geni_se_probe()
892 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); in geni_se_probe()
905 { .compatible = "qcom,geni-se-qup", },