492 static void svs_writel_relaxed(struct svs_platform *svsp, u32 val,  in svs_writel_relaxed()  function
502 	svs_writel_relaxed(svsp, svsb->core_sel, CORESEL);  in svs_switch_bank()
726 		svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);  in svs_enable_debug_write()
727 		svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);  in svs_enable_debug_write()
1031 	svs_writel_relaxed(svsp, freq_pct74, FREQPCT74);  in svs_set_bank_freq_pct_v3()
1032 	svs_writel_relaxed(svsp, freq_pct30, FREQPCT30);  in svs_set_bank_freq_pct_v3()
1084 	svs_writel_relaxed(svsp, freqpct74_val, FREQPCT74);  in svs_set_bank_freq_pct_v2()
1085 	svs_writel_relaxed(svsp, freqpct30_val, FREQPCT30);  in svs_set_bank_freq_pct_v2()
1098 	svs_writel_relaxed(svsp, des_char, DESCHAR);  in svs_set_bank_phase()
1103 	svs_writel_relaxed(svsp, temp_char, TEMPCHAR);  in svs_set_bank_phase()
1107 	svs_writel_relaxed(svsp, det_char, DETCHAR);  in svs_set_bank_phase()
1109 	svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG);  in svs_set_bank_phase()
1110 	svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG);  in svs_set_bank_phase()
1111 	svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG);  in svs_set_bank_phase()
1119 	svs_writel_relaxed(svsp, limit_vals, LIMITVALS);  in svs_set_bank_phase()
1121 	svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW);  in svs_set_bank_phase()
1122 	svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG);  in svs_set_bank_phase()
1123 	svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT);  in svs_set_bank_phase()
1124 	svs_writel_relaxed(svsp, svsb->ctl0, CTL0);  in svs_set_bank_phase()
1125 	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);  in svs_set_bank_phase()
1129 		svs_writel_relaxed(svsp, svsb->vboot, VBOOT);  in svs_set_bank_phase()
1130 		svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);  in svs_set_bank_phase()
1131 		svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN);  in svs_set_bank_phase()
1136 		svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);  in svs_set_bank_phase()
1137 		svs_writel_relaxed(svsp, init2vals, INIT2VALS);  in svs_set_bank_phase()
1138 		svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, SVSEN);  in svs_set_bank_phase()
1143 		svs_writel_relaxed(svsp, ts_calcs, TSCALCS);  in svs_set_bank_phase()
1144 		svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN);  in svs_set_bank_phase()
1145 		svs_writel_relaxed(svsp, SVSB_PTPEN_MON, SVSEN);  in svs_set_bank_phase()
1181 	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);  in svs_error_isr_handler()
1182 	svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);  in svs_error_isr_handler()
1207 	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);  in svs_init01_isr_handler()
1208 	svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);  in svs_init01_isr_handler()
1226 	svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);  in svs_init02_isr_handler()
1227 	svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);  in svs_init02_isr_handler()
1240 	svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS);  in svs_mon_mode_isr_handler()
1559 		svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);  in svs_suspend()
1560 		svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);  in svs_suspend()