34 /* svs bank 1-line software id */
40 /* svs bank 2-line type */
44 /* svs bank mode support */
50 /* svs bank volt flags */
57 /* svs bank register fields and common configuration */
130 /* svs bank related setting */
175  * enum svsb_phase - svs bank phase enumeration
176  * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition
177  * @SVSB_PHASE_INIT01: svs bank basic init for data calibration
178  * @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table
179  * @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect
180  * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose)
182  * Each svs bank has its own independent phase and we enable each svs bank by
183  * running their phase orderly. However, when svs bank encounters unexpected
184  * condition, it will fire an irq (PHASE_ERROR) to inform svs software.
186  * svs bank general phase-enabled order:
313  * struct svs_platform - svs platform control
314  * @name: svs platform name
315  * @base: svs platform register base
316  * @dev: svs platform device
317  * @main_clk: main clock for svs bank
318  * @pbank: svs bank pointer needing to be protected by spin_lock section
319  * @banks: svs banks that svs platform supports
320  * @rst: svs platform reset control
321  * @efuse_parsing: svs platform efuse parsing function pointer
322  * @probe: svs platform probe function pointer
323  * @efuse_max: total number of svs efuse
325  * @regs: svs platform registers map
326  * @bank_max: total number of svs banks
327  * @efuse: svs efuse data received from NVMEM framework
358  * struct svs_bank - svs bank representation
398  * @cpu_id: cpu core id for SVS CPU bank use only
405  * @bts: svs efuse data
406  * @mts: svs efuse data
407  * @bdes: svs efuse data
408  * @mdes: svs efuse data
409  * @mtdes: svs efuse data
410  * @dcbdet: svs efuse data
411  * @dcmdet: svs efuse data
415  * Svs bank will generate suitalbe voltages by below general math equation
783 	const char *d = "/sys/kernel/debug/svs";  in svs_create_debug_cmds()
800 	svs_dir = debugfs_create_dir("svs", NULL);  in svs_create_debug_cmds()
1257 		/* Find out which svs bank fires interrupt */  in svs_isr()
1302 	 /* Svs bank init01 preparation - power enable */  in svs_init01()
1336 	 * Svs bank init01 preparation - vboot voltage adjustment  in svs_init01()
1337 	 * Sometimes two svs banks use the same buck. Therefore,  in svs_init01()
1338 	 * we have to set each svs bank to target voltage(vboot) first.  in svs_init01()
1384 	/* Svs bank init01 begins */  in svs_init01()
1585 		dev_err(svsp->dev, "cannot enable main_clk, disable svs\n");  in svs_resume()
1751 	/* Svs efuse parsing */  in svs_mt8192_efuse_parsing()
1818 	/* Svs efuse parsing */  in svs_mt8183_efuse_parsing()
1995 	/* Get svs efuse by nvmem */  in svs_is_efuse_data_correct()
1996 	cell = nvmem_cell_get(svsp->dev, "svs-calibration-data");  in svs_is_efuse_data_correct()
1998 		dev_err(svsp->dev, "no \"svs-calibration-data\"? %ld\n",  in svs_is_efuse_data_correct()
2005 		dev_err(svsp->dev, "cannot read svs efuse: %ld\n",  in svs_is_efuse_data_correct()
2078 				     "cannot get svs reset control\n");  in svs_mt8192_platform_probe()
2301 	.name = "mt8192-svs",
2310 	.name = "mt8183-svs",
2320 		.compatible = "mediatek,mt8192-svs",
2323 		.compatible = "mediatek,mt8183-svs",
2338 		dev_err(&pdev->dev, "no svs platform data?\n");  in svs_platform_probe()
2378 		dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret);  in svs_probe()
2412 		dev_err(svsp->dev, "cannot find svs register base\n");  in svs_probe()
2419 		dev_err(svsp->dev, "svs start fail: %d\n", ret);  in svs_probe()
2425 		dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret);  in svs_probe()
2451 		.name		= "mtk-svs",
2460 MODULE_DESCRIPTION("MediaTek SVS driver");