Lines Matching +full:100 +full:base +full:- +full:fx
1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/nvmem-consumer.h>
34 /* svs bank 1-line software id */
40 /* svs bank 2-line type */
146 inode->i_private); \
161 inode->i_private); \
175 * enum svsb_phase - svs bank phase enumeration
186 * svs bank general phase-enabled order:
187 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON
313 * struct svs_platform - svs platform control
315 * @base: svs platform register base
332 void __iomem *base; member
358 * struct svs_bank - svs bank representation
376 * @turn_freq_base: refenrece frequency for 2-line turn point
383 * @volt_base: bank voltage base
399 * @ctl0: TS-x selection
412 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank
413 * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank
480 /* If not divide 1000, "numerator * 100" will have data overflow. */ in percent()
484 return DIV_ROUND_UP(numerator * 100, denominator); in percent()
489 return readl_relaxed(svsp->base + svsp->regs[rg_i]); in svs_readl_relaxed()
495 writel_relaxed(val, svsp->base + svsp->regs[rg_i]); in svs_writel_relaxed()
500 struct svs_bank *svsb = svsp->pbank; in svs_switch_bank()
502 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL); in svs_switch_bank()
514 return (opp_u_volt - svsb_volt_base) / svsb_volt_step; in svs_opp_volt_to_bank_volt()
522 for (i = 0; i < svsb->opp_count; i++) { in svs_sync_bank_volts_from_opp()
523 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, in svs_sync_bank_volts_from_opp()
524 svsb->opp_dfreq[i], in svs_sync_bank_volts_from_opp()
527 dev_err(svsb->dev, "cannot find freq = %u (%ld)\n", in svs_sync_bank_volts_from_opp()
528 svsb->opp_dfreq[i], PTR_ERR(opp)); in svs_sync_bank_volts_from_opp()
533 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt, in svs_sync_bank_volts_from_opp()
534 svsb->volt_step, in svs_sync_bank_volts_from_opp()
535 svsb->volt_base); in svs_sync_bank_volts_from_opp()
544 int ret = -EPERM, tzone_temp = 0; in svs_adjust_pm_opp_volts()
547 mutex_lock(&svsb->lock); in svs_adjust_pm_opp_volts()
550 * 2-line bank updates its corresponding opp volts. in svs_adjust_pm_opp_volts()
551 * 1-line bank updates all opp volts. in svs_adjust_pm_opp_volts()
553 if (svsb->type == SVSB_HIGH) { in svs_adjust_pm_opp_volts()
555 opp_stop = svsb->turn_pt; in svs_adjust_pm_opp_volts()
556 } else if (svsb->type == SVSB_LOW) { in svs_adjust_pm_opp_volts()
557 opp_start = svsb->turn_pt; in svs_adjust_pm_opp_volts()
558 opp_stop = svsb->opp_count; in svs_adjust_pm_opp_volts()
561 opp_stop = svsb->opp_count; in svs_adjust_pm_opp_volts()
565 if (svsb->phase == SVSB_PHASE_MON) { in svs_adjust_pm_opp_volts()
566 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); in svs_adjust_pm_opp_volts()
567 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && in svs_adjust_pm_opp_volts()
568 svsb->temp < SVSB_TEMP_LOWER_BOUND)) { in svs_adjust_pm_opp_volts()
569 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n", in svs_adjust_pm_opp_volts()
570 svsb->tzone_name, ret, svsb->temp); in svs_adjust_pm_opp_volts()
571 svsb->phase = SVSB_PHASE_ERROR; in svs_adjust_pm_opp_volts()
574 if (tzone_temp >= svsb->tzone_htemp) in svs_adjust_pm_opp_volts()
575 temp_voffset += svsb->tzone_htemp_voffset; in svs_adjust_pm_opp_volts()
576 else if (tzone_temp <= svsb->tzone_ltemp) in svs_adjust_pm_opp_volts()
577 temp_voffset += svsb->tzone_ltemp_voffset; in svs_adjust_pm_opp_volts()
579 /* 2-line bank update all opp volts when running mon mode */ in svs_adjust_pm_opp_volts()
580 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { in svs_adjust_pm_opp_volts()
582 opp_stop = svsb->opp_count; in svs_adjust_pm_opp_volts()
588 switch (svsb->phase) { in svs_adjust_pm_opp_volts()
590 opp_volt = svsb->opp_dvolt[i]; in svs_adjust_pm_opp_volts()
596 svsb_volt = max(svsb->volt[i], svsb->vmin); in svs_adjust_pm_opp_volts()
598 svsb->volt_step, in svs_adjust_pm_opp_volts()
599 svsb->volt_base); in svs_adjust_pm_opp_volts()
602 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); in svs_adjust_pm_opp_volts()
604 svsb->volt_step, in svs_adjust_pm_opp_volts()
605 svsb->volt_base); in svs_adjust_pm_opp_volts()
608 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase); in svs_adjust_pm_opp_volts()
609 ret = -EINVAL; in svs_adjust_pm_opp_volts()
613 opp_volt = min(opp_volt, svsb->opp_dvolt[i]); in svs_adjust_pm_opp_volts()
614 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, in svs_adjust_pm_opp_volts()
615 svsb->opp_dfreq[i], in svs_adjust_pm_opp_volts()
617 svsb->opp_dvolt[i]); in svs_adjust_pm_opp_volts()
619 dev_err(svsb->dev, "set %uuV fail: %d\n", in svs_adjust_pm_opp_volts()
626 mutex_unlock(&svsb->lock); in svs_adjust_pm_opp_volts()
633 struct svs_platform *svsp = (struct svs_platform *)m->private; in svs_dump_debug_show()
638 for (i = 0; i < svsp->efuse_max; i++) in svs_dump_debug_show()
639 if (svsp->efuse && svsp->efuse[i]) in svs_dump_debug_show()
641 i, svsp->efuse[i]); in svs_dump_debug_show()
643 for (i = 0; i < svsp->tefuse_max; i++) in svs_dump_debug_show()
644 if (svsp->tefuse) in svs_dump_debug_show()
646 i, svsp->tefuse[i]); in svs_dump_debug_show()
648 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) { in svs_dump_debug_show()
649 svsb = &svsp->banks[idx]; in svs_dump_debug_show()
662 svs_reg_addr = (unsigned long)(svsp->base + in svs_dump_debug_show()
663 svsp->regs[j]); in svs_dump_debug_show()
665 svs_reg_addr, svsb->reg_data[i][j]); in svs_dump_debug_show()
677 struct svs_bank *svsb = (struct svs_bank *)m->private; in svs_enable_debug_show()
679 switch (svsb->phase) { in svs_enable_debug_show()
704 struct svs_bank *svsb = file_inode(filp)->i_private; in svs_enable_debug_write()
705 struct svs_platform *svsp = dev_get_drvdata(svsb->dev); in svs_enable_debug_write()
711 return -EINVAL; in svs_enable_debug_write()
723 svsp->pbank = svsb; in svs_enable_debug_write()
724 svsb->mode_support = SVSB_MODE_ALL_DISABLE; in svs_enable_debug_write()
730 svsb->phase = SVSB_PHASE_ERROR; in svs_enable_debug_write()
743 struct svs_bank *svsb = (struct svs_bank *)m->private; in svs_status_debug_show()
748 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); in svs_status_debug_show()
751 svsb->name, svsb->turn_pt); in svs_status_debug_show()
754 svsb->name, tzone_temp, svsb->turn_pt); in svs_status_debug_show()
756 for (i = 0; i < svsb->opp_count; i++) { in svs_status_debug_show()
757 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev, in svs_status_debug_show()
758 svsb->opp_dfreq[i], true); in svs_status_debug_show()
761 svsb->name, svsb->opp_dfreq[i], in svs_status_debug_show()
767 i, svsb->opp_dfreq[i], i, in svs_status_debug_show()
770 i, svsb->volt[i], i, svsb->freq_pct[i]); in svs_status_debug_show()
802 dev_err(svsp->dev, "cannot create %s: %ld\n", in svs_create_debug_cmds()
812 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", in svs_create_debug_cmds()
818 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_create_debug_cmds()
819 svsb = &svsp->banks[idx]; in svs_create_debug_cmds()
821 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) in svs_create_debug_cmds()
824 svsb_dir = debugfs_create_dir(svsb->name, svs_dir); in svs_create_debug_cmds()
826 dev_err(svsp->dev, "cannot create %s/%s: %ld\n", in svs_create_debug_cmds()
827 d, svsb->name, PTR_ERR(svsb_dir)); in svs_create_debug_cmds()
836 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n", in svs_create_debug_cmds()
837 d, svsb->name, svsb_entries[i].name, in svs_create_debug_cmds()
847 static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx) in interpolate() argument
854 /* *100 to have decimal fraction factor */ in interpolate()
855 vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx)); in interpolate()
857 return DIV_ROUND_UP(vx, 100); in interpolate()
862 struct svs_bank *svsb = svsp->pbank; in svs_get_bank_volts_v3()
863 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt; in svs_get_bank_volts_v3()
865 u32 middle_index = (svsb->opp_count / 2); in svs_get_bank_volts_v3()
867 if (svsb->phase == SVSB_PHASE_MON && in svs_get_bank_volts_v3()
868 svsb->volt_flags & SVSB_MON_VOLT_IGNORE) in svs_get_bank_volts_v3()
874 /* Target is to set svsb->volt[] by algorithm */ in svs_get_bank_volts_v3()
876 if (svsb->type == SVSB_HIGH) { in svs_get_bank_volts_v3()
877 /* volt[0] ~ volt[turn_pt - 1] */ in svs_get_bank_volts_v3()
882 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
885 } else if (svsb->type == SVSB_LOW) { in svs_get_bank_volts_v3()
886 /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */ in svs_get_bank_volts_v3()
887 j = svsb->opp_count - 7; in svs_get_bank_volts_v3()
888 svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); in svs_get_bank_volts_v3()
890 for (i = j; i < svsb->opp_count; i++) { in svs_get_bank_volts_v3()
894 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
898 /* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */ in svs_get_bank_volts_v3()
900 svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt], in svs_get_bank_volts_v3()
901 svsb->freq_pct[j], in svs_get_bank_volts_v3()
902 svsb->volt[turn_pt], in svs_get_bank_volts_v3()
903 svsb->volt[j], in svs_get_bank_volts_v3()
904 svsb->freq_pct[i]); in svs_get_bank_volts_v3()
907 if (svsb->type == SVSB_HIGH) { in svs_get_bank_volts_v3()
908 /* volt[0] + volt[j] ~ volt[turn_pt - 1] */ in svs_get_bank_volts_v3()
909 j = turn_pt - 7; in svs_get_bank_volts_v3()
910 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30); in svs_get_bank_volts_v3()
916 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
920 /* volt[1] ~ volt[j - 1] by interpolate */ in svs_get_bank_volts_v3()
922 svsb->volt[i] = interpolate(svsb->freq_pct[0], in svs_get_bank_volts_v3()
923 svsb->freq_pct[j], in svs_get_bank_volts_v3()
924 svsb->volt[0], in svs_get_bank_volts_v3()
925 svsb->volt[j], in svs_get_bank_volts_v3()
926 svsb->freq_pct[i]); in svs_get_bank_volts_v3()
927 } else if (svsb->type == SVSB_LOW) { in svs_get_bank_volts_v3()
928 /* volt[turn_pt] ~ volt[opp_count - 1] */ in svs_get_bank_volts_v3()
929 for (i = turn_pt; i < svsb->opp_count; i++) { in svs_get_bank_volts_v3()
933 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0); in svs_get_bank_volts_v3()
939 if (svsb->type == SVSB_HIGH) { in svs_get_bank_volts_v3()
941 opp_stop = svsb->turn_pt; in svs_get_bank_volts_v3()
942 } else if (svsb->type == SVSB_LOW) { in svs_get_bank_volts_v3()
943 opp_start = svsb->turn_pt; in svs_get_bank_volts_v3()
944 opp_stop = svsb->opp_count; in svs_get_bank_volts_v3()
948 if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) in svs_get_bank_volts_v3()
949 svsb->volt[i] -= svsb->dvt_fixed; in svs_get_bank_volts_v3()
954 struct svs_bank *svsb = svsp->pbank; in svs_set_bank_freq_pct_v3()
957 u32 middle_index = (svsb->opp_count / 2); in svs_set_bank_freq_pct_v3()
959 for (i = 0; i < svsb->opp_count; i++) { in svs_set_bank_freq_pct_v3()
960 if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) { in svs_set_bank_freq_pct_v3()
961 svsb->turn_pt = i; in svs_set_bank_freq_pct_v3()
966 turn_pt = svsb->turn_pt; in svs_set_bank_freq_pct_v3()
970 if (svsb->type == SVSB_HIGH) { in svs_set_bank_freq_pct_v3()
977 freq_pct30 = svsb->freq_pct[0]; in svs_set_bank_freq_pct_v3()
979 /* freq_pct[0] ~ freq_pct[turn_pt - 1] */ in svs_set_bank_freq_pct_v3()
984 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
987 } else if (svsb->type == SVSB_LOW) { in svs_set_bank_freq_pct_v3()
990 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1] in svs_set_bank_freq_pct_v3()
992 freq_pct30 = svsb->freq_pct[turn_pt]; in svs_set_bank_freq_pct_v3()
994 j = svsb->opp_count - 7; in svs_set_bank_freq_pct_v3()
995 for (i = j; i < svsb->opp_count; i++) { in svs_set_bank_freq_pct_v3()
999 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
1004 if (svsb->type == SVSB_HIGH) { in svs_set_bank_freq_pct_v3()
1007 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1] in svs_set_bank_freq_pct_v3()
1009 freq_pct30 = svsb->freq_pct[0]; in svs_set_bank_freq_pct_v3()
1011 j = turn_pt - 7; in svs_set_bank_freq_pct_v3()
1016 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
1019 } else if (svsb->type == SVSB_LOW) { in svs_set_bank_freq_pct_v3()
1020 /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */ in svs_set_bank_freq_pct_v3()
1021 for (i = turn_pt; i < svsb->opp_count; i++) { in svs_set_bank_freq_pct_v3()
1025 *freq_pct |= (svsb->freq_pct[i] << b_sft); in svs_set_bank_freq_pct_v3()
1037 struct svs_bank *svsb = svsp->pbank; in svs_get_bank_volts_v2()
1041 svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); in svs_get_bank_volts_v2()
1042 svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); in svs_get_bank_volts_v2()
1043 svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); in svs_get_bank_volts_v2()
1044 svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); in svs_get_bank_volts_v2()
1047 svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp); in svs_get_bank_volts_v2()
1048 svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp); in svs_get_bank_volts_v2()
1049 svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp); in svs_get_bank_volts_v2()
1050 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp); in svs_get_bank_volts_v2()
1053 svsb->volt[i + 1] = interpolate(svsb->freq_pct[i], in svs_get_bank_volts_v2()
1054 svsb->freq_pct[i + 2], in svs_get_bank_volts_v2()
1055 svsb->volt[i], in svs_get_bank_volts_v2()
1056 svsb->volt[i + 2], in svs_get_bank_volts_v2()
1057 svsb->freq_pct[i + 1]); in svs_get_bank_volts_v2()
1059 svsb->volt[15] = interpolate(svsb->freq_pct[12], in svs_get_bank_volts_v2()
1060 svsb->freq_pct[14], in svs_get_bank_volts_v2()
1061 svsb->volt[12], in svs_get_bank_volts_v2()
1062 svsb->volt[14], in svs_get_bank_volts_v2()
1063 svsb->freq_pct[15]); in svs_get_bank_volts_v2()
1065 for (i = 0; i < svsb->opp_count; i++) in svs_get_bank_volts_v2()
1066 svsb->volt[i] += svsb->volt_od; in svs_get_bank_volts_v2()
1071 struct svs_bank *svsb = svsp->pbank; in svs_set_bank_freq_pct_v2()
1074 freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) | in svs_set_bank_freq_pct_v2()
1075 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) | in svs_set_bank_freq_pct_v2()
1076 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) | in svs_set_bank_freq_pct_v2()
1077 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]); in svs_set_bank_freq_pct_v2()
1079 freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) | in svs_set_bank_freq_pct_v2()
1080 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) | in svs_set_bank_freq_pct_v2()
1081 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) | in svs_set_bank_freq_pct_v2()
1082 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]); in svs_set_bank_freq_pct_v2()
1091 struct svs_bank *svsb = svsp->pbank; in svs_set_bank_phase()
1096 des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) | in svs_set_bank_phase()
1097 FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes); in svs_set_bank_phase()
1100 temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) | in svs_set_bank_phase()
1101 FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) | in svs_set_bank_phase()
1102 FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed); in svs_set_bank_phase()
1105 det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) | in svs_set_bank_phase()
1106 FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet); in svs_set_bank_phase()
1109 svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG); in svs_set_bank_phase()
1110 svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG); in svs_set_bank_phase()
1113 svsb->set_freq_pct(svsp); in svs_set_bank_phase()
1117 FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) | in svs_set_bank_phase()
1118 FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax); in svs_set_bank_phase()
1123 svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT); in svs_set_bank_phase()
1124 svs_writel_relaxed(svsp, svsb->ctl0, CTL0); in svs_set_bank_phase()
1129 svs_writel_relaxed(svsp, svsb->vboot, VBOOT); in svs_set_bank_phase()
1134 init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) | in svs_set_bank_phase()
1135 FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in); in svs_set_bank_phase()
1141 ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) | in svs_set_bank_phase()
1142 FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts); in svs_set_bank_phase()
1148 dev_err(svsb->dev, "requested unknown target phase: %u\n", in svs_set_bank_phase()
1157 struct svs_bank *svsb = svsp->pbank; in svs_save_bank_register_data()
1161 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i); in svs_save_bank_register_data()
1166 struct svs_bank *svsb = svsp->pbank; in svs_error_isr_handler()
1168 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n", in svs_error_isr_handler()
1170 dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n", in svs_error_isr_handler()
1173 dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n", in svs_error_isr_handler()
1176 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP)); in svs_error_isr_handler()
1180 svsb->phase = SVSB_PHASE_ERROR; in svs_error_isr_handler()
1187 struct svs_bank *svsb = svsp->pbank; in svs_init01_isr_handler()
1189 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n", in svs_init01_isr_handler()
1196 svsb->phase = SVSB_PHASE_INIT01; in svs_init01_isr_handler()
1197 svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) & in svs_init01_isr_handler()
1199 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE || in svs_init01_isr_handler()
1200 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT && in svs_init01_isr_handler()
1201 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY)) in svs_init01_isr_handler()
1202 svsb->dc_voffset_in = 0; in svs_init01_isr_handler()
1204 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) & in svs_init01_isr_handler()
1209 svsb->core_sel &= ~SVSB_DET_CLK_EN; in svs_init01_isr_handler()
1214 struct svs_bank *svsb = svsp->pbank; in svs_init02_isr_handler()
1216 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n", in svs_init02_isr_handler()
1223 svsb->phase = SVSB_PHASE_INIT02; in svs_init02_isr_handler()
1224 svsb->get_volts(svsp); in svs_init02_isr_handler()
1232 struct svs_bank *svsb = svsp->pbank; in svs_mon_mode_isr_handler()
1236 svsb->phase = SVSB_PHASE_MON; in svs_mon_mode_isr_handler()
1237 svsb->get_volts(svsp); in svs_mon_mode_isr_handler()
1239 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0); in svs_mon_mode_isr_handler()
1250 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_isr()
1251 svsb = &svsp->banks[idx]; in svs_isr()
1252 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name); in svs_isr()
1255 svsp->pbank = svsb; in svs_isr()
1258 if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) { in svs_isr()
1284 if (svsb->phase == SVSB_PHASE_INIT01 || in svs_isr()
1285 svsb->phase == SVSB_PHASE_INIT02) in svs_isr()
1286 complete(&svsb->init_completion); in svs_isr()
1302 /* Svs bank init01 preparation - power enable */ in svs_init01()
1303 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1304 svsb = &svsp->banks[idx]; in svs_init01()
1306 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1309 ret = regulator_enable(svsb->buck); in svs_init01()
1311 dev_err(svsb->dev, "%s enable fail: %d\n", in svs_init01()
1312 svsb->buck_name, ret); in svs_init01()
1317 ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST); in svs_init01()
1319 dev_notice(svsb->dev, "set fast mode fail: %d\n", ret); in svs_init01()
1321 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { in svs_init01()
1322 if (!pm_runtime_enabled(svsb->opp_dev)) { in svs_init01()
1323 pm_runtime_enable(svsb->opp_dev); in svs_init01()
1324 svsb->pm_runtime_enabled_count++; in svs_init01()
1327 ret = pm_runtime_get_sync(svsb->opp_dev); in svs_init01()
1329 dev_err(svsb->dev, "mtcmos on fail: %d\n", ret); in svs_init01()
1336 * Svs bank init01 preparation - vboot voltage adjustment in svs_init01()
1340 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1341 svsb = &svsp->banks[idx]; in svs_init01()
1343 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1351 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, in svs_init01()
1352 svsb->volt_step, in svs_init01()
1353 svsb->volt_base); in svs_init01()
1355 for (i = 0; i < svsb->opp_count; i++) { in svs_init01()
1356 opp_freq = svsb->opp_dfreq[i]; in svs_init01()
1357 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) { in svs_init01()
1358 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev, in svs_init01()
1364 dev_err(svsb->dev, in svs_init01()
1372 ret = dev_pm_opp_disable(svsb->opp_dev, in svs_init01()
1373 svsb->opp_dfreq[i]); in svs_init01()
1375 dev_err(svsb->dev, in svs_init01()
1377 svsb->opp_dfreq[i], ret); in svs_init01()
1385 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1386 svsb = &svsp->banks[idx]; in svs_init01()
1388 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1391 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot, in svs_init01()
1392 svsb->volt_step, in svs_init01()
1393 svsb->volt_base); in svs_init01()
1395 buck_volt = regulator_get_voltage(svsb->buck); in svs_init01()
1397 dev_err(svsb->dev, in svs_init01()
1400 ret = -EPERM; in svs_init01()
1405 svsp->pbank = svsb; in svs_init01()
1409 time_left = wait_for_completion_timeout(&svsb->init_completion, in svs_init01()
1412 dev_err(svsb->dev, "init01 completion timeout\n"); in svs_init01()
1413 ret = -EBUSY; in svs_init01()
1419 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init01()
1420 svsb = &svsp->banks[idx]; in svs_init01()
1422 if (!(svsb->mode_support & SVSB_MODE_INIT01)) in svs_init01()
1425 for (i = 0; i < svsb->opp_count; i++) { in svs_init01()
1426 r = dev_pm_opp_enable(svsb->opp_dev, in svs_init01()
1427 svsb->opp_dfreq[i]); in svs_init01()
1429 dev_err(svsb->dev, "opp %uHz enable fail: %d\n", in svs_init01()
1430 svsb->opp_dfreq[i], r); in svs_init01()
1433 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) { in svs_init01()
1434 r = pm_runtime_put_sync(svsb->opp_dev); in svs_init01()
1436 dev_err(svsb->dev, "mtcmos off fail: %d\n", r); in svs_init01()
1438 if (svsb->pm_runtime_enabled_count > 0) { in svs_init01()
1439 pm_runtime_disable(svsb->opp_dev); in svs_init01()
1440 svsb->pm_runtime_enabled_count--; in svs_init01()
1444 r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL); in svs_init01()
1446 dev_notice(svsb->dev, "set normal mode fail: %d\n", r); in svs_init01()
1448 r = regulator_disable(svsb->buck); in svs_init01()
1450 dev_err(svsb->dev, "%s disable fail: %d\n", in svs_init01()
1451 svsb->buck_name, r); in svs_init01()
1466 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init02()
1467 svsb = &svsp->banks[idx]; in svs_init02()
1469 if (!(svsb->mode_support & SVSB_MODE_INIT02)) in svs_init02()
1472 reinit_completion(&svsb->init_completion); in svs_init02()
1474 svsp->pbank = svsb; in svs_init02()
1478 time_left = wait_for_completion_timeout(&svsb->init_completion, in svs_init02()
1481 dev_err(svsb->dev, "init02 completion timeout\n"); in svs_init02()
1482 return -EBUSY; in svs_init02()
1487 * 2-line high/low bank update its corresponding opp voltages only. in svs_init02()
1491 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_init02()
1492 svsb = &svsp->banks[idx]; in svs_init02()
1494 if (!(svsb->mode_support & SVSB_MODE_INIT02)) in svs_init02()
1497 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { in svs_init02()
1499 dev_err(svsb->dev, "sync volt fail\n"); in svs_init02()
1500 return -EPERM; in svs_init02()
1514 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mon_mode()
1515 svsb = &svsp->banks[idx]; in svs_mon_mode()
1517 if (!(svsb->mode_support & SVSB_MODE_MON)) in svs_mon_mode()
1521 svsp->pbank = svsb; in svs_mon_mode()
1552 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_suspend()
1553 svsb = &svsp->banks[idx]; in svs_suspend()
1557 svsp->pbank = svsb; in svs_suspend()
1563 svsb->phase = SVSB_PHASE_ERROR; in svs_suspend()
1567 ret = reset_control_assert(svsp->rst); in svs_suspend()
1569 dev_err(svsp->dev, "cannot assert reset %d\n", ret); in svs_suspend()
1573 clk_disable_unprepare(svsp->main_clk); in svs_suspend()
1583 ret = clk_prepare_enable(svsp->main_clk); in svs_resume()
1585 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n"); in svs_resume()
1589 ret = reset_control_deassert(svsp->rst); in svs_resume()
1591 dev_err(svsp->dev, "cannot deassert reset %d\n", ret); in svs_resume()
1604 clk_disable_unprepare(svsp->main_clk); in svs_resume()
1616 dev_set_drvdata(svsp->dev, svsp); in svs_bank_resource_setup()
1618 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_bank_resource_setup()
1619 svsb = &svsp->banks[idx]; in svs_bank_resource_setup()
1621 switch (svsb->sw_id) { in svs_bank_resource_setup()
1623 svsb->name = "SVSB_CPU_LITTLE"; in svs_bank_resource_setup()
1626 svsb->name = "SVSB_CPU_BIG"; in svs_bank_resource_setup()
1629 svsb->name = "SVSB_CCI"; in svs_bank_resource_setup()
1632 if (svsb->type == SVSB_HIGH) in svs_bank_resource_setup()
1633 svsb->name = "SVSB_GPU_HIGH"; in svs_bank_resource_setup()
1634 else if (svsb->type == SVSB_LOW) in svs_bank_resource_setup()
1635 svsb->name = "SVSB_GPU_LOW"; in svs_bank_resource_setup()
1637 svsb->name = "SVSB_GPU"; in svs_bank_resource_setup()
1640 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); in svs_bank_resource_setup()
1641 return -EINVAL; in svs_bank_resource_setup()
1644 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev), in svs_bank_resource_setup()
1646 if (!svsb->dev) in svs_bank_resource_setup()
1647 return -ENOMEM; in svs_bank_resource_setup()
1649 ret = dev_set_name(svsb->dev, "%s", svsb->name); in svs_bank_resource_setup()
1653 dev_set_drvdata(svsb->dev, svsp); in svs_bank_resource_setup()
1655 ret = devm_pm_opp_of_add_table(svsb->opp_dev); in svs_bank_resource_setup()
1657 dev_err(svsb->dev, "add opp table fail: %d\n", ret); in svs_bank_resource_setup()
1661 mutex_init(&svsb->lock); in svs_bank_resource_setup()
1662 init_completion(&svsb->init_completion); in svs_bank_resource_setup()
1664 if (svsb->mode_support & SVSB_MODE_INIT01) { in svs_bank_resource_setup()
1665 svsb->buck = devm_regulator_get_optional(svsb->opp_dev, in svs_bank_resource_setup()
1666 svsb->buck_name); in svs_bank_resource_setup()
1667 if (IS_ERR(svsb->buck)) { in svs_bank_resource_setup()
1668 dev_err(svsb->dev, "cannot get \"%s-supply\"\n", in svs_bank_resource_setup()
1669 svsb->buck_name); in svs_bank_resource_setup()
1670 return PTR_ERR(svsb->buck); in svs_bank_resource_setup()
1674 if (svsb->mode_support & SVSB_MODE_MON) { in svs_bank_resource_setup()
1675 svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name); in svs_bank_resource_setup()
1676 if (IS_ERR(svsb->tzd)) { in svs_bank_resource_setup()
1677 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", in svs_bank_resource_setup()
1678 svsb->tzone_name); in svs_bank_resource_setup()
1679 return PTR_ERR(svsb->tzd); in svs_bank_resource_setup()
1683 count = dev_pm_opp_get_opp_count(svsb->opp_dev); in svs_bank_resource_setup()
1684 if (svsb->opp_count != count) { in svs_bank_resource_setup()
1685 dev_err(svsb->dev, in svs_bank_resource_setup()
1687 svsb->opp_count, count); in svs_bank_resource_setup()
1691 for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) { in svs_bank_resource_setup()
1692 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq); in svs_bank_resource_setup()
1694 dev_err(svsb->dev, "cannot find freq = %ld\n", in svs_bank_resource_setup()
1699 svsb->opp_dfreq[i] = freq; in svs_bank_resource_setup()
1700 svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp); in svs_bank_resource_setup()
1701 svsb->freq_pct[i] = percent(svsb->opp_dfreq[i], in svs_bank_resource_setup()
1702 svsb->freq_base); in svs_bank_resource_setup()
1715 cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); in svs_thermal_efuse_get_data()
1717 dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", PTR_ERR(cell)); in svs_thermal_efuse_get_data()
1721 svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); in svs_thermal_efuse_get_data()
1722 if (IS_ERR(svsp->tefuse)) { in svs_thermal_efuse_get_data()
1723 dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", in svs_thermal_efuse_get_data()
1724 PTR_ERR(svsp->tefuse)); in svs_thermal_efuse_get_data()
1726 return PTR_ERR(svsp->tefuse); in svs_thermal_efuse_get_data()
1729 svsp->tefuse_max /= sizeof(u32); in svs_thermal_efuse_get_data()
1741 for (i = 0; i < svsp->efuse_max; i++) in svs_mt8192_efuse_parsing()
1742 if (svsp->efuse[i]) in svs_mt8192_efuse_parsing()
1743 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", in svs_mt8192_efuse_parsing()
1744 i, svsp->efuse[i]); in svs_mt8192_efuse_parsing()
1746 if (!svsp->efuse[9]) { in svs_mt8192_efuse_parsing()
1747 dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n"); in svs_mt8192_efuse_parsing()
1752 vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); in svs_mt8192_efuse_parsing()
1754 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8192_efuse_parsing()
1755 svsb = &svsp->banks[idx]; in svs_mt8192_efuse_parsing()
1758 svsb->vmin = 0x1e; in svs_mt8192_efuse_parsing()
1760 if (svsb->type == SVSB_LOW) { in svs_mt8192_efuse_parsing()
1761 svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1762 svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1763 svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1764 svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1765 svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1766 } else if (svsb->type == SVSB_HIGH) { in svs_mt8192_efuse_parsing()
1767 svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1768 svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1769 svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1770 svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1771 svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1774 svsb->vmax += svsb->dvt_fixed; in svs_mt8192_efuse_parsing()
1781 for (i = 0; i < svsp->tefuse_max; i++) in svs_mt8192_efuse_parsing()
1782 if (svsp->tefuse[i] != 0) in svs_mt8192_efuse_parsing()
1785 if (i == svsp->tefuse_max) in svs_mt8192_efuse_parsing()
1788 golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); in svs_mt8192_efuse_parsing()
1790 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8192_efuse_parsing()
1791 svsb = &svsp->banks[idx]; in svs_mt8192_efuse_parsing()
1792 svsb->mts = 500; in svs_mt8192_efuse_parsing()
1793 svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; in svs_mt8192_efuse_parsing()
1808 for (i = 0; i < svsp->efuse_max; i++) in svs_mt8183_efuse_parsing()
1809 if (svsp->efuse[i]) in svs_mt8183_efuse_parsing()
1810 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", in svs_mt8183_efuse_parsing()
1811 i, svsp->efuse[i]); in svs_mt8183_efuse_parsing()
1813 if (!svsp->efuse[2]) { in svs_mt8183_efuse_parsing()
1814 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n"); in svs_mt8183_efuse_parsing()
1819 ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0); in svs_mt8183_efuse_parsing()
1821 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_efuse_parsing()
1822 svsb = &svsp->banks[idx]; in svs_mt8183_efuse_parsing()
1825 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; in svs_mt8183_efuse_parsing()
1827 switch (svsb->sw_id) { in svs_mt8183_efuse_parsing()
1829 svsb->bdes = svsp->efuse[16] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1830 svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1831 svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1832 svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1833 svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1836 svsb->volt_od += 10; in svs_mt8183_efuse_parsing()
1838 svsb->volt_od += 2; in svs_mt8183_efuse_parsing()
1841 svsb->bdes = svsp->efuse[18] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1842 svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1843 svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1844 svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1845 svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1848 svsb->volt_od += 15; in svs_mt8183_efuse_parsing()
1850 svsb->volt_od += 12; in svs_mt8183_efuse_parsing()
1853 svsb->bdes = svsp->efuse[4] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1854 svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1855 svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1856 svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1857 svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1860 svsb->volt_od += 10; in svs_mt8183_efuse_parsing()
1862 svsb->volt_od += 2; in svs_mt8183_efuse_parsing()
1865 svsb->bdes = svsp->efuse[6] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1866 svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1867 svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1868 svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1869 svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0); in svs_mt8183_efuse_parsing()
1872 svsb->freq_base = 800000000; /* 800MHz */ in svs_mt8183_efuse_parsing()
1873 svsb->dvt_fixed = 2; in svs_mt8183_efuse_parsing()
1877 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); in svs_mt8183_efuse_parsing()
1887 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0); in svs_mt8183_efuse_parsing()
1888 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0); in svs_mt8183_efuse_parsing()
1890 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1891 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1892 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1893 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1894 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1895 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0); in svs_mt8183_efuse_parsing()
1897 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0); in svs_mt8183_efuse_parsing()
1898 adc_cali_en_t = svsp->tefuse[0] & BIT(0); in svs_mt8183_efuse_parsing()
1899 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0); in svs_mt8183_efuse_parsing()
1901 ts_id = (svsp->tefuse[1] >> 9) & BIT(0); in svs_mt8183_efuse_parsing()
1902 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0); in svs_mt8183_efuse_parsing()
1910 o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 || in svs_mt8183_efuse_parsing()
1911 o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 || in svs_mt8183_efuse_parsing()
1912 o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 || in svs_mt8183_efuse_parsing()
1913 o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 || in svs_mt8183_efuse_parsing()
1914 o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 || in svs_mt8183_efuse_parsing()
1915 o_vtsabb < -8 || o_vtsabb > 484 || in svs_mt8183_efuse_parsing()
1917 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n"); in svs_mt8183_efuse_parsing()
1921 dev_err(svsp->dev, "no thermal efuse, no mon mode\n"); in svs_mt8183_efuse_parsing()
1925 ge = ((adc_ge_t - 512) * 10000) / 4096; in svs_mt8183_efuse_parsing()
1926 oe = (adc_oe_t - 512); in svs_mt8183_efuse_parsing()
1929 format[0] = (o_vtsmcu[0] + 3350 - oe); in svs_mt8183_efuse_parsing()
1930 format[1] = (o_vtsmcu[1] + 3350 - oe); in svs_mt8183_efuse_parsing()
1931 format[2] = (o_vtsmcu[2] + 3350 - oe); in svs_mt8183_efuse_parsing()
1932 format[3] = (o_vtsmcu[3] + 3350 - oe); in svs_mt8183_efuse_parsing()
1933 format[4] = (o_vtsmcu[4] + 3350 - oe); in svs_mt8183_efuse_parsing()
1934 format[5] = (o_vtsabb + 3350 - oe); in svs_mt8183_efuse_parsing()
1944 mts = (temp0 * 10) / (1534 - o_slope * 10); in svs_mt8183_efuse_parsing()
1946 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_efuse_parsing()
1947 svsb = &svsp->banks[idx]; in svs_mt8183_efuse_parsing()
1948 svsb->mts = mts; in svs_mt8183_efuse_parsing()
1950 switch (svsb->sw_id) { in svs_mt8183_efuse_parsing()
1964 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); in svs_mt8183_efuse_parsing()
1973 temp2 = temp1 * 100 / (1534 + o_slope * 10); in svs_mt8183_efuse_parsing()
1975 temp2 = temp1 * 100 / (1534 - o_slope * 10); in svs_mt8183_efuse_parsing()
1977 svsb->bts = (temp0 + temp2 - 250) * 4 / 10; in svs_mt8183_efuse_parsing()
1983 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_efuse_parsing()
1984 svsb = &svsp->banks[idx]; in svs_mt8183_efuse_parsing()
1985 svsb->mode_support &= ~SVSB_MODE_MON; in svs_mt8183_efuse_parsing()
1996 cell = nvmem_cell_get(svsp->dev, "svs-calibration-data"); in svs_is_efuse_data_correct()
1998 dev_err(svsp->dev, "no \"svs-calibration-data\"? %ld\n", in svs_is_efuse_data_correct()
2003 svsp->efuse = nvmem_cell_read(cell, &svsp->efuse_max); in svs_is_efuse_data_correct()
2004 if (IS_ERR(svsp->efuse)) { in svs_is_efuse_data_correct()
2005 dev_err(svsp->dev, "cannot read svs efuse: %ld\n", in svs_is_efuse_data_correct()
2006 PTR_ERR(svsp->efuse)); in svs_is_efuse_data_correct()
2011 svsp->efuse_max /= sizeof(u32); in svs_is_efuse_data_correct()
2014 return svsp->efuse_parsing(svsp); in svs_is_efuse_data_correct()
2025 dev_err(svsp->dev, "cannot find %s node\n", node_name); in svs_get_subsys_device()
2026 return ERR_PTR(-ENODEV); in svs_get_subsys_device()
2032 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name); in svs_get_subsys_device()
2033 return ERR_PTR(-ENXIO); in svs_get_subsys_device()
2038 return &pdev->dev; in svs_get_subsys_device()
2048 dev_err(svsp->dev, "node name cannot be null\n"); in svs_add_device_link()
2049 return ERR_PTR(-EINVAL); in svs_add_device_link()
2056 sup_link = device_link_add(svsp->dev, dev, in svs_add_device_link()
2059 dev_err(svsp->dev, "sup_link is NULL\n"); in svs_add_device_link()
2060 return ERR_PTR(-EINVAL); in svs_add_device_link()
2063 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND) in svs_add_device_link()
2064 return ERR_PTR(-EPROBE_DEFER); in svs_add_device_link()
2075 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); in svs_mt8192_platform_probe()
2076 if (IS_ERR(svsp->rst)) in svs_mt8192_platform_probe()
2077 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), in svs_mt8192_platform_probe()
2082 return dev_err_probe(svsp->dev, PTR_ERR(dev), in svs_mt8192_platform_probe()
2085 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8192_platform_probe()
2086 svsb = &svsp->banks[idx]; in svs_mt8192_platform_probe()
2088 if (svsb->type == SVSB_HIGH) in svs_mt8192_platform_probe()
2089 svsb->opp_dev = svs_add_device_link(svsp, "mali"); in svs_mt8192_platform_probe()
2090 else if (svsb->type == SVSB_LOW) in svs_mt8192_platform_probe()
2091 svsb->opp_dev = svs_get_subsys_device(svsp, "mali"); in svs_mt8192_platform_probe()
2093 if (IS_ERR(svsb->opp_dev)) in svs_mt8192_platform_probe()
2094 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), in svs_mt8192_platform_probe()
2110 return dev_err_probe(svsp->dev, PTR_ERR(dev), in svs_mt8183_platform_probe()
2113 for (idx = 0; idx < svsp->bank_max; idx++) { in svs_mt8183_platform_probe()
2114 svsb = &svsp->banks[idx]; in svs_mt8183_platform_probe()
2116 switch (svsb->sw_id) { in svs_mt8183_platform_probe()
2119 svsb->opp_dev = get_cpu_device(svsb->cpu_id); in svs_mt8183_platform_probe()
2122 svsb->opp_dev = svs_add_device_link(svsp, "cci"); in svs_mt8183_platform_probe()
2125 svsb->opp_dev = svs_add_device_link(svsp, "gpu"); in svs_mt8183_platform_probe()
2128 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); in svs_mt8183_platform_probe()
2129 return -EINVAL; in svs_mt8183_platform_probe()
2132 if (IS_ERR(svsb->opp_dev)) in svs_mt8183_platform_probe()
2133 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), in svs_mt8183_platform_probe()
2301 .name = "mt8192-svs",
2310 .name = "mt8183-svs",
2320 .compatible = "mediatek,mt8192-svs",
2323 .compatible = "mediatek,mt8183-svs",
2336 svsp_data = of_device_get_match_data(&pdev->dev); in svs_platform_probe()
2338 dev_err(&pdev->dev, "no svs platform data?\n"); in svs_platform_probe()
2339 return ERR_PTR(-EPERM); in svs_platform_probe()
2342 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL); in svs_platform_probe()
2344 return ERR_PTR(-ENOMEM); in svs_platform_probe()
2346 svsp->dev = &pdev->dev; in svs_platform_probe()
2347 svsp->name = svsp_data->name; in svs_platform_probe()
2348 svsp->banks = svsp_data->banks; in svs_platform_probe()
2349 svsp->efuse_parsing = svsp_data->efuse_parsing; in svs_platform_probe()
2350 svsp->probe = svsp_data->probe; in svs_platform_probe()
2351 svsp->regs = svsp_data->regs; in svs_platform_probe()
2352 svsp->bank_max = svsp_data->bank_max; in svs_platform_probe()
2354 ret = svsp->probe(svsp); in svs_platform_probe()
2371 dev_notice(svsp->dev, "efuse data isn't correct\n"); in svs_probe()
2372 ret = -EPERM; in svs_probe()
2378 dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret); in svs_probe()
2388 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr, in svs_probe()
2389 IRQF_ONESHOT, svsp->name, svsp); in svs_probe()
2391 dev_err(svsp->dev, "register irq(%d) failed: %d\n", in svs_probe()
2396 svsp->main_clk = devm_clk_get(svsp->dev, "main"); in svs_probe()
2397 if (IS_ERR(svsp->main_clk)) { in svs_probe()
2398 dev_err(svsp->dev, "failed to get clock: %ld\n", in svs_probe()
2399 PTR_ERR(svsp->main_clk)); in svs_probe()
2400 ret = PTR_ERR(svsp->main_clk); in svs_probe()
2404 ret = clk_prepare_enable(svsp->main_clk); in svs_probe()
2406 dev_err(svsp->dev, "cannot enable main clk: %d\n", ret); in svs_probe()
2410 svsp->base = of_iomap(svsp->dev->of_node, 0); in svs_probe()
2411 if (IS_ERR_OR_NULL(svsp->base)) { in svs_probe()
2412 dev_err(svsp->dev, "cannot find svs register base\n"); in svs_probe()
2413 ret = -EINVAL; in svs_probe()
2419 dev_err(svsp->dev, "svs start fail: %d\n", ret); in svs_probe()
2425 dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret); in svs_probe()
2432 iounmap(svsp->base); in svs_probe()
2435 clk_disable_unprepare(svsp->main_clk); in svs_probe()
2438 if (!IS_ERR_OR_NULL(svsp->efuse)) in svs_probe()
2439 kfree(svsp->efuse); in svs_probe()
2440 if (!IS_ERR_OR_NULL(svsp->tefuse)) in svs_probe()
2441 kfree(svsp->tefuse); in svs_probe()
2451 .name = "mtk-svs",