34 	void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
35 	void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
56 	struct imx8mp_blk_ctrl *bc;  member
64 	void (*power_off) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
65 	void (*power_on) (struct imx8mp_blk_ctrl *bc, struct imx8mp_blk_ctrl_domain *domain);
76 static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,  in imx8mp_hsio_blk_ctrl_power_on()  argument
81 		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);  in imx8mp_hsio_blk_ctrl_power_on()
84 		regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);  in imx8mp_hsio_blk_ctrl_power_on()
87 		regmap_set_bits(bc->regmap, GPR_REG0,  in imx8mp_hsio_blk_ctrl_power_on()
95 static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,  in imx8mp_hsio_blk_ctrl_power_off()  argument
100 		regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);  in imx8mp_hsio_blk_ctrl_power_off()
103 		regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);  in imx8mp_hsio_blk_ctrl_power_off()
106 		regmap_clear_bits(bc->regmap, GPR_REG0,  in imx8mp_hsio_blk_ctrl_power_off()
117 	struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,  in imx8mp_hsio_power_notifier()  local
119 	struct clk_bulk_data *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clks;  in imx8mp_hsio_power_notifier()
120 	int num_clks = bc->domains[IMX8MP_HSIOBLK_PD_USB].data->num_clks;  in imx8mp_hsio_power_notifier()
132 		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);  in imx8mp_hsio_power_notifier()
136 		regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);  in imx8mp_hsio_power_notifier()
145 		regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);  in imx8mp_hsio_power_notifier()
205 static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,  in imx8mp_hdmi_blk_ctrl_power_on()  argument
210 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));  in imx8mp_hdmi_blk_ctrl_power_on()
211 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));  in imx8mp_hdmi_blk_ctrl_power_on()
214 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,  in imx8mp_hdmi_blk_ctrl_power_on()
217 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));  in imx8mp_hdmi_blk_ctrl_power_on()
218 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,  in imx8mp_hdmi_blk_ctrl_power_on()
222 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));  in imx8mp_hdmi_blk_ctrl_power_on()
223 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));  in imx8mp_hdmi_blk_ctrl_power_on()
226 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));  in imx8mp_hdmi_blk_ctrl_power_on()
227 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));  in imx8mp_hdmi_blk_ctrl_power_on()
230 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));  in imx8mp_hdmi_blk_ctrl_power_on()
231 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));  in imx8mp_hdmi_blk_ctrl_power_on()
234 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,  in imx8mp_hdmi_blk_ctrl_power_on()
236 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1,  in imx8mp_hdmi_blk_ctrl_power_on()
239 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0,  in imx8mp_hdmi_blk_ctrl_power_on()
241 		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));  in imx8mp_hdmi_blk_ctrl_power_on()
244 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));  in imx8mp_hdmi_blk_ctrl_power_on()
245 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));  in imx8mp_hdmi_blk_ctrl_power_on()
246 		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));  in imx8mp_hdmi_blk_ctrl_power_on()
249 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));  in imx8mp_hdmi_blk_ctrl_power_on()
252 		regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));  in imx8mp_hdmi_blk_ctrl_power_on()
253 		regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));  in imx8mp_hdmi_blk_ctrl_power_on()
260 static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,  in imx8mp_hdmi_blk_ctrl_power_off()  argument
265 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9));  in imx8mp_hdmi_blk_ctrl_power_off()
266 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16));  in imx8mp_hdmi_blk_ctrl_power_off()
269 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,  in imx8mp_hdmi_blk_ctrl_power_off()
271 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11));  in imx8mp_hdmi_blk_ctrl_power_off()
272 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,  in imx8mp_hdmi_blk_ctrl_power_off()
277 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18));  in imx8mp_hdmi_blk_ctrl_power_off()
278 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17));  in imx8mp_hdmi_blk_ctrl_power_off()
281 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22));  in imx8mp_hdmi_blk_ctrl_power_off()
282 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28));  in imx8mp_hdmi_blk_ctrl_power_off()
285 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20));  in imx8mp_hdmi_blk_ctrl_power_off()
286 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30));  in imx8mp_hdmi_blk_ctrl_power_off()
289 		regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1));  in imx8mp_hdmi_blk_ctrl_power_off()
290 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0,  in imx8mp_hdmi_blk_ctrl_power_off()
292 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1,  in imx8mp_hdmi_blk_ctrl_power_off()
295 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0,  in imx8mp_hdmi_blk_ctrl_power_off()
299 		regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));  in imx8mp_hdmi_blk_ctrl_power_off()
300 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));  in imx8mp_hdmi_blk_ctrl_power_off()
301 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));  in imx8mp_hdmi_blk_ctrl_power_off()
304 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));  in imx8mp_hdmi_blk_ctrl_power_off()
307 		regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));  in imx8mp_hdmi_blk_ctrl_power_off()
308 		regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));  in imx8mp_hdmi_blk_ctrl_power_off()
318 	struct imx8mp_blk_ctrl *bc = container_of(nb, struct imx8mp_blk_ctrl,  in imx8mp_hdmi_power_notifier()  local
330 	regmap_write(bc->regmap, HDMI_RTX_RESET_CTL0, 0x0);  in imx8mp_hdmi_power_notifier()
331 	regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0);  in imx8mp_hdmi_power_notifier()
332 	regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0);  in imx8mp_hdmi_power_notifier()
333 	regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0,  in imx8mp_hdmi_power_notifier()
335 	regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0));  in imx8mp_hdmi_power_notifier()
423 	struct imx8mp_blk_ctrl *bc = domain->bc;  in imx8mp_blk_ctrl_power_on()  local
427 	ret = pm_runtime_resume_and_get(bc->bus_power_dev);  in imx8mp_blk_ctrl_power_on()
429 		dev_err(bc->dev, "failed to power up bus domain\n");  in imx8mp_blk_ctrl_power_on()
436 		dev_err(bc->dev, "failed to enable clocks\n");  in imx8mp_blk_ctrl_power_on()
441 	bc->power_on(bc, domain);  in imx8mp_blk_ctrl_power_on()
446 		dev_err(bc->dev, "failed to power up peripheral domain\n");  in imx8mp_blk_ctrl_power_on()
452 		dev_err(bc->dev, "failed to set icc bw\n");  in imx8mp_blk_ctrl_power_on()
461 	pm_runtime_put(bc->bus_power_dev);  in imx8mp_blk_ctrl_power_on()
470 	struct imx8mp_blk_ctrl *bc = domain->bc;  in imx8mp_blk_ctrl_power_off()  local
475 		dev_err(bc->dev, "failed to enable clocks\n");  in imx8mp_blk_ctrl_power_off()
480 	bc->power_off(bc, domain);  in imx8mp_blk_ctrl_power_off()
488 	pm_runtime_put(bc->bus_power_dev);  in imx8mp_blk_ctrl_power_off()
499 	struct imx8mp_blk_ctrl *bc;  in imx8mp_blk_ctrl_probe()  local
509 	bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);  in imx8mp_blk_ctrl_probe()
510 	if (!bc)  in imx8mp_blk_ctrl_probe()
513 	bc->dev = dev;  in imx8mp_blk_ctrl_probe()
523 	bc->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);  in imx8mp_blk_ctrl_probe()
524 	if (IS_ERR(bc->regmap))  in imx8mp_blk_ctrl_probe()
525 		return dev_err_probe(dev, PTR_ERR(bc->regmap),  in imx8mp_blk_ctrl_probe()
528 	bc->domains = devm_kcalloc(dev, num_domains,  in imx8mp_blk_ctrl_probe()
531 	if (!bc->domains)  in imx8mp_blk_ctrl_probe()
534 	bc->onecell_data.num_domains = num_domains;  in imx8mp_blk_ctrl_probe()
535 	bc->onecell_data.domains =  in imx8mp_blk_ctrl_probe()
538 	if (!bc->onecell_data.domains)  in imx8mp_blk_ctrl_probe()
541 	bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");  in imx8mp_blk_ctrl_probe()
542 	if (IS_ERR(bc->bus_power_dev))  in imx8mp_blk_ctrl_probe()
543 		return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),  in imx8mp_blk_ctrl_probe()
546 	bc->power_off = bc_data->power_off;  in imx8mp_blk_ctrl_probe()
547 	bc->power_on = bc_data->power_on;  in imx8mp_blk_ctrl_probe()
551 		struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];  in imx8mp_blk_ctrl_probe()
598 		domain->bc = bc;  in imx8mp_blk_ctrl_probe()
621 		bc->onecell_data.domains[i] = &domain->genpd;  in imx8mp_blk_ctrl_probe()
624 	ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);  in imx8mp_blk_ctrl_probe()
630 	bc->power_nb.notifier_call = bc_data->power_notifier_fn;  in imx8mp_blk_ctrl_probe()
631 	ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);  in imx8mp_blk_ctrl_probe()
637 	dev_set_drvdata(dev, bc);  in imx8mp_blk_ctrl_probe()
645 		pm_genpd_remove(&bc->domains[i].genpd);  in imx8mp_blk_ctrl_probe()
646 		dev_pm_domain_detach(bc->domains[i].power_dev, true);  in imx8mp_blk_ctrl_probe()
649 	dev_pm_domain_detach(bc->bus_power_dev, true);  in imx8mp_blk_ctrl_probe()
656 	struct imx8mp_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);  in imx8mp_blk_ctrl_remove()  local
661 	for (i = 0; bc->onecell_data.num_domains; i++) {  in imx8mp_blk_ctrl_remove()
662 		struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];  in imx8mp_blk_ctrl_remove()
668 	dev_pm_genpd_remove_notifier(bc->bus_power_dev);  in imx8mp_blk_ctrl_remove()
670 	dev_pm_domain_detach(bc->bus_power_dev, true);  in imx8mp_blk_ctrl_remove()
678 	struct imx8mp_blk_ctrl *bc = dev_get_drvdata(dev);  in imx8mp_blk_ctrl_suspend()  local
689 	ret = pm_runtime_get_sync(bc->bus_power_dev);  in imx8mp_blk_ctrl_suspend()
691 		pm_runtime_put_noidle(bc->bus_power_dev);  in imx8mp_blk_ctrl_suspend()
695 	for (i = 0; i < bc->onecell_data.num_domains; i++) {  in imx8mp_blk_ctrl_suspend()
696 		struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i];  in imx8mp_blk_ctrl_suspend()
709 		pm_runtime_put(bc->domains[i].power_dev);  in imx8mp_blk_ctrl_suspend()
711 	pm_runtime_put(bc->bus_power_dev);  in imx8mp_blk_ctrl_suspend()
718 	struct imx8mp_blk_ctrl *bc = dev_get_drvdata(dev);  in imx8mp_blk_ctrl_resume()  local
721 	for (i = 0; i < bc->onecell_data.num_domains; i++)  in imx8mp_blk_ctrl_resume()
722 		pm_runtime_put(bc->domains[i].power_dev);  in imx8mp_blk_ctrl_resume()
724 	pm_runtime_put(bc->bus_power_dev);  in imx8mp_blk_ctrl_resume()