Lines Matching +full:axi +full:- +full:usb2 +full:- +full:device
1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/device.h>
17 #include <dt-bindings/power/imx8mp-power.h>
28 struct device *dev;
30 struct device *bus_power_dev;
55 struct device *power_dev;
79 switch (domain->id) { in imx8mp_hsio_blk_ctrl_power_on()
81 regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); in imx8mp_hsio_blk_ctrl_power_on()
84 regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN); in imx8mp_hsio_blk_ctrl_power_on()
87 regmap_set_bits(bc->regmap, GPR_REG0, in imx8mp_hsio_blk_ctrl_power_on()
98 switch (domain->id) { in imx8mp_hsio_blk_ctrl_power_off()
100 regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); in imx8mp_hsio_blk_ctrl_power_off()
103 regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN); in imx8mp_hsio_blk_ctrl_power_off()
106 regmap_clear_bits(bc->regmap, GPR_REG0, in imx8mp_hsio_blk_ctrl_power_off()
119 struct clk_bulk_data *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clks; in imx8mp_hsio_power_notifier()
120 int num_clks = bc->domains[IMX8MP_HSIOBLK_PD_USB].data->num_clks; in imx8mp_hsio_power_notifier()
126 * enable USB clock for a moment for the power-on ADB handshake in imx8mp_hsio_power_notifier()
132 regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); in imx8mp_hsio_power_notifier()
136 regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); in imx8mp_hsio_power_notifier()
140 /* enable USB clock for the power-down ADB handshake to work */ in imx8mp_hsio_power_notifier()
145 regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); in imx8mp_hsio_power_notifier()
159 .name = "hsioblk-usb",
163 .path_names = (const char *[]){"usb1", "usb2"},
167 .name = "hsioblk-usb-phy1",
168 .gpc_name = "usb-phy1",
171 .name = "hsioblk-usb-phy2",
172 .gpc_name = "usb-phy2",
175 .name = "hsioblk-pcie",
179 .path_names = (const char *[]){"noc-pcie", "pcie"},
183 .name = "hsioblk-pcie-phy",
184 .gpc_name = "pcie-phy",
208 switch (domain->id) { in imx8mp_hdmi_blk_ctrl_power_on()
210 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9)); in imx8mp_hdmi_blk_ctrl_power_on()
211 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16)); in imx8mp_hdmi_blk_ctrl_power_on()
214 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, in imx8mp_hdmi_blk_ctrl_power_on()
217 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11)); in imx8mp_hdmi_blk_ctrl_power_on()
218 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, in imx8mp_hdmi_blk_ctrl_power_on()
222 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17)); in imx8mp_hdmi_blk_ctrl_power_on()
223 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18)); in imx8mp_hdmi_blk_ctrl_power_on()
226 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28)); in imx8mp_hdmi_blk_ctrl_power_on()
227 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22)); in imx8mp_hdmi_blk_ctrl_power_on()
230 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30)); in imx8mp_hdmi_blk_ctrl_power_on()
231 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20)); in imx8mp_hdmi_blk_ctrl_power_on()
234 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, in imx8mp_hdmi_blk_ctrl_power_on()
236 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, in imx8mp_hdmi_blk_ctrl_power_on()
239 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, in imx8mp_hdmi_blk_ctrl_power_on()
241 regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1)); in imx8mp_hdmi_blk_ctrl_power_on()
244 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24)); in imx8mp_hdmi_blk_ctrl_power_on()
245 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12)); in imx8mp_hdmi_blk_ctrl_power_on()
246 regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3)); in imx8mp_hdmi_blk_ctrl_power_on()
249 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11)); in imx8mp_hdmi_blk_ctrl_power_on()
252 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5)); in imx8mp_hdmi_blk_ctrl_power_on()
253 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15)); in imx8mp_hdmi_blk_ctrl_power_on()
263 switch (domain->id) { in imx8mp_hdmi_blk_ctrl_power_off()
265 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9)); in imx8mp_hdmi_blk_ctrl_power_off()
266 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16)); in imx8mp_hdmi_blk_ctrl_power_off()
269 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, in imx8mp_hdmi_blk_ctrl_power_off()
271 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11)); in imx8mp_hdmi_blk_ctrl_power_off()
272 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, in imx8mp_hdmi_blk_ctrl_power_off()
277 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(18)); in imx8mp_hdmi_blk_ctrl_power_off()
278 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(17)); in imx8mp_hdmi_blk_ctrl_power_off()
281 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(22)); in imx8mp_hdmi_blk_ctrl_power_off()
282 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(28)); in imx8mp_hdmi_blk_ctrl_power_off()
285 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(20)); in imx8mp_hdmi_blk_ctrl_power_off()
286 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(27) | BIT(30)); in imx8mp_hdmi_blk_ctrl_power_off()
289 regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(1)); in imx8mp_hdmi_blk_ctrl_power_off()
290 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, in imx8mp_hdmi_blk_ctrl_power_off()
292 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, in imx8mp_hdmi_blk_ctrl_power_off()
295 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, in imx8mp_hdmi_blk_ctrl_power_off()
299 regmap_set_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3)); in imx8mp_hdmi_blk_ctrl_power_off()
300 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12)); in imx8mp_hdmi_blk_ctrl_power_off()
301 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24)); in imx8mp_hdmi_blk_ctrl_power_off()
304 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11)); in imx8mp_hdmi_blk_ctrl_power_off()
307 regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15)); in imx8mp_hdmi_blk_ctrl_power_off()
308 regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5)); in imx8mp_hdmi_blk_ctrl_power_off()
325 * Contrary to other blk-ctrls the reset and clock don't clear when the in imx8mp_hdmi_power_notifier()
330 regmap_write(bc->regmap, HDMI_RTX_RESET_CTL0, 0x0); in imx8mp_hdmi_power_notifier()
331 regmap_write(bc->regmap, HDMI_RTX_CLK_CTL0, 0x0); in imx8mp_hdmi_power_notifier()
332 regmap_write(bc->regmap, HDMI_RTX_CLK_CTL1, 0x0); in imx8mp_hdmi_power_notifier()
333 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, in imx8mp_hdmi_power_notifier()
335 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(0)); in imx8mp_hdmi_power_notifier()
349 .name = "hdmiblk-irqsteer",
355 .name = "hdmiblk-lcdif",
356 .clk_names = (const char *[]){ "axi", "apb" },
359 .path_names = (const char *[]){"lcdif-hdmi"},
363 .name = "hdmiblk-pai",
369 .name = "hdmiblk-pvi",
375 .name = "hdmiblk-trng",
381 .name = "hdmiblk-hdmi-tx",
384 .gpc_name = "hdmi-tx",
387 .name = "hdmiblk-hdmi-tx-phy",
390 .gpc_name = "hdmi-tx-phy",
393 .name = "hdmiblk-hrv",
394 .clk_names = (const char *[]){ "axi", "apb" },
401 .name = "hdmiblk-hdcp",
402 .clk_names = (const char *[]){ "axi", "apb" },
422 const struct imx8mp_blk_ctrl_domain_data *data = domain->data; in imx8mp_blk_ctrl_power_on()
423 struct imx8mp_blk_ctrl *bc = domain->bc; in imx8mp_blk_ctrl_power_on()
427 ret = pm_runtime_resume_and_get(bc->bus_power_dev); in imx8mp_blk_ctrl_power_on()
429 dev_err(bc->dev, "failed to power up bus domain\n"); in imx8mp_blk_ctrl_power_on()
434 ret = clk_bulk_prepare_enable(data->num_clks, domain->clks); in imx8mp_blk_ctrl_power_on()
436 dev_err(bc->dev, "failed to enable clocks\n"); in imx8mp_blk_ctrl_power_on()
440 /* domain specific blk-ctrl manipulation */ in imx8mp_blk_ctrl_power_on()
441 bc->power_on(bc, domain); in imx8mp_blk_ctrl_power_on()
444 ret = pm_runtime_resume_and_get(domain->power_dev); in imx8mp_blk_ctrl_power_on()
446 dev_err(bc->dev, "failed to power up peripheral domain\n"); in imx8mp_blk_ctrl_power_on()
450 ret = icc_bulk_set_bw(domain->num_paths, domain->paths); in imx8mp_blk_ctrl_power_on()
452 dev_err(bc->dev, "failed to set icc bw\n"); in imx8mp_blk_ctrl_power_on()
454 clk_bulk_disable_unprepare(data->num_clks, domain->clks); in imx8mp_blk_ctrl_power_on()
459 clk_bulk_disable_unprepare(data->num_clks, domain->clks); in imx8mp_blk_ctrl_power_on()
461 pm_runtime_put(bc->bus_power_dev); in imx8mp_blk_ctrl_power_on()
469 const struct imx8mp_blk_ctrl_domain_data *data = domain->data; in imx8mp_blk_ctrl_power_off()
470 struct imx8mp_blk_ctrl *bc = domain->bc; in imx8mp_blk_ctrl_power_off()
473 ret = clk_bulk_prepare_enable(data->num_clks, domain->clks); in imx8mp_blk_ctrl_power_off()
475 dev_err(bc->dev, "failed to enable clocks\n"); in imx8mp_blk_ctrl_power_off()
479 /* domain specific blk-ctrl manipulation */ in imx8mp_blk_ctrl_power_off()
480 bc->power_off(bc, domain); in imx8mp_blk_ctrl_power_off()
482 clk_bulk_disable_unprepare(data->num_clks, domain->clks); in imx8mp_blk_ctrl_power_off()
485 pm_runtime_put(domain->power_dev); in imx8mp_blk_ctrl_power_off()
488 pm_runtime_put(bc->bus_power_dev); in imx8mp_blk_ctrl_power_off()
498 struct device *dev = &pdev->dev; in imx8mp_blk_ctrl_probe()
511 return -ENOMEM; in imx8mp_blk_ctrl_probe()
513 bc->dev = dev; in imx8mp_blk_ctrl_probe()
516 num_domains = bc_data->num_domains; in imx8mp_blk_ctrl_probe()
522 regmap_config.max_register = bc_data->max_reg; in imx8mp_blk_ctrl_probe()
523 bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config); in imx8mp_blk_ctrl_probe()
524 if (IS_ERR(bc->regmap)) in imx8mp_blk_ctrl_probe()
525 return dev_err_probe(dev, PTR_ERR(bc->regmap), in imx8mp_blk_ctrl_probe()
528 bc->domains = devm_kcalloc(dev, num_domains, in imx8mp_blk_ctrl_probe()
531 if (!bc->domains) in imx8mp_blk_ctrl_probe()
532 return -ENOMEM; in imx8mp_blk_ctrl_probe()
534 bc->onecell_data.num_domains = num_domains; in imx8mp_blk_ctrl_probe()
535 bc->onecell_data.domains = in imx8mp_blk_ctrl_probe()
538 if (!bc->onecell_data.domains) in imx8mp_blk_ctrl_probe()
539 return -ENOMEM; in imx8mp_blk_ctrl_probe()
541 bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus"); in imx8mp_blk_ctrl_probe()
542 if (IS_ERR(bc->bus_power_dev)) in imx8mp_blk_ctrl_probe()
543 return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev), in imx8mp_blk_ctrl_probe()
546 bc->power_off = bc_data->power_off; in imx8mp_blk_ctrl_probe()
547 bc->power_on = bc_data->power_on; in imx8mp_blk_ctrl_probe()
550 const struct imx8mp_blk_ctrl_domain_data *data = &bc_data->domains[i]; in imx8mp_blk_ctrl_probe()
551 struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i]; in imx8mp_blk_ctrl_probe()
554 domain->data = data; in imx8mp_blk_ctrl_probe()
555 domain->num_paths = data->num_paths; in imx8mp_blk_ctrl_probe()
557 for (j = 0; j < data->num_clks; j++) in imx8mp_blk_ctrl_probe()
558 domain->clks[j].id = data->clk_names[j]; in imx8mp_blk_ctrl_probe()
560 for (j = 0; j < data->num_paths; j++) { in imx8mp_blk_ctrl_probe()
561 domain->paths[j].name = data->path_names[j]; in imx8mp_blk_ctrl_probe()
563 domain->paths[j].avg_bw = 1; in imx8mp_blk_ctrl_probe()
564 domain->paths[j].peak_bw = 1; in imx8mp_blk_ctrl_probe()
567 ret = devm_of_icc_bulk_get(dev, data->num_paths, domain->paths); in imx8mp_blk_ctrl_probe()
569 if (ret != -EPROBE_DEFER) { in imx8mp_blk_ctrl_probe()
571 domain->num_paths = 0; in imx8mp_blk_ctrl_probe()
578 ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks); in imx8mp_blk_ctrl_probe()
584 domain->power_dev = in imx8mp_blk_ctrl_probe()
585 dev_pm_domain_attach_by_name(dev, data->gpc_name); in imx8mp_blk_ctrl_probe()
586 if (IS_ERR(domain->power_dev)) { in imx8mp_blk_ctrl_probe()
587 dev_err_probe(dev, PTR_ERR(domain->power_dev), in imx8mp_blk_ctrl_probe()
589 data->gpc_name); in imx8mp_blk_ctrl_probe()
590 ret = PTR_ERR(domain->power_dev); in imx8mp_blk_ctrl_probe()
593 dev_set_name(domain->power_dev, "%s", data->name); in imx8mp_blk_ctrl_probe()
595 domain->genpd.name = data->name; in imx8mp_blk_ctrl_probe()
596 domain->genpd.power_on = imx8mp_blk_ctrl_power_on; in imx8mp_blk_ctrl_probe()
597 domain->genpd.power_off = imx8mp_blk_ctrl_power_off; in imx8mp_blk_ctrl_probe()
598 domain->bc = bc; in imx8mp_blk_ctrl_probe()
599 domain->id = i; in imx8mp_blk_ctrl_probe()
601 ret = pm_genpd_init(&domain->genpd, NULL, true); in imx8mp_blk_ctrl_probe()
604 dev_pm_domain_detach(domain->power_dev, true); in imx8mp_blk_ctrl_probe()
616 * self-deadlock. in imx8mp_blk_ctrl_probe()
618 lockdep_set_class(&domain->genpd.mlock, in imx8mp_blk_ctrl_probe()
621 bc->onecell_data.domains[i] = &domain->genpd; in imx8mp_blk_ctrl_probe()
624 ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data); in imx8mp_blk_ctrl_probe()
630 bc->power_nb.notifier_call = bc_data->power_notifier_fn; in imx8mp_blk_ctrl_probe()
631 ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb); in imx8mp_blk_ctrl_probe()
642 of_genpd_del_provider(dev->of_node); in imx8mp_blk_ctrl_probe()
644 for (i--; i >= 0; i--) { in imx8mp_blk_ctrl_probe()
645 pm_genpd_remove(&bc->domains[i].genpd); in imx8mp_blk_ctrl_probe()
646 dev_pm_domain_detach(bc->domains[i].power_dev, true); in imx8mp_blk_ctrl_probe()
649 dev_pm_domain_detach(bc->bus_power_dev, true); in imx8mp_blk_ctrl_probe()
656 struct imx8mp_blk_ctrl *bc = dev_get_drvdata(&pdev->dev); in imx8mp_blk_ctrl_remove()
659 of_genpd_del_provider(pdev->dev.of_node); in imx8mp_blk_ctrl_remove()
661 for (i = 0; bc->onecell_data.num_domains; i++) { in imx8mp_blk_ctrl_remove()
662 struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i]; in imx8mp_blk_ctrl_remove()
664 pm_genpd_remove(&domain->genpd); in imx8mp_blk_ctrl_remove()
665 dev_pm_domain_detach(domain->power_dev, true); in imx8mp_blk_ctrl_remove()
668 dev_pm_genpd_remove_notifier(bc->bus_power_dev); in imx8mp_blk_ctrl_remove()
670 dev_pm_domain_detach(bc->bus_power_dev, true); in imx8mp_blk_ctrl_remove()
676 static int imx8mp_blk_ctrl_suspend(struct device *dev) in imx8mp_blk_ctrl_suspend()
686 * in the system suspend/resume paths due to the device parent/child in imx8mp_blk_ctrl_suspend()
689 ret = pm_runtime_get_sync(bc->bus_power_dev); in imx8mp_blk_ctrl_suspend()
691 pm_runtime_put_noidle(bc->bus_power_dev); in imx8mp_blk_ctrl_suspend()
695 for (i = 0; i < bc->onecell_data.num_domains; i++) { in imx8mp_blk_ctrl_suspend()
696 struct imx8mp_blk_ctrl_domain *domain = &bc->domains[i]; in imx8mp_blk_ctrl_suspend()
698 ret = pm_runtime_get_sync(domain->power_dev); in imx8mp_blk_ctrl_suspend()
700 pm_runtime_put_noidle(domain->power_dev); in imx8mp_blk_ctrl_suspend()
708 for (i--; i >= 0; i--) in imx8mp_blk_ctrl_suspend()
709 pm_runtime_put(bc->domains[i].power_dev); in imx8mp_blk_ctrl_suspend()
711 pm_runtime_put(bc->bus_power_dev); in imx8mp_blk_ctrl_suspend()
716 static int imx8mp_blk_ctrl_resume(struct device *dev) in imx8mp_blk_ctrl_resume()
721 for (i = 0; i < bc->onecell_data.num_domains; i++) in imx8mp_blk_ctrl_resume()
722 pm_runtime_put(bc->domains[i].power_dev); in imx8mp_blk_ctrl_resume()
724 pm_runtime_put(bc->bus_power_dev); in imx8mp_blk_ctrl_resume()
737 .compatible = "fsl,imx8mp-hsio-blk-ctrl",
740 .compatible = "fsl,imx8mp-hdmi-blk-ctrl",
752 .name = "imx8mp-blk-ctrl",