Lines Matching full:ddr
6 * S3: power off all of the chip except the Always ON (AON) island; keep DDR is
8 * S5: (a.k.a. S3 cold boot) much like S3, except DDR is powered down, so we
370 * from SRAM, in order to allow DDR to come back up safely before we continue.
581 .compatible = "brcm,brcmstb-ddr-phy-v71.1",
585 .compatible = "brcm,brcmstb-ddr-phy-v72.0",
589 .compatible = "brcm,brcmstb-ddr-phy-v225.1",
593 .compatible = "brcm,brcmstb-ddr-phy-v240.1",
598 .compatible = "brcm,brcmstb-ddr-phy-v240.2",
619 { .compatible = "brcm,brcmstb-ddr-shimphy-v1.0" },
625 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
629 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
633 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
637 .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0",
641 .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1",
645 .compatible = "brcm,brcmstb-memc-ddr",
724 /* DDR PHY registers */ in brcmstb_pm_probe()
728 pr_err("error mapping DDR PHY\n"); in brcmstb_pm_probe()
734 /* Only need DDR PHY 0 for now? */ in brcmstb_pm_probe()
746 /* DDR SHIM-PHY registers */ in brcmstb_pm_probe()
761 pr_err("error mapping DDR SHIMPHY %d\n", i); in brcmstb_pm_probe()
775 pr_err("error mapping DDR Sequencer %d\n", i); in brcmstb_pm_probe()
790 /* Adjust warm boot offset based on the DDR sequencer */ in brcmstb_pm_probe()