Lines Matching +full:0 +full:x402
60 unsigned char dma_addr; /* DMA address [0x0000] */
61 unsigned char dmapad2[0x7fff];
62 unsigned char dma_latch; /* DMA latch [0x8000] */
68 unsigned char dma_addr; /* DMA address [0x0000] */
69 unsigned char dmapad2[0xf];
70 unsigned char dma_latch; /* DMA latch [0x0010] */
76 unsigned char dma_led_ctrl; /* DMA led control [0x000] */
77 unsigned char dmapad1[0x0f];
78 unsigned char dma_addr0; /* DMA address (MSB) [0x010] */
79 unsigned char dmapad2[0x03];
80 unsigned char dma_addr1; /* DMA address [0x014] */
81 unsigned char dmapad3[0x03];
82 unsigned char dma_addr2; /* DMA address [0x018] */
83 unsigned char dmapad4[0x03];
84 unsigned char dma_addr3; /* DMA address (LSB) [0x01c] */
88 #define DMA_WRITE 0x80000000
93 unsigned char dma_addr0; /* DMA address (MSB) [0x000] */
95 unsigned char dma_addr1; /* DMA address [0x002] */
97 unsigned char dma_addr2; /* DMA address [0x004] */
99 unsigned char dma_addr3; /* DMA address (LSB) [0x006] */
100 unsigned char dmapad4[0x3fb];
101 unsigned char cond_reg; /* DMA cond (ro) [0x402] */
102 #define ctrl_reg cond_reg /* DMA control (wo) [0x402] */
106 #define CYBER_DMA_WRITE 0x40 /* DMA direction. 1 = write */
107 #define CYBER_DMA_Z3 0x20 /* 16 (Z2) or 32 (CHIP/Z3) bit DMA transfer */
110 #define CYBER_DMA_HNDL_INTR 0x80 /* DMA IRQ pending? */
114 unsigned char cond_reg; /* DMA cond (ro) [0x000] */
115 #define ctrl_reg cond_reg /* DMA control (wo) [0x000] */
116 unsigned char dmapad4[0x3f];
117 unsigned char dma_addr0; /* DMA address (MSB) [0x040] */
119 unsigned char dma_addr1; /* DMA address [0x044] */
121 unsigned char dma_addr2; /* DMA address [0x048] */
123 unsigned char dma_addr3; /* DMA address (LSB) [0x04c] */
129 unsigned char cond_reg; /* DMA status (ro) [0x0000] */
130 #define ctrl_reg cond_reg /* DMA control (wo) [0x0000] */
131 char dmapad1[0x3f];
132 unsigned char clear_strobe; /* DMA clear (wo) [0x0040] */
139 #define FASTLANE_ESP_ADDR 0x1000001
142 #define FASTLANE_DMA_MINT 0x80
143 #define FASTLANE_DMA_IACT 0x40
144 #define FASTLANE_DMA_CREQ 0x20
147 #define FASTLANE_DMA_FCODE 0xa0
148 #define FASTLANE_DMA_MASK 0xf3
149 #define FASTLANE_DMA_WRITE 0x08 /* 1 = write */
150 #define FASTLANE_DMA_ENABLE 0x04 /* Enable DMA */
151 #define FASTLANE_DMA_EDI 0x02 /* Enable DMA IRQ ? */
152 #define FASTLANE_DMA_ESI 0x01 /* Enable SCSI IRQ */
188 return 0; in zorro_esp_irq_pending()
209 return 0; /* not our IRQ */ in fastlane_esp_irq_pending()
227 /* The old driver used 0xfffc as limit, so do that here too */ in fastlane_esp_dma_length_limit()
228 return dma_len > 0xfffc ? 0xfffc : dma_len; in fastlane_esp_dma_length_limit()
253 writeb(0, &dregs->clear_strobe); in fastlane_esp_dma_invalidate()
254 z_writel(0, zep->board_base); in fastlane_esp_dma_invalidate()
277 esp->send_cmd_error = 0; in zorro_esp_send_blz1230_dma_cmd()
278 esp->send_cmd_residual = 0; in zorro_esp_send_blz1230_dma_cmd()
295 writeb((addr >> 24) & 0xff, &dregs->dma_latch); in zorro_esp_send_blz1230_dma_cmd()
296 writeb((addr >> 24) & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230_dma_cmd()
297 writeb((addr >> 16) & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230_dma_cmd()
298 writeb((addr >> 8) & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230_dma_cmd()
299 writeb(addr & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230_dma_cmd()
302 zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW); in zorro_esp_send_blz1230_dma_cmd()
303 zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED); in zorro_esp_send_blz1230_dma_cmd()
323 esp->send_cmd_error = 0; in zorro_esp_send_blz1230II_dma_cmd()
324 esp->send_cmd_residual = 0; in zorro_esp_send_blz1230II_dma_cmd()
341 writeb((addr >> 24) & 0xff, &dregs->dma_latch); in zorro_esp_send_blz1230II_dma_cmd()
342 writeb((addr >> 16) & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230II_dma_cmd()
343 writeb((addr >> 8) & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230II_dma_cmd()
344 writeb(addr & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230II_dma_cmd()
347 zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW); in zorro_esp_send_blz1230II_dma_cmd()
348 zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED); in zorro_esp_send_blz1230II_dma_cmd()
368 esp->send_cmd_error = 0; in zorro_esp_send_blz2060_dma_cmd()
369 esp->send_cmd_residual = 0; in zorro_esp_send_blz2060_dma_cmd()
386 writeb(addr & 0xff, &dregs->dma_addr3); in zorro_esp_send_blz2060_dma_cmd()
387 writeb((addr >> 8) & 0xff, &dregs->dma_addr2); in zorro_esp_send_blz2060_dma_cmd()
388 writeb((addr >> 16) & 0xff, &dregs->dma_addr1); in zorro_esp_send_blz2060_dma_cmd()
389 writeb((addr >> 24) & 0xff, &dregs->dma_addr0); in zorro_esp_send_blz2060_dma_cmd()
392 zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW); in zorro_esp_send_blz2060_dma_cmd()
393 zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED); in zorro_esp_send_blz2060_dma_cmd()
415 esp->send_cmd_error = 0; in zorro_esp_send_cyber_dma_cmd()
416 esp->send_cmd_residual = 0; in zorro_esp_send_cyber_dma_cmd()
418 zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW); in zorro_esp_send_cyber_dma_cmd()
419 zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED); in zorro_esp_send_cyber_dma_cmd()
433 writeb((addr >> 24) & 0xff, &dregs->dma_addr0); in zorro_esp_send_cyber_dma_cmd()
434 writeb((addr >> 16) & 0xff, &dregs->dma_addr1); in zorro_esp_send_cyber_dma_cmd()
435 writeb((addr >> 8) & 0xff, &dregs->dma_addr2); in zorro_esp_send_cyber_dma_cmd()
436 writeb(addr & 0xff, &dregs->dma_addr3); in zorro_esp_send_cyber_dma_cmd()
465 esp->send_cmd_error = 0; in zorro_esp_send_cyberII_dma_cmd()
466 esp->send_cmd_residual = 0; in zorro_esp_send_cyberII_dma_cmd()
468 zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW); in zorro_esp_send_cyberII_dma_cmd()
469 zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED); in zorro_esp_send_cyberII_dma_cmd()
483 writeb((addr >> 24) & 0xff, &dregs->dma_addr0); in zorro_esp_send_cyberII_dma_cmd()
484 writeb((addr >> 16) & 0xff, &dregs->dma_addr1); in zorro_esp_send_cyberII_dma_cmd()
485 writeb((addr >> 8) & 0xff, &dregs->dma_addr2); in zorro_esp_send_cyberII_dma_cmd()
486 writeb(addr & 0xff, &dregs->dma_addr3); in zorro_esp_send_cyberII_dma_cmd()
508 esp->send_cmd_error = 0; in zorro_esp_send_fastlane_dma_cmd()
509 esp->send_cmd_residual = 0; in zorro_esp_send_fastlane_dma_cmd()
511 zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW); in zorro_esp_send_fastlane_dma_cmd()
512 zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED); in zorro_esp_send_fastlane_dma_cmd()
526 writeb(0, &dregs->clear_strobe); in zorro_esp_send_fastlane_dma_cmd()
527 z_writel(addr, ((addr & 0x00ffffff) + zep->board_base)); in zorro_esp_send_fastlane_dma_cmd()
649 .offset = 0x8000,
650 .dma_offset = 0x10000,
656 .offset = 0x10000,
657 .dma_offset = 0x10021,
663 .offset = 0x1ff00,
664 .dma_offset = 0x1ffe0,
669 .offset = 0xf400,
670 .dma_offset = 0xf800,
675 .offset = 0x1ff03,
676 .dma_offset = 0x1ff43,
682 .offset = 0x1000001,
683 .dma_offset = 0x1000041,
690 .id = ZORRO_ID(PHASE5, 0x11, 0),
694 .id = ZORRO_ID(PHASE5, 0x0B, 0),
698 .id = ZORRO_ID(PHASE5, 0x18, 0),
702 .id = ZORRO_ID(PHASE5, 0x0C, 0),
706 .id = ZORRO_ID(PHASE5, 0x19, 0),
709 { 0 }
727 pr_info("%s found at address 0x%lx.\n", zdd->name, board); in zorro_esp_probe()
737 if (board > 0xffffff) in zorro_esp_probe()
757 pr_info("%s at address 0x%lx is Fastlane Z3, fixing data!\n", in zorro_esp_probe()
771 pr_err("cannot reserve region 0x%lx, abort\n", in zorro_esp_probe()
817 if (ioaddr > 0xffffff) in zorro_esp_probe()
818 esp->regs = ioremap(ioaddr, 0x20); in zorro_esp_probe()
867 if (err < 0) { in zorro_esp_probe()
880 return 0; in zorro_esp_probe()
895 if (ioaddr > 0xffffff) in zorro_esp_probe()
932 if (host->base > 0xffffff) in zorro_esp_remove()