91 #define UDC_MODE 0x38
92 #define UDC_CSR 0x2e /* command/status */
93 #define UDC_CHN_HI 0x26 /* chain high word */
94 #define UDC_CHN_LO 0x22 /* chain lo word */
95 #define UDC_CURA_HI 0x1a /* cur reg A high */
96 #define UDC_CURA_LO 0x0a /* cur reg A low */
97 #define UDC_CURB_HI 0x12 /* cur reg B high */
98 #define UDC_CURB_LO 0x02 /* cur reg B low */
99 #define UDC_MODE_HI 0x56 /* mode reg high */
100 #define UDC_MODE_LO 0x52 /* mode reg low */
101 #define UDC_COUNT 0x32 /* words to xfer */
104 #define UDC_RESET 0
105 #define UDC_CHN_START 0xa0 /* start chain */
106 #define UDC_INT_ENABLE 0x32 /* channel 1 int on */
109 #define UDC_MODE_HIWORD 0x40
110 #define UDC_MODE_LSEND 0xc2
111 #define UDC_MODE_LRECV 0xd2
114 #define UDC_RSEL_SEND 0x282
115 #define UDC_RSEL_RECV 0x182
118 #define CSR_DMA_ACTIVE 0x8000
119 #define CSR_DMA_CONFLICT 0x4000
120 #define CSR_DMA_BUSERR 0x2000
122 #define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
123 #define CSR_SDB_INT 0x200 /* sbc interrupt pending */
124 #define CSR_DMA_INT 0x100 /* dma interrupt pending */
126 #define CSR_LEFT 0xc0
127 #define CSR_LEFT_3 0xc0
128 #define CSR_LEFT_2 0x80
129 #define CSR_LEFT_1 0x40
130 #define CSR_PACK_ENABLE 0x20
132 #define CSR_DMA_ENABLE 0x10
134 #define CSR_SEND 0x8 /* 1 = send  0 = recv */
135 #define CSR_FIFO 0x2 /* reset fifo */
136 #define CSR_INTR 0x4 /* interrupt enable */
137 #define CSR_SCSI 0x1
139 #define VME_DATA24 0x3d00
144 module_param(setup_can_queue, int, 0);
146 module_param(setup_cmd_per_lun, int, 0);
148 module_param(setup_sg_tablesize, int, 0);
150 module_param(setup_hostid, int, 0);
156 #define SUN3_DVMA_BUFSIZE 0xe000
191 #define CSR_GOOD 0x060f
197 	int handled = 0;  in scsi_sun3_intr()
238 	dregs->fifo_count = 0;  in sun3scsi_dma_setup()
256 	dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);  in sun3scsi_dma_setup()
258 	dregs->dma_count_hi = 0;  in sun3scsi_dma_setup()
259 	dregs->dma_count_lo = 0;  in sun3scsi_dma_setup()
260 	dregs->fifo_count_hi = 0;  in sun3scsi_dma_setup()
261 	dregs->fifo_count = 0;  in sun3scsi_dma_setup()
280 	udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);  in sun3scsi_dma_setup()
281 	udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);  in sun3scsi_dma_setup()
295 	sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),  in sun3scsi_dma_setup()
298 	sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);  in sun3scsi_dma_setup()
301 	sun3_udc_write(0xd, UDC_MODE);  in sun3scsi_dma_setup()
320 	return sun3scsi_dma_setup(hostdata, data, count, 0);  in sun3scsi_dma_recv_setup()
340 		return 0;  in sun3scsi_dma_xfer_len()
353 	dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);  in sun3scsi_dma_start()
356 	dregs->fifo_count = (sun3_dma_orig_count & 0xffff);  in sun3scsi_dma_start()
365     return 0;  in sun3scsi_dma_start()
374 	int ret = 0;  in sun3scsi_dma_finish()
376 	sun3_dma_active = 0;  in sun3scsi_dma_finish()
383 		if ((fifo > 0) && (fifo < sun3_dma_orig_count))  in sun3scsi_dma_finish()
399 			*vaddr = (dregs->bpack_lo & 0xff00) >> 8;  in sun3scsi_dma_finish()
404 			*vaddr = (dregs->bpack_hi & 0x00ff);  in sun3scsi_dma_finish()
409 			*vaddr = (dregs->bpack_hi & 0xff00) >> 8;  in sun3scsi_dma_finish()
422 			if(--tmo <= 0) {  in sun3scsi_dma_finish()
430 	dregs->udc_addr = 0x32;  in sun3scsi_dma_finish()
448 		vaddr[-2] = (data & 0xff00) >> 8;  in sun3scsi_dma_finish()
449 		vaddr[-1] = (data & 0xff);  in sun3scsi_dma_finish()
457 	dregs->dma_addr_hi = 0;  in sun3scsi_dma_finish()
458 	dregs->dma_addr_lo = 0;  in sun3scsi_dma_finish()
459 	dregs->dma_count_hi = 0;  in sun3scsi_dma_finish()
460 	dregs->dma_count_lo = 0;  in sun3scsi_dma_finish()
462 	dregs->fifo_count = 0;  in sun3scsi_dma_finish()
463 	dregs->fifo_count_hi = 0;  in sun3scsi_dma_finish()
469 	dregs->fifo_count = 0;  in sun3scsi_dma_finish()
518 	int host_flags = 0;  in sun3_scsi_probe()
523 	if (setup_can_queue > 0)  in sun3_scsi_probe()
525 	if (setup_cmd_per_lun > 0)  in sun3_scsi_probe()
527 	if (setup_sg_tablesize > 0)  in sun3_scsi_probe()
529 	if (setup_hostid >= 0)  in sun3_scsi_probe()
534 	for (i = 0; i < 2; i++) {  in sun3_scsi_probe()
550 			dregs->csr = 0;  in sun3_scsi_probe()
552 			if (dregs->csr == 0x1400)  in sun3_scsi_probe()
564 	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);  in sun3_scsi_probe()
565 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in sun3_scsi_probe()
597 	error = request_irq(instance->irq, scsi_sun3_intr, 0,  in sun3_scsi_probe()
605 	dregs->csr = 0;  in sun3_scsi_probe()
609 	dregs->fifo_count = 0;  in sun3_scsi_probe()
611 	dregs->fifo_count_hi = 0;  in sun3_scsi_probe()
612 	dregs->dma_addr_hi = 0;  in sun3_scsi_probe()
613 	dregs->dma_addr_lo = 0;  in sun3_scsi_probe()
614 	dregs->dma_count_hi = 0;  in sun3_scsi_probe()
615 	dregs->dma_count_lo = 0;  in sun3_scsi_probe()
617 	dregs->ivect = VME_DATA24 | (instance->irq & 0xff);  in sun3_scsi_probe()
629 	return 0;  in sun3_scsi_probe()
657 	return 0;  in sun3_scsi_remove()