Lines Matching +full:0 +full:x3500
11 #define INTENT_TO_RECOVER 0x01
12 #define PROCEED_TO_RECOVER 0x02
13 #define IDC_LOCK_RECOVERY_OWNER_MASK 0x3C
14 #define IDC_LOCK_RECOVERY_STATE_MASK 0x3
18 #define QLA8044_ADDR_DDR_NET (0x0000000000000000ULL)
19 #define QLA8044_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
21 #define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
22 #define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
23 #define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
24 #define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
36 #define QLA8044_P2_ADDR_PCIE (0x0000000800000000ULL)
37 #define QLA8044_P3_ADDR_PCIE (0x0000008000000000ULL)
38 #define QLA8044_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
39 #define QLA8044_ADDR_OCM0 (0x0000000200000000ULL)
40 #define QLA8044_ADDR_OCM0_MAX (0x00000002000fffffULL)
41 #define QLA8044_ADDR_OCM1 (0x0000000200400000ULL)
42 #define QLA8044_ADDR_OCM1_MAX (0x00000002004fffffULL)
43 #define QLA8044_ADDR_QDR_NET (0x0000000300000000ULL)
44 #define QLA8044_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
45 #define QLA8044_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
46 #define QLA8044_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
47 #define QLA8044_PCI_CRBSPACE ((unsigned long)0x06000000)
48 #define QLA8044_PCI_DIRECT_CRB ((unsigned long)0x04400000)
49 #define QLA8044_PCI_CAMQM ((unsigned long)0x04800000)
50 #define QLA8044_PCI_CAMQM_MAX ((unsigned long)0x04ffffff)
51 #define QLA8044_PCI_DDR_NET ((unsigned long)0x00000000)
52 #define QLA8044_PCI_QDR_NET ((unsigned long)0x04000000)
53 #define QLA8044_PCI_QDR_NET_MAX ((unsigned long)0x043fffff)
62 #define QLA8044_FLASH_SPI_STATUS 0x2808E010
63 #define QLA8044_FLASH_SPI_CONTROL 0x2808E014
64 #define QLA8044_FLASH_STATUS 0x42100004
65 #define QLA8044_FLASH_CONTROL 0x42110004
66 #define QLA8044_FLASH_ADDR 0x42110008
67 #define QLA8044_FLASH_WRDATA 0x4211000C
68 #define QLA8044_FLASH_RDDATA 0x42110018
69 #define QLA8044_FLASH_DIRECT_WINDOW 0x42110030
70 #define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
73 #define QLA8044_FLASH_LOCK 0x3850
74 #define QLA8044_FLASH_UNLOCK 0x3854
75 #define QLA8044_FLASH_LOCK_ID 0x3500
78 #define QLA8044_DRV_LOCK 0x3868
79 #define QLA8044_DRV_UNLOCK 0x386C
80 #define QLA8044_DRV_LOCK_ID 0x3504
81 #define QLA8044_DRV_LOCKRECOVERY 0x379C
84 #define QLA8044_IDC_VER_MAJ_VALUE 0x1
85 #define QLA8044_IDC_VER_MIN_VALUE 0x0
88 #define QLA8044_CRB_IDC_VER_MAJOR 0x3780
89 #define QLA8044_CRB_IDC_VER_MINOR 0x3798
90 #define QLA8044_IDC_DRV_AUDIT 0x3794
91 #define QLA8044_SRE_SHIM_CONTROL 0x0D200284
92 #define QLA8044_PORT0_RXB_PAUSE_THRS 0x0B2003A4
93 #define QLA8044_PORT1_RXB_PAUSE_THRS 0x0B2013A4
94 #define QLA8044_PORT0_RXB_TC_MAX_CELL 0x0B200388
95 #define QLA8044_PORT1_RXB_TC_MAX_CELL 0x0B201388
96 #define QLA8044_PORT0_RXB_TC_STATS 0x0B20039C
97 #define QLA8044_PORT1_RXB_TC_STATS 0x0B20139C
98 #define QLA8044_PORT2_IFB_PAUSE_THRS 0x0B200704
99 #define QLA8044_PORT3_IFB_PAUSE_THRS 0x0B201704
102 #define QLA8044_SET_PAUSE_VAL 0x0
103 #define QLA8044_SET_TC_MAX_CELL_VAL 0x03FF03FF
104 #define QLA8044_PEG_HALT_STATUS1 0x34A8
105 #define QLA8044_PEG_HALT_STATUS2 0x34AC
106 #define QLA8044_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
107 #define QLA8044_FW_CAPABILITIES 0x3528
108 #define QLA8044_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
109 #define QLA8044_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
110 #define QLA8044_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
111 #define QLA8044_CRB_DRV_SCRATCH 0x3548
112 #define QLA8044_CRB_DEV_PART_INFO1 0x37E0
113 #define QLA8044_CRB_DEV_PART_INFO2 0x37E4
114 #define QLA8044_FW_VER_MAJOR 0x3550
115 #define QLA8044_FW_VER_MINOR 0x3554
116 #define QLA8044_FW_VER_SUB 0x3558
117 #define QLA8044_NPAR_STATE 0x359C
118 #define QLA8044_FW_IMAGE_VALID 0x35FC
119 #define QLA8044_CMDPEG_STATE 0x3650
120 #define QLA8044_ASIC_TEMP 0x37B4
121 #define QLA8044_FW_API 0x356C
122 #define QLA8044_DRV_OP_MODE 0x3570
123 #define QLA8044_CRB_WIN_BASE 0x3800
125 #define QLA8044_SEM_LOCK_BASE 0x3840
126 #define QLA8044_SEM_UNLOCK_BASE 0x3844
129 #define QLA8044_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
130 #define QLA8044_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
131 #define QLA8044_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
133 #define QLA8044_FUN7_ACTIVE_INDEX 0x80
140 #define QLA8044_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
141 #define QLA8044_FLASH_WRITE_CMD 0xdacdacda
142 #define QLA8044_FLASH_BUFFER_WRITE_CMD 0xcadcadca
144 #define QLA8044_FLASH_STATUS_READY 0x6
151 #define QLA8044_GLOBAL_RESET 0x38CC
152 #define QLA8044_WILDCARD 0x38F0
153 #define QLA8044_INFORMANT 0x38FC
154 #define QLA8044_HOST_MBX_CTRL 0x3038
155 #define QLA8044_FW_MBX_CTRL 0x303C
156 #define QLA8044_BOOTLOADER_ADDR 0x355C
157 #define QLA8044_BOOTLOADER_SIZE 0x3560
158 #define QLA8044_FW_IMAGE_ADDR 0x3564
159 #define QLA8044_MBX_INTR_ENABLE 0x1000
160 #define QLA8044_MBX_INTR_MASK 0x1200
163 #define DONTRESET_BIT0 0x1
164 #define GRACEFUL_RESET_BIT1 0x2
167 #define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29)
168 #define QLA8044_HALT_STATUS_FW_RESET (0x2 << 29)
169 #define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
172 #define QLA8044_BOOTLOADER_FLASH_ADDR 0x10000
173 #define QLA8044_BOOT_FROM_FLASH 0
174 #define QLA8044_IDC_PARAM_ADDR 0x3e8020
177 #define QLA8044_OPTROM_BURST_SIZE 0x100
182 #define QLA8044_FLASH_SPI_CTL 0x4
183 #define QLA8044_FLASH_FIRST_TEMP_VAL 0x00800000
184 #define QLA8044_FLASH_SECOND_TEMP_VAL 0x00800001
185 #define QLA8044_FLASH_FIRST_MS_PATTERN 0x43
186 #define QLA8044_FLASH_SECOND_MS_PATTERN 0x7F
187 #define QLA8044_FLASH_LAST_MS_PATTERN 0x7D
188 #define QLA8044_FLASH_STATUS_WRITE_DEF_SIG 0xFD0100
189 #define QLA8044_FLASH_SECOND_ERASE_MS_VAL 0x5
190 #define QLA8044_FLASH_ERASE_SIG 0xFD0300
191 #define QLA8044_FLASH_LAST_ERASE_MS_VAL 0x3D
195 #define QLA8044_RESTART_TEMPLATE_SIZE 0x2000
196 #define QLA8044_RESET_TEMPLATE_ADDR 0x4F0000
197 #define QLA8044_RESET_SEQ_VERSION 0x0101
200 #define OPCODE_NOP 0x0000
201 #define OPCODE_WRITE_LIST 0x0001
202 #define OPCODE_READ_WRITE_LIST 0x0002
203 #define OPCODE_POLL_LIST 0x0004
204 #define OPCODE_POLL_WRITE_LIST 0x0008
205 #define OPCODE_READ_MODIFY_WRITE 0x0010
206 #define OPCODE_SEQ_PAUSE 0x0020
207 #define OPCODE_SEQ_END 0x0040
208 #define OPCODE_TMPL_END 0x0080
209 #define OPCODE_POLL_READ_LIST 0x0100
212 #define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
213 #define QLA8044_IDC_DRV_CTRL 0x3790
214 #define AF_8044_NO_FW_DUMP 27 /* 0x08000000 */
513 QLA8044_PEG_HALT_STATUS1_INDEX = 0,
543 #define QLA8044_SS_PCI_INDEX 0
570 uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
575 uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/