Lines Matching +full:0 +full:x10101
15 #define PHAN_INITIALIZE_FAILED 0xffff
16 #define PHAN_INITIALIZE_COMPLETE 0xff01
19 #define PHAN_INITIALIZE_ACK 0xf00f
20 #define PHAN_PEG_RCV_INITIALIZED 0xff01
23 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200)
26 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
27 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
28 #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54)
29 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
30 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
31 #define QLA82XX_DMA_SHIFT_VALUE 0x55555555
33 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
34 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
35 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
36 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
37 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
38 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
39 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
41 /* Hub 0 */
42 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
43 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
46 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
47 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
48 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
49 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
50 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
51 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
52 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
53 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
54 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
55 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
56 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
57 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
58 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
59 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
60 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
63 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
64 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
65 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
67 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
68 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
69 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
70 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
71 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
72 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
73 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
74 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
75 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
76 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
77 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
78 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
79 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
82 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
83 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
84 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
85 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
88 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
89 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
90 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
91 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
92 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
93 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
94 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
95 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
96 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
97 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
98 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
99 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
102 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
103 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
104 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
105 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
106 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
107 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
108 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
111 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
112 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
113 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
114 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
115 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
116 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
117 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
118 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
119 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
123 #define QLA82XX_HW_PX_MAP_CRB_PH 0
323 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
324 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
325 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
326 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
327 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
328 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
329 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
330 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
331 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
333 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
334 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
335 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
337 #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
471 #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL)
472 #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
478 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
479 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
480 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
481 #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL)
482 #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL)
483 #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL)
484 #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL)
485 #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL)
486 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
488 #define QLA82XX_PCI_CRBSPACE 0x06000000UL
489 #define QLA82XX_PCI_DIRECT_CRB 0x04400000UL
490 #define QLA82XX_PCI_CAMQM 0x04800000UL
491 #define QLA82XX_PCI_CAMQM_MAX 0x04ffffffUL
492 #define QLA82XX_PCI_DDR_NET 0x00000000UL
493 #define QLA82XX_PCI_QDR_NET 0x04000000UL
494 #define QLA82XX_PCI_QDR_NET_MAX 0x043fffffUL
499 #define MIU_CONTROL (0x000)
500 #define MIU_TAG (0x004)
501 #define MIU_TEST_AGT_CTRL (0x090)
502 #define MIU_TEST_AGT_ADDR_LO (0x094)
503 #define MIU_TEST_AGT_ADDR_HI (0x098)
504 #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
505 #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
506 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
507 #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
508 #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
509 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
510 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
511 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
520 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
523 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
524 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
525 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
526 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
528 #define QLA82XX_CAMRAM_DB1 (QLA82XX_CAM_RAM(0x1b8))
529 #define QLA82XX_CAMRAM_DB2 (QLA82XX_CAM_RAM(0x1bc))
531 #define HALT_STATUS_UNRECOVERABLE 0x80000000
532 #define HALT_STATUS_RECOVERABLE 0x40000000
535 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
536 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
537 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
538 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
539 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
540 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
555 #define QLA8XXX_BAD_VALUE 0xbad0bad0
561 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
562 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
563 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
564 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
565 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
568 #define PCIE_SETUP_FUNCTION (0x12040)
569 #define PCIE_SETUP_FUNCTION2 (0x12048)
574 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
575 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
576 #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */
577 #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */
578 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
579 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
582 #define QLA82XX_DRVST_NOT_RDY 0
587 #define QLA82XX_DRV_NOT_ACTIVE 0
593 #define PCI_DEVICE_ID_QLOGIC_ISP8021 0x8021
594 #define PCI_DEVICE_ID_QLOGIC_ISP8044 0x8044
597 #define QLA82XX_PCI_REG_MSIX_TBL 0x44
598 #define QLA82XX_PCI_MSIX_CONTROL 0x40
616 #define ADDR_ERROR ((unsigned long) 0xffffffff)
626 #define PCIX_TARGET_STATUS (0x10118)
627 #define PCIX_TARGET_STATUS_F1 (0x10160)
628 #define PCIX_TARGET_STATUS_F2 (0x10164)
629 #define PCIX_TARGET_STATUS_F3 (0x10168)
630 #define PCIX_TARGET_STATUS_F4 (0x10360)
631 #define PCIX_TARGET_STATUS_F5 (0x10364)
632 #define PCIX_TARGET_STATUS_F6 (0x10368)
633 #define PCIX_TARGET_STATUS_F7 (0x1036c)
635 #define PCIX_TARGET_MASK (0x10128)
636 #define PCIX_TARGET_MASK_F1 (0x10170)
637 #define PCIX_TARGET_MASK_F2 (0x10174)
638 #define PCIX_TARGET_MASK_F3 (0x10178)
639 #define PCIX_TARGET_MASK_F4 (0x10370)
640 #define PCIX_TARGET_MASK_F5 (0x10374)
641 #define PCIX_TARGET_MASK_F6 (0x10378)
642 #define PCIX_TARGET_MASK_F7 (0x1037c)
647 #define PCIX_MSI_F0 (0x13000)
648 #define PCIX_MSI_F1 (0x13004)
649 #define PCIX_MSI_F2 (0x13008)
650 #define PCIX_MSI_F3 (0x1300c)
651 #define PCIX_MSI_F4 (0x13010)
652 #define PCIX_MSI_F5 (0x13014)
653 #define PCIX_MSI_F6 (0x13018)
654 #define PCIX_MSI_F7 (0x1301c)
655 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
656 #define PCIX_INT_VECTOR (0x10100)
657 #define PCIX_INT_MASK (0x10104)
662 #define PCIE_MISCCFG_RC (0x1206c)
708 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
709 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
714 #define PCIX_INT_VECTOR_BIT_F0 0x0080
715 #define PCIX_INT_VECTOR_BIT_F1 0x0100
716 #define PCIX_INT_VECTOR_BIT_F2 0x0200
717 #define PCIX_INT_VECTOR_BIT_F3 0x0400
718 #define PCIX_INT_VECTOR_BIT_F4 0x0800
719 #define PCIX_INT_VECTOR_BIT_F5 0x1000
720 #define PCIX_INT_VECTOR_BIT_F6 0x2000
721 #define PCIX_INT_VECTOR_BIT_F7 0x4000
736 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
781 #define BRDCFG_START 0x4000
782 #define BOOTLD_START 0x10000
783 #define IMAGE_START 0x100000
784 #define FLASH_ADDR_START 0x43000
787 #define QLA82XX_BDINFO_MAGIC 0x12345678
788 #define QLA82XX_FW_MAGIC_OFFSET (BRDCFG_START + 0x128)
789 #define FW_SIZE_OFFSET (0x3e840c)
790 #define QLA82XX_FW_MIN_SIZE 0x3fffff
793 #define QLA82XX_URI_FW_MIN_SIZE 0xc8000
794 #define QLA82XX_URI_DIR_SECT_PRODUCT_TBL 0x0
795 #define QLA82XX_URI_DIR_SECT_BOOTLD 0x6
796 #define QLA82XX_URI_DIR_SECT_FW 0x7
822 #define QLA82XX_UNKNOWN_ROMIMAGE 0xff
824 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
825 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
879 #define MBC_TOGGLE_INTERRUPT 0x10
880 #define MBC_SET_LED_CONFIG 0x125 /* FCoE specific LED control */
881 #define MBC_GET_LED_CONFIG 0x126 /* FCoE specific LED control */
884 #define FLT_REG_BOOTLOAD_82XX 0x72
885 #define FLT_REG_BOOT_CODE_82XX 0x78
886 #define FLT_REG_FW_82XX 0x74
887 #define FLT_REG_GOLD_FW_82XX 0x75
888 #define FLT_REG_VPD_8XXX 0x81
890 #define FA_VPD_SIZE_82XX 0x400
892 #define FA_FLASH_LAYOUT_ADDR_82 0xFC400
901 #define M25P_INSTR_WREN 0x06
902 #define M25P_INSTR_WRDI 0x04
903 #define M25P_INSTR_RDID 0x9f
904 #define M25P_INSTR_RDSR 0x05
905 #define M25P_INSTR_WRSR 0x01
906 #define M25P_INSTR_READ 0x03
907 #define M25P_INSTR_FAST_READ 0x0b
908 #define M25P_INSTR_PP 0x02
909 #define M25P_INSTR_SE 0xd8
910 #define M25P_INSTR_BE 0xc7
911 #define M25P_INSTR_DP 0xb9
912 #define M25P_INSTR_RES 0xab
921 #define QLA82XX_MINIDUMP_VERSION 0x10101
926 #define QLA82XX_RDNOP 0
955 #define QLA82XX_DBG_OPCODE_WR 0x01
956 #define QLA82XX_DBG_OPCODE_RW 0x02
957 #define QLA82XX_DBG_OPCODE_AND 0x04
958 #define QLA82XX_DBG_OPCODE_OR 0x08
959 #define QLA82XX_DBG_OPCODE_POLL 0x10
960 #define QLA82XX_DBG_OPCODE_RDSTATE 0x20
961 #define QLA82XX_DBG_OPCODE_WRSTATE 0x40
962 #define QLA82XX_DBG_OPCODE_MDSTATE 0x80
981 #define QLA82XX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
982 #define QLA82XX_DEFAULT_CAP_MASK 0xFF /* default capture mask */
1160 #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129
1161 #define RQST_TMPLT_SIZE 0x0
1162 #define RQST_TMPLT 0x1
1163 #define MD_DIRECT_ROM_WINDOW 0x42110030
1164 #define MD_DIRECT_ROM_READ_BASE 0x42150000
1165 #define MD_MIU_TEST_AGT_CTRL 0x41000090
1166 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
1167 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1171 #define CRB_NIU_XG_PAUSE_CTL_P0 0x1
1172 #define CRB_NIU_XG_PAUSE_CTL_P1 0x8
1175 #define qla82xx_get_temp_state(x) ((x) & 0xffff)
1182 QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */
1187 #define LEG_INTR_PTR_OFFSET 0x38C0
1188 #define LEG_INTR_TRIG_OFFSET 0x38C4
1189 #define LEG_INTR_MASK_OFFSET 0x38C8