2465 		if (rd_reg_word(&reg->mailbox12) & BIT_0)  in qla2x00_initialize_adapter()
2603 	ha->pci_attr = rd_reg_word(&reg->ctrl_status);  in qla2100_pci_config()
2647 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) != 0)  in qla2300_pci_config()
2655 		rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2665 		rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2670 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0)  in qla2300_pci_config()
2685 	ha->pci_attr = rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2836 				if ((rd_reg_word(&reg->hccr) &  in qla2x00_reset_chip()
2842 			rd_reg_word(&reg->hccr);	/* PCI Posting. */  in qla2x00_reset_chip()
2848 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
2852 		rd_reg_word(&reg->fpm_diag_config);	/* PCI Posting. */  in qla2x00_reset_chip()
2857 			rd_reg_word(&reg->fpm_diag_config); /* PCI Posting. */  in qla2x00_reset_chip()
2862 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
2881 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
2885 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
2889 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
2907 			if ((rd_reg_word(&reg->ctrl_status) &  in qla2x00_reset_chip()
2922 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_chip()
2941 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
2980 	mb[0] = rd_reg_word(mbptr);  in qla_chk_risc_recovery()
2986 			mb[i] = rd_reg_word(mbptr);  in qla_chk_risc_recovery()
3054 	rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3055 	for (cnt = 10000; rd_reg_word(&reg->mailbox0) != 0 &&  in qla24xx_reset_risc()
3070 	    rd_reg_word(&reg->mailbox0));  in qla24xx_reset_risc()
3117 	wd = rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3125 			wd = rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3140 	     rd_reg_word(&reg->mailbox0));  in qla24xx_reset_risc()
3297 		data = rd_reg_word(&reg->ctrl_status);  in qla2x00_chip_diag()
3984 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
4095 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
4356 	rd_reg_word(ISP_RSP_Q_OUT(ha, reg));		/* PCI Posting. */  in qla2x00_config_rings()
4440 	rd_reg_word(&ioreg->hccr);  in qla24xx_config_rings()
4926 		if ((rd_reg_word(&reg->ctrl_status) >> 14) == 1)  in qla2x00_nvram_config()
7549 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()
7551 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()