2729 	ha->pci_attr = rd_reg_dword(&reg->ctrl_status);  in qla24xx_pci_config()
3032 		if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)  in qla24xx_reset_risc()
3038 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE))  in qla24xx_reset_risc()
3043 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3044 	    rd_reg_dword(&reg->ctrl_status),  in qla24xx_reset_risc()
3045 	    (rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE));  in qla24xx_reset_risc()
3069 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3073 	rd_reg_dword(&reg->ctrl_status);  in qla24xx_reset_risc()
3076 		if ((rd_reg_dword(&reg->ctrl_status) &  in qla24xx_reset_risc()
3082 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))  in qla24xx_reset_risc()
3087 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3088 	    rd_reg_dword(&reg->ctrl_status));  in qla24xx_reset_risc()
3108 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3111 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3115 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3139 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3160 	*data = rd_reg_dword(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFSET);  in qla25xx_read_risc_sema_reg()
7572 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()
7574 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()