Lines Matching +full:0 +full:- +full:32
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2003-2014 QLogic Corporation
17 __be16 mailbox_reg[32];
18 __be16 resp_dma_reg[32];
32 __be16 risc_ram[0xf800];
33 __be16 stack_ram[0x1000];
40 __be16 mailbox_reg[32];
54 __be16 risc_ram[0xf000];
60 __be32 host_reg[32];
62 __be16 mailbox_reg[32];
74 __be32 xmt0_dma_reg[32];
75 __be32 xmt1_dma_reg[32];
76 __be32 xmt2_dma_reg[32];
77 __be32 xmt3_dma_reg[32];
78 __be32 xmt4_dma_reg[32];
80 __be32 rcvt0_data_dma_reg[32];
81 __be32 rcvt1_data_dma_reg[32];
86 __be32 code_ram[0x2000];
92 __be32 host_risc_reg[32];
94 __be32 host_reg[32];
97 __be16 mailbox_reg[32];
102 __be32 rseq_0_reg[32];
106 __be32 aseq_0_reg[32];
113 __be32 xmt0_dma_reg[32];
114 __be32 xmt1_dma_reg[32];
115 __be32 xmt2_dma_reg[32];
116 __be32 xmt3_dma_reg[32];
117 __be32 xmt4_dma_reg[32];
119 __be32 rcvt0_data_dma_reg[32];
120 __be32 rcvt1_data_dma_reg[32];
125 __be32 code_ram[0x2000];
131 __be32 host_risc_reg[32];
133 __be32 host_reg[32];
136 __be16 mailbox_reg[32];
141 __be32 rseq_0_reg[32];
145 __be32 aseq_0_reg[32];
152 __be32 xmt0_dma_reg[32];
153 __be32 xmt1_dma_reg[32];
154 __be32 xmt2_dma_reg[32];
155 __be32 xmt3_dma_reg[32];
156 __be32 xmt4_dma_reg[32];
158 __be32 rcvt0_data_dma_reg[32];
159 __be32 rcvt1_data_dma_reg[32];
164 __be32 code_ram[0x2000];
172 __be32 host_reg[32];
175 __be16 mailbox_reg[32];
181 __be32 rseq_0_reg[32];
186 __be32 aseq_0_reg[32];
194 __be32 xmt0_dma_reg[32];
195 __be32 xmt1_dma_reg[32];
196 __be32 xmt2_dma_reg[32];
197 __be32 xmt3_dma_reg[32];
198 __be32 xmt4_dma_reg[32];
200 __be32 rcvt0_data_dma_reg[32];
201 __be32 rcvt1_data_dma_reg[32];
212 __be32 code_ram[0x2400];
217 #define EFT_BYTES_PER_BUFFER 0x4000
221 #define FCE_BYTES_PER_BUFFER 0x400
255 #define TYPE_REQUEST_QUEUE 0x1
256 #define TYPE_RESPONSE_QUEUE 0x2
257 #define TYPE_ATIO_QUEUE 0x3
267 #define DUMP_CHAIN_VARIANT 0x80000000
268 #define DUMP_CHAIN_FCE 0x7FFFFAF0
269 #define DUMP_CHAIN_MQ 0x7FFFFAF1
270 #define DUMP_CHAIN_QUEUE 0x7FFFFAF2
271 #define DUMP_CHAIN_EXLOGIN 0x7FFFFAF3
272 #define DUMP_CHAIN_EXCHG 0x7FFFFAF4
273 #define DUMP_CHAIN_LAST 0x80000000
311 #define QL_DBG_DEFAULT1_MASK 0x1e600000
313 #define ql_log_fatal 0 /* display fatal errors */
341 /* The 0x40000000 is the max value any debug level can have
344 #define ql_dbg_init 0x40000000 /* Init Debug */
345 #define ql_dbg_mbx 0x20000000 /* MBX Debug */
346 #define ql_dbg_disc 0x10000000 /* Device Discovery Debug */
347 #define ql_dbg_io 0x08000000 /* IO Tracing Debug */
348 #define ql_dbg_dpc 0x04000000 /* DPC Thead Debug */
349 #define ql_dbg_async 0x02000000 /* Async events Debug */
350 #define ql_dbg_timer 0x01000000 /* Timer Debug */
351 #define ql_dbg_user 0x00800000 /* User Space Interations Debug */
352 #define ql_dbg_taskm 0x00400000 /* Task Management Debug */
353 #define ql_dbg_aer 0x00200000 /* AER/EEH Debug */
354 #define ql_dbg_multiq 0x00100000 /* MultiQ Debug */
355 #define ql_dbg_p3p 0x00080000 /* P3P specific Debug */
356 #define ql_dbg_vport 0x00040000 /* Virtual Port Debug */
357 #define ql_dbg_buffer 0x00020000 /* For dumping the buffer/regs */
358 #define ql_dbg_misc 0x00010000 /* For dumping everything that is not
361 #define ql_dbg_verbose 0x00008000 /* More verbosity for each level
366 #define ql_dbg_tgt 0x00004000 /* Target mode */
367 #define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */
368 #define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */
369 #define ql_dbg_tgt_dif 0x00000800 /* Target mode dif */
370 #define ql_dbg_edif 0x00000400 /* edif and purex debug */
402 u32 dbg_off = dbg_msg ? ql_dbg_offset : 0; \
404 pbuf[0] = 0; \
421 } while (0)