Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x03ffffff
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
18 * 3. Neither the names of the above-listed copyright holders nor the names
55 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value); in pm80xx_bar4_shift()
59 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER); in pm80xx_bar4_shift()
62 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n", in pm80xx_bar4_shift()
64 return -1; in pm80xx_bar4_shift()
66 return 0; in pm80xx_bar4_shift()
75 for (index = 0; index < dw_count; index += 4, destination++) { in pm80xx_pci_mem_copy()
90 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; in pm80xx_get_fatal_dump()
91 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr; in pm80xx_get_fatal_dump()
100 pm8001_ha->forensic_info.data_buf.direct_data = buf; in pm80xx_get_fatal_dump()
101 if (pm8001_ha->chip_id == chip_8001) { in pm80xx_get_fatal_dump()
102 pm8001_ha->forensic_info.data_buf.direct_data += in pm80xx_get_fatal_dump()
103 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, in pm80xx_get_fatal_dump()
105 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - in pm80xx_get_fatal_dump()
109 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { in pm80xx_get_fatal_dump()
113 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL; in pm80xx_get_fatal_dump()
114 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET; in pm80xx_get_fatal_dump()
115 pm8001_ha->forensic_info.data_buf.direct_offset = 0; in pm80xx_get_fatal_dump()
116 pm8001_ha->forensic_info.data_buf.read_len = 0; in pm80xx_get_fatal_dump()
117 pm8001_ha->forensic_preserved_accumulated_transfer = 0; in pm80xx_get_fatal_dump()
121 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd); in pm80xx_get_fatal_dump()
123 pm8001_ha->forensic_info.data_buf.direct_data = direct_data; in pm80xx_get_fatal_dump()
125 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n", in pm80xx_get_fatal_dump()
126 pm8001_ha->forensic_info.data_buf.read_len); in pm80xx_get_fatal_dump()
127 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n", in pm80xx_get_fatal_dump()
128 pm8001_ha->forensic_info.data_buf.direct_len); in pm80xx_get_fatal_dump()
129 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n", in pm80xx_get_fatal_dump()
130 pm8001_ha->forensic_info.data_buf.direct_offset); in pm80xx_get_fatal_dump()
132 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) { in pm80xx_get_fatal_dump()
134 /* Program the MEMBASE II Shifting Register with 0x00.*/ in pm80xx_get_fatal_dump()
135 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, in pm80xx_get_fatal_dump()
136 pm8001_ha->fatal_forensic_shift_offset); in pm80xx_get_fatal_dump()
137 pm8001_ha->forensic_last_offset = 0; in pm80xx_get_fatal_dump()
138 pm8001_ha->forensic_fatal_step = 0; in pm80xx_get_fatal_dump()
139 pm8001_ha->fatal_bar_loc = 0; in pm80xx_get_fatal_dump()
149 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer; in pm80xx_get_fatal_dump()
150 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n", in pm80xx_get_fatal_dump()
152 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n", in pm80xx_get_fatal_dump()
154 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n", in pm80xx_get_fatal_dump()
155 pm8001_ha->forensic_last_offset); in pm80xx_get_fatal_dump()
156 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n", in pm80xx_get_fatal_dump()
157 pm8001_ha->forensic_info.data_buf.read_len); in pm80xx_get_fatal_dump()
158 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n", in pm80xx_get_fatal_dump()
159 pm8001_ha->forensic_info.data_buf.direct_len); in pm80xx_get_fatal_dump()
160 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n", in pm80xx_get_fatal_dump()
161 pm8001_ha->forensic_info.data_buf.direct_offset); in pm80xx_get_fatal_dump()
164 if (accum_len == 0xFFFFFFFF) { in pm80xx_get_fatal_dump()
166 "Possible PCI issue 0x%x not expected\n", in pm80xx_get_fatal_dump()
171 if (accum_len == 0) { in pm80xx_get_fatal_dump()
172 pm8001_ha->forensic_info.data_buf.direct_data += in pm80xx_get_fatal_dump()
173 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, in pm80xx_get_fatal_dump()
174 "%08x ", 0xFFFFFFFF); in pm80xx_get_fatal_dump()
175 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - in pm80xx_get_fatal_dump()
179 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; in pm80xx_get_fatal_dump()
180 if (pm8001_ha->forensic_fatal_step == 0) { in pm80xx_get_fatal_dump()
185 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET in pm80xx_get_fatal_dump()
187 pm8001_ha->forensic_info.data_buf.direct_len = in pm80xx_get_fatal_dump()
188 length_to_read - in pm80xx_get_fatal_dump()
189 pm8001_ha->forensic_last_offset; in pm80xx_get_fatal_dump()
191 pm8001_ha->forensic_info.data_buf.direct_len = in pm80xx_get_fatal_dump()
194 if (pm8001_ha->forensic_info.data_buf.direct_data) { in pm80xx_get_fatal_dump()
197 pm8001_ha->fatal_bar_loc, in pm80xx_get_fatal_dump()
198 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr, in pm80xx_get_fatal_dump()
199 pm8001_ha->forensic_info.data_buf.direct_len, 1); in pm80xx_get_fatal_dump()
201 pm8001_ha->fatal_bar_loc += in pm80xx_get_fatal_dump()
202 pm8001_ha->forensic_info.data_buf.direct_len; in pm80xx_get_fatal_dump()
203 pm8001_ha->forensic_info.data_buf.direct_offset += in pm80xx_get_fatal_dump()
204 pm8001_ha->forensic_info.data_buf.direct_len; in pm80xx_get_fatal_dump()
205 pm8001_ha->forensic_last_offset += in pm80xx_get_fatal_dump()
206 pm8001_ha->forensic_info.data_buf.direct_len; in pm80xx_get_fatal_dump()
207 pm8001_ha->forensic_info.data_buf.read_len = in pm80xx_get_fatal_dump()
208 pm8001_ha->forensic_info.data_buf.direct_len; in pm80xx_get_fatal_dump()
210 if (pm8001_ha->forensic_last_offset >= length_to_read) { in pm80xx_get_fatal_dump()
211 pm8001_ha->forensic_info.data_buf.direct_data += in pm80xx_get_fatal_dump()
212 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, in pm80xx_get_fatal_dump()
214 for (index = 0; index < in pm80xx_get_fatal_dump()
215 (pm8001_ha->forensic_info.data_buf.direct_len in pm80xx_get_fatal_dump()
217 pm8001_ha->forensic_info.data_buf.direct_data += in pm80xx_get_fatal_dump()
219 pm8001_ha->forensic_info.data_buf.direct_data, in pm80xx_get_fatal_dump()
223 pm8001_ha->fatal_bar_loc = 0; in pm80xx_get_fatal_dump()
224 pm8001_ha->forensic_fatal_step = 1; in pm80xx_get_fatal_dump()
225 pm8001_ha->fatal_forensic_shift_offset = 0; in pm80xx_get_fatal_dump()
226 pm8001_ha->forensic_last_offset = 0; in pm80xx_get_fatal_dump()
227 status = 0; in pm80xx_get_fatal_dump()
229 ((char *)pm8001_ha->forensic_info.data_buf.direct_data in pm80xx_get_fatal_dump()
230 - (char *)buf); in pm80xx_get_fatal_dump()
232 "get_fatal_spcv:return1 0x%x\n", offset); in pm80xx_get_fatal_dump()
233 return (char *)pm8001_ha-> in pm80xx_get_fatal_dump()
234 forensic_info.data_buf.direct_data - in pm80xx_get_fatal_dump()
237 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) { in pm80xx_get_fatal_dump()
238 pm8001_ha->forensic_info.data_buf.direct_data += in pm80xx_get_fatal_dump()
239 sprintf(pm8001_ha-> in pm80xx_get_fatal_dump()
242 for (index = 0; index < in pm80xx_get_fatal_dump()
243 (pm8001_ha->forensic_info.data_buf.direct_len in pm80xx_get_fatal_dump()
245 pm8001_ha->forensic_info.data_buf.direct_data in pm80xx_get_fatal_dump()
246 += sprintf(pm8001_ha-> in pm80xx_get_fatal_dump()
250 status = 0; in pm80xx_get_fatal_dump()
252 ((char *)pm8001_ha->forensic_info.data_buf.direct_data in pm80xx_get_fatal_dump()
253 - (char *)buf); in pm80xx_get_fatal_dump()
255 "get_fatal_spcv:return2 0x%x\n", offset); in pm80xx_get_fatal_dump()
256 return (char *)pm8001_ha-> in pm80xx_get_fatal_dump()
257 forensic_info.data_buf.direct_data - in pm80xx_get_fatal_dump()
261 /* Increment the MEMBASE II Shifting Register value by 0x100.*/ in pm80xx_get_fatal_dump()
262 pm8001_ha->forensic_info.data_buf.direct_data += in pm80xx_get_fatal_dump()
263 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, in pm80xx_get_fatal_dump()
265 for (index = 0; index < in pm80xx_get_fatal_dump()
266 (pm8001_ha->forensic_info.data_buf.direct_len in pm80xx_get_fatal_dump()
268 pm8001_ha->forensic_info.data_buf.direct_data += in pm80xx_get_fatal_dump()
269 sprintf(pm8001_ha-> in pm80xx_get_fatal_dump()
273 pm8001_ha->fatal_forensic_shift_offset += 0x100; in pm80xx_get_fatal_dump()
274 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, in pm80xx_get_fatal_dump()
275 pm8001_ha->fatal_forensic_shift_offset); in pm80xx_get_fatal_dump()
276 pm8001_ha->fatal_bar_loc = 0; in pm80xx_get_fatal_dump()
277 status = 0; in pm80xx_get_fatal_dump()
279 ((char *)pm8001_ha->forensic_info.data_buf.direct_data in pm80xx_get_fatal_dump()
280 - (char *)buf); in pm80xx_get_fatal_dump()
281 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n", in pm80xx_get_fatal_dump()
283 return (char *)pm8001_ha->forensic_info.data_buf.direct_data - in pm80xx_get_fatal_dump()
286 if (pm8001_ha->forensic_fatal_step == 1) { in pm80xx_get_fatal_dump()
290 pm8001_ha->forensic_preserved_accumulated_transfer = in pm80xx_get_fatal_dump()
294 /* continue capturing the fatal log until Dump status is 0x3 */ in pm80xx_get_fatal_dump()
301 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0); in pm80xx_get_fatal_dump()
318 if (reg_val != 0) { in pm80xx_get_fatal_dump()
320 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n", in pm80xx_get_fatal_dump()
323 pm8001_ha->forensic_info.data_buf.direct_data += in pm80xx_get_fatal_dump()
325 pm8001_ha->forensic_info.data_buf.direct_data, in pm80xx_get_fatal_dump()
326 "%08x ", 0xFFFFFFFF); in pm80xx_get_fatal_dump()
328 pm8001_ha->forensic_info.data_buf.direct_data in pm80xx_get_fatal_dump()
329 - (char *)buf); in pm80xx_get_fatal_dump()
344 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n", in pm80xx_get_fatal_dump()
347 pm8001_ha->forensic_info.data_buf.direct_data += in pm80xx_get_fatal_dump()
349 pm8001_ha->forensic_info.data_buf.direct_data, in pm80xx_get_fatal_dump()
350 "%08x ", 0xFFFFFFFF); in pm80xx_get_fatal_dump()
351 return((char *)pm8001_ha->forensic_info.data_buf.direct_data - in pm80xx_get_fatal_dump()
355 pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */ in pm80xx_get_fatal_dump()
356 pm8001_cw32(pm8001_ha, 0, in pm80xx_get_fatal_dump()
358 pm8001_ha->fatal_forensic_shift_offset); in pm80xx_get_fatal_dump()
362 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) - in pm80xx_get_fatal_dump()
363 pm8001_ha->forensic_preserved_accumulated_transfer; in pm80xx_get_fatal_dump()
364 if (length_to_read != 0x0) { in pm80xx_get_fatal_dump()
365 pm8001_ha->forensic_fatal_step = 0; in pm80xx_get_fatal_dump()
368 pm8001_ha->forensic_info.data_buf.direct_data += in pm80xx_get_fatal_dump()
369 sprintf(pm8001_ha->forensic_info.data_buf.direct_data, in pm80xx_get_fatal_dump()
371 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF; in pm80xx_get_fatal_dump()
372 pm8001_ha->forensic_info.data_buf.direct_len = 0; in pm80xx_get_fatal_dump()
373 pm8001_ha->forensic_info.data_buf.direct_offset = 0; in pm80xx_get_fatal_dump()
374 pm8001_ha->forensic_info.data_buf.read_len = 0; in pm80xx_get_fatal_dump()
377 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data in pm80xx_get_fatal_dump()
378 - (char *)buf); in pm80xx_get_fatal_dump()
379 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset); in pm80xx_get_fatal_dump()
380 return ((char *)pm8001_ha->forensic_info.data_buf.direct_data - in pm80xx_get_fatal_dump()
384 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
392 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha; in pm80xx_get_non_fatal_dump()
393 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr; in pm80xx_get_non_fatal_dump()
394 u32 accum_len = 0; in pm80xx_get_non_fatal_dump()
395 u32 total_len = 0; in pm80xx_get_non_fatal_dump()
396 u32 reg_val = 0; in pm80xx_get_non_fatal_dump()
398 u32 index = 0; in pm80xx_get_non_fatal_dump()
400 unsigned long start = 0; in pm80xx_get_non_fatal_dump()
403 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr; in pm80xx_get_non_fatal_dump()
404 if (++pm8001_ha->non_fatal_count == 1) { in pm80xx_get_non_fatal_dump()
405 if (pm8001_ha->chip_id == chip_8001) { in pm80xx_get_non_fatal_dump()
406 snprintf(pm8001_ha->forensic_info.data_buf.direct_data, in pm80xx_get_non_fatal_dump()
408 return 0; in pm80xx_get_non_fatal_dump()
413 * Non-Fatal Error Dump Capture Table.This is the buffer in pm80xx_get_non_fatal_dump()
418 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo); in pm80xx_get_non_fatal_dump()
422 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi); in pm80xx_get_non_fatal_dump()
428 * keeps sending active I/Os while capturing the non-fatal in pm80xx_get_non_fatal_dump()
436 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump in pm80xx_get_non_fatal_dump()
440 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0); in pm80xx_get_non_fatal_dump()
442 /* initiallize previous accumulated length to 0 */ in pm80xx_get_non_fatal_dump()
443 pm8001_ha->forensic_preserved_accumulated_transfer = 0; in pm80xx_get_non_fatal_dump()
444 pm8001_ha->non_fatal_read_length = 0; in pm80xx_get_non_fatal_dump()
450 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT] in pm80xx_get_non_fatal_dump()
454 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0); in pm80xx_get_non_fatal_dump()
455 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, in pm80xx_get_non_fatal_dump()
465 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) & in pm80xx_get_non_fatal_dump()
467 } while ((reg_val != 0) && time_before(jiffies, start)); in pm80xx_get_non_fatal_dump()
471 * the MPI Fatal and Non-Fatal Error Dump Capture Table. in pm80xx_get_non_fatal_dump()
479 if ((reg_val == 0x00) || in pm80xx_get_non_fatal_dump()
482 pm8001_ha->non_fatal_read_length = 0; in pm80xx_get_non_fatal_dump()
483 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF); in pm80xx_get_non_fatal_dump()
484 pm8001_ha->non_fatal_count = 0; in pm80xx_get_non_fatal_dump()
485 return (buf_copy - buf); in pm80xx_get_non_fatal_dump()
490 (pm8001_ha->non_fatal_read_length >= total_len)) { in pm80xx_get_non_fatal_dump()
491 pm8001_ha->non_fatal_read_length = 0; in pm80xx_get_non_fatal_dump()
493 pm8001_ha->non_fatal_count = 0; in pm80xx_get_non_fatal_dump()
497 output_length = accum_len - in pm80xx_get_non_fatal_dump()
498 pm8001_ha->forensic_preserved_accumulated_transfer; in pm80xx_get_non_fatal_dump()
500 for (index = 0; index < output_length/4; index++) in pm80xx_get_non_fatal_dump()
504 pm8001_ha->non_fatal_read_length += output_length; in pm80xx_get_non_fatal_dump()
509 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len; in pm80xx_get_non_fatal_dump()
510 return (buf_copy - buf); in pm80xx_get_non_fatal_dump()
514 * read_main_config_table - read the configure table and save it.
519 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; in read_main_config_table()
521 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature = in read_main_config_table()
523 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev = in read_main_config_table()
525 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev = in read_main_config_table()
527 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io = in read_main_config_table()
529 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl = in read_main_config_table()
531 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag = in read_main_config_table()
533 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset = in read_main_config_table()
535 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset = in read_main_config_table()
537 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset = in read_main_config_table()
541 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 = in read_main_config_table()
543 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 = in read_main_config_table()
545 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 = in read_main_config_table()
547 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 = in read_main_config_table()
551 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping = in read_main_config_table()
555 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset = in read_main_config_table()
558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset = in read_main_config_table()
560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset = in read_main_config_table()
563 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer = in read_main_config_table()
566 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version = in read_main_config_table()
568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version = in read_main_config_table()
573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature, in read_main_config_table()
574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev, in read_main_config_table()
575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev); in read_main_config_table()
579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset, in read_main_config_table()
580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset, in read_main_config_table()
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset, in read_main_config_table()
582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset, in read_main_config_table()
583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset); in read_main_config_table()
587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version, in read_main_config_table()
588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version); in read_main_config_table()
592 * read_general_status_table - read the general status table and save it.
597 void __iomem *address = pm8001_ha->general_stat_tbl_addr; in read_general_status_table()
598 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate = in read_general_status_table()
600 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 = in read_general_status_table()
602 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 = in read_general_status_table()
604 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt = in read_general_status_table()
606 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt = in read_general_status_table()
608 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val = in read_general_status_table()
610 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] = in read_general_status_table()
612 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] = in read_general_status_table()
614 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] = in read_general_status_table()
616 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] = in read_general_status_table()
618 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] = in read_general_status_table()
620 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] = in read_general_status_table()
622 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] = in read_general_status_table()
624 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] = in read_general_status_table()
628 * read_phy_attr_table - read the phy attribute table and save it.
633 void __iomem *address = pm8001_ha->pspa_q_tbl_addr; in read_phy_attr_table()
634 pm8001_ha->phy_attr_table.phystart1_16[0] = in read_phy_attr_table()
636 pm8001_ha->phy_attr_table.phystart1_16[1] = in read_phy_attr_table()
638 pm8001_ha->phy_attr_table.phystart1_16[2] = in read_phy_attr_table()
640 pm8001_ha->phy_attr_table.phystart1_16[3] = in read_phy_attr_table()
642 pm8001_ha->phy_attr_table.phystart1_16[4] = in read_phy_attr_table()
644 pm8001_ha->phy_attr_table.phystart1_16[5] = in read_phy_attr_table()
646 pm8001_ha->phy_attr_table.phystart1_16[6] = in read_phy_attr_table()
648 pm8001_ha->phy_attr_table.phystart1_16[7] = in read_phy_attr_table()
650 pm8001_ha->phy_attr_table.phystart1_16[8] = in read_phy_attr_table()
652 pm8001_ha->phy_attr_table.phystart1_16[9] = in read_phy_attr_table()
654 pm8001_ha->phy_attr_table.phystart1_16[10] = in read_phy_attr_table()
656 pm8001_ha->phy_attr_table.phystart1_16[11] = in read_phy_attr_table()
658 pm8001_ha->phy_attr_table.phystart1_16[12] = in read_phy_attr_table()
660 pm8001_ha->phy_attr_table.phystart1_16[13] = in read_phy_attr_table()
662 pm8001_ha->phy_attr_table.phystart1_16[14] = in read_phy_attr_table()
664 pm8001_ha->phy_attr_table.phystart1_16[15] = in read_phy_attr_table()
667 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] = in read_phy_attr_table()
669 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] = in read_phy_attr_table()
671 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] = in read_phy_attr_table()
673 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] = in read_phy_attr_table()
675 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] = in read_phy_attr_table()
677 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] = in read_phy_attr_table()
679 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] = in read_phy_attr_table()
681 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] = in read_phy_attr_table()
683 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] = in read_phy_attr_table()
685 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] = in read_phy_attr_table()
687 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] = in read_phy_attr_table()
689 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] = in read_phy_attr_table()
691 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] = in read_phy_attr_table()
693 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] = in read_phy_attr_table()
695 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] = in read_phy_attr_table()
697 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] = in read_phy_attr_table()
703 * read_inbnd_queue_table - read the inbound queue table and save it.
709 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; in read_inbnd_queue_table()
710 for (i = 0; i < PM8001_MAX_INB_NUM; i++) { in read_inbnd_queue_table()
711 u32 offset = i * 0x20; in read_inbnd_queue_table()
712 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = in read_inbnd_queue_table()
715 pm8001_ha->inbnd_q_tbl[i].pi_offset = in read_inbnd_queue_table()
721 * read_outbnd_queue_table - read the outbound queue table and save it.
727 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; in read_outbnd_queue_table()
728 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) { in read_outbnd_queue_table()
729 u32 offset = i * 0x24; in read_outbnd_queue_table()
730 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = in read_outbnd_queue_table()
733 pm8001_ha->outbnd_q_tbl[i].ci_offset = in read_outbnd_queue_table()
739 * init_default_table_values - init the default table.
746 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr; in init_default_table_values()
747 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr; in init_default_table_values()
748 u32 ib_offset = pm8001_ha->ib_offset; in init_default_table_values()
749 u32 ob_offset = pm8001_ha->ob_offset; in init_default_table_values()
750 u32 ci_offset = pm8001_ha->ci_offset; in init_default_table_values()
751 u32 pi_offset = pm8001_ha->pi_offset; in init_default_table_values()
753 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr = in init_default_table_values()
754 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi; in init_default_table_values()
755 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr = in init_default_table_values()
756 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo; in init_default_table_values()
757 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size = in init_default_table_values()
759 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01; in init_default_table_values()
760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr = in init_default_table_values()
761 pm8001_ha->memoryMap.region[IOP].phys_addr_hi; in init_default_table_values()
762 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr = in init_default_table_values()
763 pm8001_ha->memoryMap.region[IOP].phys_addr_lo; in init_default_table_values()
764 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size = in init_default_table_values()
766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; in init_default_table_values()
767 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; in init_default_table_values()
770 if (pm8001_ha->max_q_num > 32) in init_default_table_values()
771 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= in init_default_table_values()
774 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); in init_default_table_values()
776 for (i = 0; i < pm8001_ha->max_q_num; i++) { in init_default_table_values()
777 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt = in init_default_table_values()
778 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30); in init_default_table_values()
779 pm8001_ha->inbnd_q_tbl[i].upper_base_addr = in init_default_table_values()
780 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi; in init_default_table_values()
781 pm8001_ha->inbnd_q_tbl[i].lower_base_addr = in init_default_table_values()
782 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo; in init_default_table_values()
783 pm8001_ha->inbnd_q_tbl[i].base_virt = in init_default_table_values()
784 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr; in init_default_table_values()
785 pm8001_ha->inbnd_q_tbl[i].total_length = in init_default_table_values()
786 pm8001_ha->memoryMap.region[ib_offset + i].total_len; in init_default_table_values()
787 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr = in init_default_table_values()
788 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi; in init_default_table_values()
789 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr = in init_default_table_values()
790 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo; in init_default_table_values()
791 pm8001_ha->inbnd_q_tbl[i].ci_virt = in init_default_table_values()
792 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr; in init_default_table_values()
793 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0); in init_default_table_values()
794 offsetib = i * 0x20; in init_default_table_values()
795 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar = in init_default_table_values()
797 (offsetib + 0x14))); in init_default_table_values()
798 pm8001_ha->inbnd_q_tbl[i].pi_offset = in init_default_table_values()
799 pm8001_mr32(addressib, (offsetib + 0x18)); in init_default_table_values()
800 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0; in init_default_table_values()
801 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0; in init_default_table_values()
804 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i, in init_default_table_values()
805 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar, in init_default_table_values()
806 pm8001_ha->inbnd_q_tbl[i].pi_offset); in init_default_table_values()
808 for (i = 0; i < pm8001_ha->max_q_num; i++) { in init_default_table_values()
809 pm8001_ha->outbnd_q_tbl[i].element_size_cnt = in init_default_table_values()
810 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30); in init_default_table_values()
811 pm8001_ha->outbnd_q_tbl[i].upper_base_addr = in init_default_table_values()
812 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi; in init_default_table_values()
813 pm8001_ha->outbnd_q_tbl[i].lower_base_addr = in init_default_table_values()
814 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo; in init_default_table_values()
815 pm8001_ha->outbnd_q_tbl[i].base_virt = in init_default_table_values()
816 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr; in init_default_table_values()
817 pm8001_ha->outbnd_q_tbl[i].total_length = in init_default_table_values()
818 pm8001_ha->memoryMap.region[ob_offset + i].total_len; in init_default_table_values()
819 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr = in init_default_table_values()
820 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi; in init_default_table_values()
821 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr = in init_default_table_values()
822 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo; in init_default_table_values()
824 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24); in init_default_table_values()
825 pm8001_ha->outbnd_q_tbl[i].pi_virt = in init_default_table_values()
826 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr; in init_default_table_values()
827 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0); in init_default_table_values()
828 offsetob = i * 0x24; in init_default_table_values()
829 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar = in init_default_table_values()
831 offsetob + 0x14)); in init_default_table_values()
832 pm8001_ha->outbnd_q_tbl[i].ci_offset = in init_default_table_values()
833 pm8001_mr32(addressob, (offsetob + 0x18)); in init_default_table_values()
834 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0; in init_default_table_values()
835 pm8001_ha->outbnd_q_tbl[i].producer_index = 0; in init_default_table_values()
838 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i, in init_default_table_values()
839 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar, in init_default_table_values()
840 pm8001_ha->outbnd_q_tbl[i].ci_offset); in init_default_table_values()
845 * update_main_config_table - update the main default table to the HBA.
850 void __iomem *address = pm8001_ha->main_cfg_tbl_addr; in update_main_config_table()
852 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd); in update_main_config_table()
854 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr); in update_main_config_table()
856 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr); in update_main_config_table()
858 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size); in update_main_config_table()
860 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity); in update_main_config_table()
862 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr); in update_main_config_table()
864 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr); in update_main_config_table()
866 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size); in update_main_config_table()
868 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity); in update_main_config_table()
870 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= in update_main_config_table()
871 ((pm8001_ha->max_q_num - 1) << 8); in update_main_config_table()
873 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt); in update_main_config_table()
875 "Updated Fatal error interrupt vector 0x%x\n", in update_main_config_table()
879 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump); in update_main_config_table()
882 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF; in update_main_config_table()
883 /* Set GPIOLED to 0x2 for LED indicator */ in update_main_config_table()
884 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000; in update_main_config_table()
886 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping); in update_main_config_table()
888 "Programming DW 0x21 in main cfg table with 0x%x\n", in update_main_config_table()
892 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); in update_main_config_table()
894 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay); in update_main_config_table()
896 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000; in update_main_config_table()
897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= in update_main_config_table()
899 if (pm8001_ha->chip_id == chip_8006) { in update_main_config_table()
900 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= in update_main_config_table()
901 0x0000ffff; in update_main_config_table()
902 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |= in update_main_config_table()
906 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer); in update_main_config_table()
910 * update_inbnd_queue_table - update the inbound queue table to the HBA.
917 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr; in update_inbnd_queue_table()
918 u16 offset = number * 0x20; in update_inbnd_queue_table()
920 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); in update_inbnd_queue_table()
922 pm8001_ha->inbnd_q_tbl[number].upper_base_addr); in update_inbnd_queue_table()
924 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); in update_inbnd_queue_table()
926 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr); in update_inbnd_queue_table()
928 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); in update_inbnd_queue_table()
931 "IQ %d: Element pri size 0x%x\n", in update_inbnd_queue_table()
933 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt); in update_inbnd_queue_table()
936 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n", in update_inbnd_queue_table()
937 pm8001_ha->inbnd_q_tbl[number].upper_base_addr, in update_inbnd_queue_table()
938 pm8001_ha->inbnd_q_tbl[number].lower_base_addr); in update_inbnd_queue_table()
941 "CI upper base addr 0x%x CI lower base addr 0x%x\n", in update_inbnd_queue_table()
942 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr, in update_inbnd_queue_table()
943 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr); in update_inbnd_queue_table()
947 * update_outbnd_queue_table - update the outbound queue table to the HBA.
954 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr; in update_outbnd_queue_table()
955 u16 offset = number * 0x24; in update_outbnd_queue_table()
957 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); in update_outbnd_queue_table()
959 pm8001_ha->outbnd_q_tbl[number].upper_base_addr); in update_outbnd_queue_table()
961 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); in update_outbnd_queue_table()
963 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr); in update_outbnd_queue_table()
965 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); in update_outbnd_queue_table()
967 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay); in update_outbnd_queue_table()
970 "OQ %d: Element pri size 0x%x\n", in update_outbnd_queue_table()
972 pm8001_ha->outbnd_q_tbl[number].element_size_cnt); in update_outbnd_queue_table()
975 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n", in update_outbnd_queue_table()
976 pm8001_ha->outbnd_q_tbl[number].upper_base_addr, in update_outbnd_queue_table()
977 pm8001_ha->outbnd_q_tbl[number].lower_base_addr); in update_outbnd_queue_table()
980 "PI upper base addr 0x%x PI lower base addr 0x%x\n", in update_outbnd_queue_table()
981 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr, in update_outbnd_queue_table()
982 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr); in update_outbnd_queue_table()
986 * mpi_init_check - check firmware initialization status.
997 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE); in mpi_init_check()
999 if (IS_SPCV_12G(pm8001_ha->pdev)) { in mpi_init_check()
1006 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); in mpi_init_check()
1008 } while ((value != 0) && (--max_wait_count)); in mpi_init_check()
1015 return -EBUSY; in mpi_init_check()
1017 /* check the MPI-State for initialization up to 100ms*/ in mpi_init_check()
1022 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, in mpi_init_check()
1025 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count)); in mpi_init_check()
1027 return -EBUSY; in mpi_init_check()
1031 if (0x0000 != gst_len_mpistate) in mpi_init_check()
1032 return -EBUSY; in mpi_init_check()
1041 return 0; in mpi_init_check()
1045 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1055 int ret = 0; in check_fw_ready()
1061 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in check_fw_ready()
1062 } while ((value == 0xFFFFFFFF) && (--max_wait_count)); in check_fw_ready()
1065 if ((pm8001_ha->chip_id != chip_8008) && in check_fw_ready()
1066 (pm8001_ha->chip_id != chip_8009)) { in check_fw_ready()
1080 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in check_fw_ready()
1082 expected_mask) && (--max_wait_count)); in check_fw_ready()
1085 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n", in check_fw_ready()
1087 ret = -1; in check_fw_ready()
1091 (max_wait_time - max_wait_count) * FW_READY_INTERVAL); in check_fw_ready()
1104 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); in init_pci_device_addresses()
1110 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */ in init_pci_device_addresses()
1112 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n", in init_pci_device_addresses()
1118 pcilogic = (value & 0xFC000000) >> 26; in init_pci_device_addresses()
1120 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar); in init_pci_device_addresses()
1125 if (offset > pm8001_ha->io_mem[pcibar].memsize) { in init_pci_device_addresses()
1128 offset, pm8001_ha->io_mem[pcibar].memsize); in init_pci_device_addresses()
1129 return -EBUSY; in init_pci_device_addresses()
1131 pm8001_ha->main_cfg_tbl_addr = base_addr = in init_pci_device_addresses()
1132 pm8001_ha->io_mem[pcibar].memvirtaddr + offset; in init_pci_device_addresses()
1138 value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0); in init_pci_device_addresses()
1139 if (memcmp(&value, "PMCS", 4) != 0) { in init_pci_device_addresses()
1141 "BAD main config signature 0x%x\n", in init_pci_device_addresses()
1143 return -EBUSY; in init_pci_device_addresses()
1146 "VALID main config signature 0x%x\n", value); in init_pci_device_addresses()
1147 pm8001_ha->general_stat_tbl_addr = in init_pci_device_addresses()
1148 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) & in init_pci_device_addresses()
1149 0xFFFFFF); in init_pci_device_addresses()
1150 pm8001_ha->inbnd_q_tbl_addr = in init_pci_device_addresses()
1151 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) & in init_pci_device_addresses()
1152 0xFFFFFF); in init_pci_device_addresses()
1153 pm8001_ha->outbnd_q_tbl_addr = in init_pci_device_addresses()
1154 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) & in init_pci_device_addresses()
1155 0xFFFFFF); in init_pci_device_addresses()
1156 pm8001_ha->ivt_tbl_addr = in init_pci_device_addresses()
1157 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) & in init_pci_device_addresses()
1158 0xFFFFFF); in init_pci_device_addresses()
1159 pm8001_ha->pspa_q_tbl_addr = in init_pci_device_addresses()
1160 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) & in init_pci_device_addresses()
1161 0xFFFFFF); in init_pci_device_addresses()
1162 pm8001_ha->fatal_tbl_addr = in init_pci_device_addresses()
1163 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) & in init_pci_device_addresses()
1164 0xFFFFFF); in init_pci_device_addresses()
1166 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n", in init_pci_device_addresses()
1167 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)); in init_pci_device_addresses()
1168 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n", in init_pci_device_addresses()
1169 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)); in init_pci_device_addresses()
1170 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n", in init_pci_device_addresses()
1171 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)); in init_pci_device_addresses()
1172 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n", in init_pci_device_addresses()
1173 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)); in init_pci_device_addresses()
1174 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n", in init_pci_device_addresses()
1175 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)); in init_pci_device_addresses()
1176 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n", in init_pci_device_addresses()
1177 pm8001_ha->main_cfg_tbl_addr, in init_pci_device_addresses()
1178 pm8001_ha->general_stat_tbl_addr); in init_pci_device_addresses()
1179 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n", in init_pci_device_addresses()
1180 pm8001_ha->inbnd_q_tbl_addr, in init_pci_device_addresses()
1181 pm8001_ha->outbnd_q_tbl_addr); in init_pci_device_addresses()
1182 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n", in init_pci_device_addresses()
1183 pm8001_ha->pspa_q_tbl_addr, in init_pci_device_addresses()
1184 pm8001_ha->ivt_tbl_addr); in init_pci_device_addresses()
1185 return 0; in init_pci_device_addresses()
1189 * pm80xx_set_thermal_config - support the thermal configuration
1201 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); in pm80xx_set_thermal_config()
1208 if (IS_SPCV_12G(pm8001_ha->pdev)) in pm80xx_set_thermal_config()
1213 payload.cfg_pg[0] = in pm80xx_set_thermal_config()
1220 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n", in pm80xx_set_thermal_config()
1221 payload.cfg_pg[0], payload.cfg_pg[1]); in pm80xx_set_thermal_config()
1223 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, in pm80xx_set_thermal_config()
1224 sizeof(payload), 0); in pm80xx_set_thermal_config()
1232 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1245 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req)); in pm80xx_set_sas_protocol_timer_config()
1246 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t)); in pm80xx_set_sas_protocol_timer_config()
1271 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n", in pm80xx_set_sas_protocol_timer_config()
1273 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n", in pm80xx_set_sas_protocol_timer_config()
1275 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n", in pm80xx_set_sas_protocol_timer_config()
1277 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n", in pm80xx_set_sas_protocol_timer_config()
1279 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n", in pm80xx_set_sas_protocol_timer_config()
1281 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n", in pm80xx_set_sas_protocol_timer_config()
1283 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n", in pm80xx_set_sas_protocol_timer_config()
1285 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n", in pm80xx_set_sas_protocol_timer_config()
1287 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n", in pm80xx_set_sas_protocol_timer_config()
1293 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, in pm80xx_set_sas_protocol_timer_config()
1294 sizeof(payload), 0); in pm80xx_set_sas_protocol_timer_config()
1302 * pm80xx_get_encrypt_info - Check for encryption
1309 int ret = -1; in pm80xx_get_encrypt_info()
1312 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); in pm80xx_get_encrypt_info()
1317 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; in pm80xx_get_encrypt_info()
1320 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; in pm80xx_get_encrypt_info()
1323 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; in pm80xx_get_encrypt_info()
1326 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; in pm80xx_get_encrypt_info()
1327 pm8001_ha->encrypt_info.status = 0; in pm80xx_get_encrypt_info()
1329 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n", in pm80xx_get_encrypt_info()
1331 pm8001_ha->encrypt_info.cipher_mode, in pm80xx_get_encrypt_info()
1332 pm8001_ha->encrypt_info.sec_mode, in pm80xx_get_encrypt_info()
1333 pm8001_ha->encrypt_info.status); in pm80xx_get_encrypt_info()
1334 ret = 0; in pm80xx_get_encrypt_info()
1338 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n", in pm80xx_get_encrypt_info()
1340 pm8001_ha->encrypt_info.status = 0xFFFFFFFF; in pm80xx_get_encrypt_info()
1341 pm8001_ha->encrypt_info.cipher_mode = 0; in pm80xx_get_encrypt_info()
1342 pm8001_ha->encrypt_info.sec_mode = 0; in pm80xx_get_encrypt_info()
1343 ret = 0; in pm80xx_get_encrypt_info()
1346 pm8001_ha->encrypt_info.status = in pm80xx_get_encrypt_info()
1349 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; in pm80xx_get_encrypt_info()
1352 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; in pm80xx_get_encrypt_info()
1355 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; in pm80xx_get_encrypt_info()
1358 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; in pm80xx_get_encrypt_info()
1360 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", in pm80xx_get_encrypt_info()
1362 pm8001_ha->encrypt_info.cipher_mode, in pm80xx_get_encrypt_info()
1363 pm8001_ha->encrypt_info.sec_mode, in pm80xx_get_encrypt_info()
1364 pm8001_ha->encrypt_info.status); in pm80xx_get_encrypt_info()
1368 pm8001_ha->encrypt_info.status = in pm80xx_get_encrypt_info()
1371 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS; in pm80xx_get_encrypt_info()
1374 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF; in pm80xx_get_encrypt_info()
1377 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA; in pm80xx_get_encrypt_info()
1380 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB; in pm80xx_get_encrypt_info()
1383 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n", in pm80xx_get_encrypt_info()
1385 pm8001_ha->encrypt_info.cipher_mode, in pm80xx_get_encrypt_info()
1386 pm8001_ha->encrypt_info.sec_mode, in pm80xx_get_encrypt_info()
1387 pm8001_ha->encrypt_info.status); in pm80xx_get_encrypt_info()
1393 * pm80xx_encrypt_update - update flash with encryption information
1403 memset(&payload, 0, sizeof(struct kek_mgmt_req)); in pm80xx_encrypt_update()
1417 "Saving Encryption info to flash. payload 0x%x\n", in pm80xx_encrypt_update()
1420 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, in pm80xx_encrypt_update()
1421 sizeof(payload), 0); in pm80xx_encrypt_update()
1429 * pm80xx_chip_init - the main init function that initializes whole PM8001 chip.
1435 u8 i = 0; in pm80xx_chip_init()
1438 if (-1 == check_fw_ready(pm8001_ha)) { in pm80xx_chip_init()
1440 return -EBUSY; in pm80xx_chip_init()
1444 pm8001_ha->controller_fatal_error = false; in pm80xx_chip_init()
1462 for (i = 0; i < pm8001_ha->max_q_num; i++) { in pm80xx_chip_init()
1467 if (0 == mpi_init_check(pm8001_ha)) { in pm80xx_chip_init()
1470 return -EBUSY; in pm80xx_chip_init()
1472 return 0; in pm80xx_chip_init()
1481 if (pm8001_ha->chip->encrypt) { in pm80xx_chip_post_init()
1486 if (ret == -1) { in pm80xx_chip_post_init()
1488 if (pm8001_ha->encrypt_info.status == 0x81) { in pm80xx_chip_post_init()
1513 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET); in mpi_uninit_check()
1516 if (IS_SPCV_12G(pm8001_ha->pdev)) { in mpi_uninit_check()
1523 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET); in mpi_uninit_check()
1525 } while ((value != 0) && (--max_wait_count)); in mpi_uninit_check()
1529 return -1; in mpi_uninit_check()
1532 /* check the MPI-State for termination in progress */ in mpi_uninit_check()
1538 pm8001_mr32(pm8001_ha->general_stat_tbl_addr, in mpi_uninit_check()
1543 } while (--max_wait_count); in mpi_uninit_check()
1545 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n", in mpi_uninit_check()
1547 return -1; in mpi_uninit_check()
1550 return 0; in mpi_uninit_check()
1554 * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors
1562 int ret = 0; in pm80xx_fatal_errors()
1563 u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0, in pm80xx_fatal_errors()
1565 u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0, in pm80xx_fatal_errors()
1567 u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in pm80xx_fatal_errors()
1568 u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in pm80xx_fatal_errors()
1569 u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); in pm80xx_fatal_errors()
1571 if (pm8001_ha->chip_id != chip_8006 && in pm80xx_fatal_errors()
1572 pm8001_ha->chip_id != chip_8074 && in pm80xx_fatal_errors()
1573 pm8001_ha->chip_id != chip_8076) { in pm80xx_fatal_errors()
1574 return 0; in pm80xx_fatal_errors()
1579 …"Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRA… in pm80xx_fatal_errors()
1589 * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all
1602 if (!pm8001_ha->controller_fatal_error) { in pm80xx_chip_soft_rst()
1604 if (mpi_uninit_check(pm8001_ha) != 0) { in pm80xx_chip_soft_rst()
1605 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0); in pm80xx_chip_soft_rst()
1606 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in pm80xx_chip_soft_rst()
1607 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2); in pm80xx_chip_soft_rst()
1608 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3); in pm80xx_chip_soft_rst()
1616 return -1; in pm80xx_chip_soft_rst()
1619 /* checked for reset register normal state; 0x0 */ in pm80xx_chip_soft_rst()
1620 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); in pm80xx_chip_soft_rst()
1621 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n", in pm80xx_chip_soft_rst()
1624 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE); in pm80xx_chip_soft_rst()
1627 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET); in pm80xx_chip_soft_rst()
1628 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n", in pm80xx_chip_soft_rst()
1634 " soft reset successful [regval: 0x%x]\n", in pm80xx_chip_soft_rst()
1638 " soft reset failed [regval: 0x%x]\n", in pm80xx_chip_soft_rst()
1643 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) & in pm80xx_chip_soft_rst()
1648 "Bootloader state - HDA mode SEEPROM\n"); in pm80xx_chip_soft_rst()
1652 "Bootloader state - HDA mode Bootstrap Pin\n"); in pm80xx_chip_soft_rst()
1656 "Bootloader state - HDA mode soft reset\n"); in pm80xx_chip_soft_rst()
1660 "Bootloader state-HDA mode critical error\n"); in pm80xx_chip_soft_rst()
1662 return -EBUSY; in pm80xx_chip_soft_rst()
1666 if (-1 == check_fw_ready(pm8001_ha)) { in pm80xx_chip_soft_rst()
1669 if (pm8001_ha->pdev->subsystem_vendor != in pm80xx_chip_soft_rst()
1671 pm8001_ha->pdev->subsystem_vendor != in pm80xx_chip_soft_rst()
1673 pm8001_ha->pdev->subsystem_vendor != 0) { in pm80xx_chip_soft_rst()
1674 ibutton0 = pm8001_cr32(pm8001_ha, 0, in pm80xx_chip_soft_rst()
1676 ibutton1 = pm8001_cr32(pm8001_ha, 0, in pm80xx_chip_soft_rst()
1681 return -EBUSY; in pm80xx_chip_soft_rst()
1683 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) { in pm80xx_chip_soft_rst()
1686 return -EBUSY; in pm80xx_chip_soft_rst()
1691 return 0; in pm80xx_chip_soft_rst()
1701 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11); in pm80xx_hw_chip_rst()
1712 } while ((--i) != 0); in pm80xx_hw_chip_rst()
1718 * pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1724 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL); in pm80xx_chip_intx_interrupt_enable()
1725 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL); in pm80xx_chip_intx_interrupt_enable()
1729 * pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1735 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL); in pm80xx_chip_intx_interrupt_disable()
1739 * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt
1748 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec); in pm80xx_chip_interrupt_enable()
1750 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, in pm80xx_chip_interrupt_enable()
1751 1U << (vec - 32)); in pm80xx_chip_interrupt_enable()
1759 * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt
1767 if (vec == 0xFF) { in pm80xx_chip_interrupt_disable()
1768 /* disable all vectors 0-31, 32-63 */ in pm80xx_chip_interrupt_disable()
1769 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF); in pm80xx_chip_interrupt_disable()
1770 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF); in pm80xx_chip_interrupt_disable()
1772 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec); in pm80xx_chip_interrupt_disable()
1774 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, in pm80xx_chip_interrupt_disable()
1775 1U << (vec - 32)); in pm80xx_chip_interrupt_disable()
1790 pm8001_ha_dev->id |= NCQ_ABORT_ALL_FLAG; in pm80xx_send_abort_all()
1791 pm8001_ha_dev->id &= ~NCQ_READ_LOG_FLAG; in pm80xx_send_abort_all()
1798 task->task_done = pm8001_task_done; in pm80xx_send_abort_all()
1806 memset(&task_abort, 0, sizeof(task_abort)); in pm80xx_send_abort_all()
1808 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id); in pm80xx_send_abort_all()
1809 task_abort.tag = cpu_to_le32(ccb->ccb_tag); in pm80xx_send_abort_all()
1811 ret = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort, in pm80xx_send_abort_all()
1812 sizeof(task_abort), 0); in pm80xx_send_abort_all()
1836 task->task_done = pm8001_task_done; in pm80xx_send_read_log()
1850 task->dev = dev; in pm80xx_send_read_log()
1851 task->dev->lldd_dev = pm8001_ha_dev; in pm80xx_send_read_log()
1860 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG; in pm80xx_send_read_log()
1861 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG; in pm80xx_send_read_log()
1863 memset(&sata_cmd, 0, sizeof(sata_cmd)); in pm80xx_send_read_log()
1866 memset(&fis, 0, sizeof(struct host_to_dev_fis)); in pm80xx_send_read_log()
1867 fis.fis_type = 0x27; in pm80xx_send_read_log()
1868 fis.flags = 0x80; in pm80xx_send_read_log()
1870 fis.lbal = 0x10; in pm80xx_send_read_log()
1871 fis.sector_count = 0x1; in pm80xx_send_read_log()
1873 sata_cmd.tag = cpu_to_le32(ccb->ccb_tag); in pm80xx_send_read_log()
1874 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); in pm80xx_send_read_log()
1875 sata_cmd.ncqtag_atap_dir_m_dad = cpu_to_le32(((0x1 << 7) | (0x5 << 9))); in pm80xx_send_read_log()
1878 res = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd, in pm80xx_send_read_log()
1879 sizeof(sata_cmd), 0); in pm80xx_send_read_log()
1889 * mpi_ssp_completion - process the event that FW response to the SSP request.
1913 status = le32_to_cpu(psspPayload->status); in mpi_ssp_completion()
1914 tag = le32_to_cpu(psspPayload->tag); in mpi_ssp_completion()
1915 ccb = &pm8001_ha->ccb_info[tag]; in mpi_ssp_completion()
1916 if ((status == IO_ABORTED) && ccb->open_retry) { in mpi_ssp_completion()
1918 ccb->open_retry = 0; in mpi_ssp_completion()
1921 pm8001_dev = ccb->device; in mpi_ssp_completion()
1922 param = le32_to_cpu(psspPayload->param); in mpi_ssp_completion()
1923 t = ccb->task; in mpi_ssp_completion()
1926 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status); in mpi_ssp_completion()
1927 if (unlikely(!t || !t->lldd_task || !t->dev)) in mpi_ssp_completion()
1929 ts = &t->task_status; in mpi_ssp_completion()
1932 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t); in mpi_ssp_completion()
1938 SAS_ADDR(t->dev->sas_addr)); in mpi_ssp_completion()
1942 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n", in mpi_ssp_completion()
1944 if (param == 0) { in mpi_ssp_completion()
1945 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
1946 ts->stat = SAS_SAM_STAT_GOOD; in mpi_ssp_completion()
1948 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
1949 ts->stat = SAS_PROTO_RESPONSE; in mpi_ssp_completion()
1950 ts->residual = param; in mpi_ssp_completion()
1951 iu = &psspPayload->ssp_resp_iu; in mpi_ssp_completion()
1952 sas_ssp_task_response(pm8001_ha->dev, t, iu); in mpi_ssp_completion()
1955 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
1959 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
1960 ts->stat = SAS_ABORTED_TASK; in mpi_ssp_completion()
1962 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
1966 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n", in mpi_ssp_completion()
1968 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
1969 ts->stat = SAS_DATA_UNDERRUN; in mpi_ssp_completion()
1970 ts->residual = param; in mpi_ssp_completion()
1972 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
1976 ts->resp = SAS_TASK_UNDELIVERED; in mpi_ssp_completion()
1977 ts->stat = SAS_PHY_DOWN; in mpi_ssp_completion()
1979 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
1983 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
1984 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
1986 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_ssp_completion()
1988 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
1992 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
1993 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
1994 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_ssp_completion()
1996 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2001 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2002 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2003 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_ssp_completion()
2005 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2010 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2011 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2012 ts->open_rej_reason = SAS_OREJ_EPROTO; in mpi_ssp_completion()
2014 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2019 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2020 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2021 ts->open_rej_reason = SAS_OREJ_UNKNOWN; in mpi_ssp_completion()
2023 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2027 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2028 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2029 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_ssp_completion()
2031 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2040 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2041 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2042 ts->open_rej_reason = SAS_OREJ_UNKNOWN; in mpi_ssp_completion()
2043 if (!t->uldd_task) in mpi_ssp_completion()
2051 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2052 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2053 ts->open_rej_reason = SAS_OREJ_BAD_DEST; in mpi_ssp_completion()
2055 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2060 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2061 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2062 ts->open_rej_reason = SAS_OREJ_CONN_RATE; in mpi_ssp_completion()
2064 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2069 ts->resp = SAS_TASK_UNDELIVERED; in mpi_ssp_completion()
2070 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2071 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; in mpi_ssp_completion()
2073 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2077 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2078 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2079 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_ssp_completion()
2081 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2085 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2086 ts->stat = SAS_NAK_R_ERR; in mpi_ssp_completion()
2088 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2092 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2093 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2095 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2099 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2100 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2101 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_ssp_completion()
2103 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2107 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2108 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2110 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2114 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2115 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2117 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2121 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2122 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2123 if (!t->uldd_task) in mpi_ssp_completion()
2130 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2131 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2133 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2137 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2138 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2140 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2144 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2145 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2147 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2152 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2153 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2154 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_ssp_completion()
2156 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2159 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); in mpi_ssp_completion()
2161 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_completion()
2162 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_completion()
2164 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_completion()
2167 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ", in mpi_ssp_completion()
2168 psspPayload->ssp_resp_iu.status); in mpi_ssp_completion()
2169 spin_lock_irqsave(&t->task_state_lock, flags); in mpi_ssp_completion()
2170 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; in mpi_ssp_completion()
2171 t->task_state_flags |= SAS_TASK_STATE_DONE; in mpi_ssp_completion()
2172 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { in mpi_ssp_completion()
2173 spin_unlock_irqrestore(&t->task_state_lock, flags); in mpi_ssp_completion()
2175 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", in mpi_ssp_completion()
2176 t, status, ts->resp, ts->stat); in mpi_ssp_completion()
2178 if (t->slow_task) in mpi_ssp_completion()
2179 complete(&t->slow_task->completion); in mpi_ssp_completion()
2181 spin_unlock_irqrestore(&t->task_state_lock, flags); in mpi_ssp_completion()
2196 u32 event = le32_to_cpu(psspPayload->event); in mpi_ssp_event()
2197 u32 tag = le32_to_cpu(psspPayload->tag); in mpi_ssp_event()
2198 u32 port_id = le32_to_cpu(psspPayload->port_id); in mpi_ssp_event()
2200 ccb = &pm8001_ha->ccb_info[tag]; in mpi_ssp_event()
2201 t = ccb->task; in mpi_ssp_event()
2202 pm8001_dev = ccb->device; in mpi_ssp_event()
2204 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event); in mpi_ssp_event()
2205 if (unlikely(!t || !t->lldd_task || !t->dev)) in mpi_ssp_event()
2207 ts = &t->task_status; in mpi_ssp_event()
2208 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", in mpi_ssp_event()
2213 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2214 ts->stat = SAS_DATA_OVERRUN; in mpi_ssp_event()
2215 ts->residual = 0; in mpi_ssp_event()
2217 atomic_dec(&pm8001_dev->running_req); in mpi_ssp_event()
2225 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2226 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_event()
2227 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_ssp_event()
2232 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2233 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_event()
2234 ts->open_rej_reason = SAS_OREJ_EPROTO; in mpi_ssp_event()
2239 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2240 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_event()
2241 ts->open_rej_reason = SAS_OREJ_UNKNOWN; in mpi_ssp_event()
2245 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2246 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_event()
2247 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_ssp_event()
2256 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2257 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_event()
2258 ts->open_rej_reason = SAS_OREJ_UNKNOWN; in mpi_ssp_event()
2259 if (!t->uldd_task) in mpi_ssp_event()
2267 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2268 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_event()
2269 ts->open_rej_reason = SAS_OREJ_BAD_DEST; in mpi_ssp_event()
2274 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2275 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_event()
2276 ts->open_rej_reason = SAS_OREJ_CONN_RATE; in mpi_ssp_event()
2281 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2282 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_event()
2283 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; in mpi_ssp_event()
2287 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2288 ts->stat = SAS_OPEN_REJECT; in mpi_ssp_event()
2289 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_ssp_event()
2293 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2294 ts->stat = SAS_NAK_R_ERR; in mpi_ssp_event()
2302 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2303 ts->stat = SAS_DATA_OVERRUN; in mpi_ssp_event()
2307 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2308 ts->stat = SAS_DATA_OVERRUN; in mpi_ssp_event()
2313 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2314 ts->stat = SAS_DATA_OVERRUN; in mpi_ssp_event()
2319 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2320 ts->stat = SAS_DATA_OVERRUN; in mpi_ssp_event()
2324 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2325 ts->stat = SAS_DATA_OVERRUN; in mpi_ssp_event()
2330 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2331 ts->stat = SAS_DATA_OVERRUN; in mpi_ssp_event()
2337 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2338 ts->stat = SAS_DATA_OVERRUN; in mpi_ssp_event()
2344 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event); in mpi_ssp_event()
2346 ts->resp = SAS_TASK_COMPLETE; in mpi_ssp_event()
2347 ts->stat = SAS_DATA_OVERRUN; in mpi_ssp_event()
2350 spin_lock_irqsave(&t->task_state_lock, flags); in mpi_ssp_event()
2351 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; in mpi_ssp_event()
2352 t->task_state_flags |= SAS_TASK_STATE_DONE; in mpi_ssp_event()
2353 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { in mpi_ssp_event()
2354 spin_unlock_irqrestore(&t->task_state_lock, flags); in mpi_ssp_event()
2356 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", in mpi_ssp_event()
2357 t, event, ts->resp, ts->stat); in mpi_ssp_event()
2360 spin_unlock_irqrestore(&t->task_state_lock, flags); in mpi_ssp_event()
2387 status = le32_to_cpu(psataPayload->status); in mpi_sata_completion()
2388 param = le32_to_cpu(psataPayload->param); in mpi_sata_completion()
2389 tag = le32_to_cpu(psataPayload->tag); in mpi_sata_completion()
2391 ccb = &pm8001_ha->ccb_info[tag]; in mpi_sata_completion()
2392 t = ccb->task; in mpi_sata_completion()
2393 pm8001_dev = ccb->device; in mpi_sata_completion()
2396 if (t->dev && (t->dev->lldd_dev)) in mpi_sata_completion()
2397 pm8001_dev = t->dev->lldd_dev; in mpi_sata_completion()
2403 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG)) in mpi_sata_completion()
2404 && unlikely(!t || !t->lldd_task || !t->dev)) { in mpi_sata_completion()
2409 ts = &t->task_status; in mpi_sata_completion()
2413 "IO failed device_id %u status 0x%x tag %d\n", in mpi_sata_completion()
2414 pm8001_dev->device_id, status, tag); in mpi_sata_completion()
2420 if (!((t->dev->parent) && in mpi_sata_completion()
2421 (dev_is_expander(t->dev->parent->dev_type)))) { in mpi_sata_completion()
2422 for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++) in mpi_sata_completion()
2423 sata_addr_low[i] = pm8001_ha->sas_addr[j]; in mpi_sata_completion()
2424 for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++) in mpi_sata_completion()
2425 sata_addr_hi[i] = pm8001_ha->sas_addr[j]; in mpi_sata_completion()
2430 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff) in mpi_sata_completion()
2432 0xff0000) | in mpi_sata_completion()
2434 & 0xff00) | in mpi_sata_completion()
2436 0xff000000)); in mpi_sata_completion()
2438 & 0xff) | in mpi_sata_completion()
2440 & 0xff0000) | in mpi_sata_completion()
2442 & 0xff00) | in mpi_sata_completion()
2444 & 0xff000000)) + in mpi_sata_completion()
2445 pm8001_dev->attached_phy + in mpi_sata_completion()
2446 0x10); in mpi_sata_completion()
2455 SAS_ADDR(t->dev->sas_addr)); in mpi_sata_completion()
2461 if (param == 0) { in mpi_sata_completion()
2462 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2463 ts->stat = SAS_SAM_STAT_GOOD; in mpi_sata_completion()
2466 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) { in mpi_sata_completion()
2475 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2476 ts->stat = SAS_PROTO_RESPONSE; in mpi_sata_completion()
2477 ts->residual = param; in mpi_sata_completion()
2481 sata_resp = &psataPayload->sata_resp[0]; in mpi_sata_completion()
2482 resp = (struct ata_task_resp *)ts->buf; in mpi_sata_completion()
2483 if (t->ata_task.dma_xfer == 0 && in mpi_sata_completion()
2484 t->data_dir == DMA_FROM_DEVICE) { in mpi_sata_completion()
2488 } else if (t->ata_task.use_ncq && in mpi_sata_completion()
2489 t->data_dir != DMA_NONE) { in mpi_sata_completion()
2499 resp->frame_len = len; in mpi_sata_completion()
2500 memcpy(&resp->ending_fis[0], sata_resp, len); in mpi_sata_completion()
2501 ts->buf_valid_size = sizeof(*resp); in mpi_sata_completion()
2507 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2511 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2512 ts->stat = SAS_ABORTED_TASK; in mpi_sata_completion()
2514 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2520 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2521 ts->stat = SAS_DATA_UNDERRUN; in mpi_sata_completion()
2522 ts->residual = param; in mpi_sata_completion()
2524 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2528 ts->resp = SAS_TASK_UNDELIVERED; in mpi_sata_completion()
2529 ts->stat = SAS_PHY_DOWN; in mpi_sata_completion()
2531 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2535 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2536 ts->stat = SAS_INTERRUPTED; in mpi_sata_completion()
2538 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2542 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2543 ts->stat = SAS_OPEN_REJECT; in mpi_sata_completion()
2544 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_sata_completion()
2546 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2551 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2552 ts->stat = SAS_OPEN_REJECT; in mpi_sata_completion()
2553 ts->open_rej_reason = SAS_OREJ_EPROTO; in mpi_sata_completion()
2555 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2560 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2561 ts->stat = SAS_OPEN_REJECT; in mpi_sata_completion()
2562 ts->open_rej_reason = SAS_OREJ_UNKNOWN; in mpi_sata_completion()
2564 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2568 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2569 ts->stat = SAS_OPEN_REJECT; in mpi_sata_completion()
2570 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; in mpi_sata_completion()
2572 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2581 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2582 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_sata_completion()
2583 if (!t->uldd_task) { in mpi_sata_completion()
2587 ts->resp = SAS_TASK_UNDELIVERED; in mpi_sata_completion()
2588 ts->stat = SAS_QUEUE_FULL; in mpi_sata_completion()
2589 spin_unlock_irqrestore(&circularQ->oq_lock, in mpi_sata_completion()
2590 circularQ->lock_flags); in mpi_sata_completion()
2592 spin_lock_irqsave(&circularQ->oq_lock, in mpi_sata_completion()
2593 circularQ->lock_flags); in mpi_sata_completion()
2600 ts->resp = SAS_TASK_UNDELIVERED; in mpi_sata_completion()
2601 ts->stat = SAS_OPEN_REJECT; in mpi_sata_completion()
2602 ts->open_rej_reason = SAS_OREJ_BAD_DEST; in mpi_sata_completion()
2603 if (!t->uldd_task) { in mpi_sata_completion()
2607 ts->resp = SAS_TASK_UNDELIVERED; in mpi_sata_completion()
2608 ts->stat = SAS_QUEUE_FULL; in mpi_sata_completion()
2609 spin_unlock_irqrestore(&circularQ->oq_lock, in mpi_sata_completion()
2610 circularQ->lock_flags); in mpi_sata_completion()
2612 spin_lock_irqsave(&circularQ->oq_lock, in mpi_sata_completion()
2613 circularQ->lock_flags); in mpi_sata_completion()
2620 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2621 ts->stat = SAS_OPEN_REJECT; in mpi_sata_completion()
2622 ts->open_rej_reason = SAS_OREJ_CONN_RATE; in mpi_sata_completion()
2624 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2629 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2630 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_sata_completion()
2631 if (!t->uldd_task) { in mpi_sata_completion()
2635 ts->resp = SAS_TASK_UNDELIVERED; in mpi_sata_completion()
2636 ts->stat = SAS_QUEUE_FULL; in mpi_sata_completion()
2637 spin_unlock_irqrestore(&circularQ->oq_lock, in mpi_sata_completion()
2638 circularQ->lock_flags); in mpi_sata_completion()
2640 spin_lock_irqsave(&circularQ->oq_lock, in mpi_sata_completion()
2641 circularQ->lock_flags); in mpi_sata_completion()
2648 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2649 ts->stat = SAS_OPEN_REJECT; in mpi_sata_completion()
2650 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; in mpi_sata_completion()
2652 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2656 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2657 ts->stat = SAS_NAK_R_ERR; in mpi_sata_completion()
2659 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2663 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2664 ts->stat = SAS_NAK_R_ERR; in mpi_sata_completion()
2666 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2670 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2671 ts->stat = SAS_ABORTED_TASK; in mpi_sata_completion()
2673 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2677 ts->resp = SAS_TASK_UNDELIVERED; in mpi_sata_completion()
2678 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_sata_completion()
2680 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2684 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2685 ts->stat = SAS_DATA_UNDERRUN; in mpi_sata_completion()
2687 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2691 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2692 ts->stat = SAS_OPEN_TO; in mpi_sata_completion()
2694 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2698 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2699 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_sata_completion()
2701 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2705 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2706 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_sata_completion()
2707 if (!t->uldd_task) { in mpi_sata_completion()
2710 ts->resp = SAS_TASK_UNDELIVERED; in mpi_sata_completion()
2711 ts->stat = SAS_QUEUE_FULL; in mpi_sata_completion()
2712 spin_unlock_irqrestore(&circularQ->oq_lock, in mpi_sata_completion()
2713 circularQ->lock_flags); in mpi_sata_completion()
2715 spin_lock_irqsave(&circularQ->oq_lock, in mpi_sata_completion()
2716 circularQ->lock_flags); in mpi_sata_completion()
2722 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2723 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_sata_completion()
2725 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2729 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2730 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_sata_completion()
2731 if (!t->uldd_task) { in mpi_sata_completion()
2734 ts->resp = SAS_TASK_UNDELIVERED; in mpi_sata_completion()
2735 ts->stat = SAS_QUEUE_FULL; in mpi_sata_completion()
2736 spin_unlock_irqrestore(&circularQ->oq_lock, in mpi_sata_completion()
2737 circularQ->lock_flags); in mpi_sata_completion()
2739 spin_lock_irqsave(&circularQ->oq_lock, in mpi_sata_completion()
2740 circularQ->lock_flags); in mpi_sata_completion()
2747 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2748 ts->stat = SAS_OPEN_REJECT; in mpi_sata_completion()
2749 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_sata_completion()
2751 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2755 "Unknown status device_id %u status 0x%x tag %d\n", in mpi_sata_completion()
2756 pm8001_dev->device_id, status, tag); in mpi_sata_completion()
2758 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_completion()
2759 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_sata_completion()
2761 atomic_dec(&pm8001_dev->running_req); in mpi_sata_completion()
2764 spin_lock_irqsave(&t->task_state_lock, flags); in mpi_sata_completion()
2765 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; in mpi_sata_completion()
2766 t->task_state_flags |= SAS_TASK_STATE_DONE; in mpi_sata_completion()
2767 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { in mpi_sata_completion()
2768 spin_unlock_irqrestore(&t->task_state_lock, flags); in mpi_sata_completion()
2770 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n", in mpi_sata_completion()
2771 t, status, ts->resp, ts->stat); in mpi_sata_completion()
2773 if (t->slow_task) in mpi_sata_completion()
2774 complete(&t->slow_task->completion); in mpi_sata_completion()
2776 spin_unlock_irqrestore(&t->task_state_lock, flags); in mpi_sata_completion()
2777 spin_unlock_irqrestore(&circularQ->oq_lock, in mpi_sata_completion()
2778 circularQ->lock_flags); in mpi_sata_completion()
2780 spin_lock_irqsave(&circularQ->oq_lock, in mpi_sata_completion()
2781 circularQ->lock_flags); in mpi_sata_completion()
2795 u32 event = le32_to_cpu(psataPayload->event); in mpi_sata_event()
2796 u32 tag = le32_to_cpu(psataPayload->tag); in mpi_sata_event()
2797 u32 port_id = le32_to_cpu(psataPayload->port_id); in mpi_sata_event()
2798 u32 dev_id = le32_to_cpu(psataPayload->device_id); in mpi_sata_event()
2801 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event); in mpi_sata_event()
2813 ccb = &pm8001_ha->ccb_info[tag]; in mpi_sata_event()
2814 t = ccb->task; in mpi_sata_event()
2815 pm8001_dev = ccb->device; in mpi_sata_event()
2817 if (unlikely(!t || !t->lldd_task || !t->dev)) { in mpi_sata_event()
2822 ts = &t->task_status; in mpi_sata_event()
2823 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n", in mpi_sata_event()
2828 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2829 ts->stat = SAS_DATA_OVERRUN; in mpi_sata_event()
2830 ts->residual = 0; in mpi_sata_event()
2834 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2835 ts->stat = SAS_INTERRUPTED; in mpi_sata_event()
2839 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2840 ts->stat = SAS_OPEN_REJECT; in mpi_sata_event()
2841 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_sata_event()
2846 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2847 ts->stat = SAS_OPEN_REJECT; in mpi_sata_event()
2848 ts->open_rej_reason = SAS_OREJ_EPROTO; in mpi_sata_event()
2853 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2854 ts->stat = SAS_OPEN_REJECT; in mpi_sata_event()
2855 ts->open_rej_reason = SAS_OREJ_UNKNOWN; in mpi_sata_event()
2859 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2860 ts->stat = SAS_OPEN_REJECT; in mpi_sata_event()
2861 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; in mpi_sata_event()
2871 ts->resp = SAS_TASK_UNDELIVERED; in mpi_sata_event()
2872 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_sata_event()
2873 if (!t->uldd_task) { in mpi_sata_event()
2877 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2878 ts->stat = SAS_QUEUE_FULL; in mpi_sata_event()
2885 ts->resp = SAS_TASK_UNDELIVERED; in mpi_sata_event()
2886 ts->stat = SAS_OPEN_REJECT; in mpi_sata_event()
2887 ts->open_rej_reason = SAS_OREJ_BAD_DEST; in mpi_sata_event()
2892 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2893 ts->stat = SAS_OPEN_REJECT; in mpi_sata_event()
2894 ts->open_rej_reason = SAS_OREJ_CONN_RATE; in mpi_sata_event()
2899 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2900 ts->stat = SAS_OPEN_REJECT; in mpi_sata_event()
2901 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; in mpi_sata_event()
2905 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2906 ts->stat = SAS_NAK_R_ERR; in mpi_sata_event()
2910 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2911 ts->stat = SAS_NAK_R_ERR; in mpi_sata_event()
2915 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2916 ts->stat = SAS_DATA_UNDERRUN; in mpi_sata_event()
2920 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2921 ts->stat = SAS_OPEN_TO; in mpi_sata_event()
2925 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2926 ts->stat = SAS_OPEN_TO; in mpi_sata_event()
2930 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2931 ts->stat = SAS_OPEN_TO; in mpi_sata_event()
2936 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2937 ts->stat = SAS_OPEN_TO; in mpi_sata_event()
2941 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2942 ts->stat = SAS_OPEN_TO; in mpi_sata_event()
2947 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2948 ts->stat = SAS_OPEN_TO; in mpi_sata_event()
2955 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2956 ts->stat = SAS_OPEN_TO; in mpi_sata_event()
2962 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2963 ts->stat = SAS_OPEN_TO; in mpi_sata_event()
2968 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2969 ts->stat = SAS_OPEN_TO; in mpi_sata_event()
2972 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event); in mpi_sata_event()
2974 ts->resp = SAS_TASK_COMPLETE; in mpi_sata_event()
2975 ts->stat = SAS_OPEN_TO; in mpi_sata_event()
2995 status = le32_to_cpu(psmpPayload->status); in mpi_smp_completion()
2996 tag = le32_to_cpu(psmpPayload->tag); in mpi_smp_completion()
2998 ccb = &pm8001_ha->ccb_info[tag]; in mpi_smp_completion()
2999 param = le32_to_cpu(psmpPayload->param); in mpi_smp_completion()
3000 t = ccb->task; in mpi_smp_completion()
3001 ts = &t->task_status; in mpi_smp_completion()
3002 pm8001_dev = ccb->device; in mpi_smp_completion()
3004 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status); in mpi_smp_completion()
3005 if (unlikely(!t || !t->lldd_task || !t->dev)) in mpi_smp_completion()
3008 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status); in mpi_smp_completion()
3014 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3015 ts->stat = SAS_SAM_STAT_GOOD; in mpi_smp_completion()
3017 atomic_dec(&pm8001_dev->running_req); in mpi_smp_completion()
3018 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { in mpi_smp_completion()
3019 struct scatterlist *sg_resp = &t->smp_task.smp_resp; in mpi_smp_completion()
3027 payload = to + sg_resp->offset; in mpi_smp_completion()
3028 for (i = 0; i < param; i++) { in mpi_smp_completion()
3029 *(payload + i) = psmpPayload->_r_a[i]; in mpi_smp_completion()
3031 "SMP Byte%d DMA data 0x%x psmp 0x%x\n", in mpi_smp_completion()
3033 psmpPayload->_r_a[i]); in mpi_smp_completion()
3040 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3041 ts->stat = SAS_ABORTED_TASK; in mpi_smp_completion()
3043 atomic_dec(&pm8001_dev->running_req); in mpi_smp_completion()
3047 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3048 ts->stat = SAS_DATA_OVERRUN; in mpi_smp_completion()
3049 ts->residual = 0; in mpi_smp_completion()
3051 atomic_dec(&pm8001_dev->running_req); in mpi_smp_completion()
3055 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3056 ts->stat = SAS_PHY_DOWN; in mpi_smp_completion()
3060 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3061 ts->stat = SAS_SAM_STAT_BUSY; in mpi_smp_completion()
3065 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3066 ts->stat = SAS_SAM_STAT_BUSY; in mpi_smp_completion()
3070 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3071 ts->stat = SAS_SAM_STAT_BUSY; in mpi_smp_completion()
3076 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3077 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3078 ts->open_rej_reason = SAS_OREJ_UNKNOWN; in mpi_smp_completion()
3083 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3084 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3085 ts->open_rej_reason = SAS_OREJ_UNKNOWN; in mpi_smp_completion()
3089 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3090 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3091 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0; in mpi_smp_completion()
3100 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3101 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3102 ts->open_rej_reason = SAS_OREJ_UNKNOWN; in mpi_smp_completion()
3110 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3111 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3112 ts->open_rej_reason = SAS_OREJ_BAD_DEST; in mpi_smp_completion()
3117 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3118 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3119 ts->open_rej_reason = SAS_OREJ_CONN_RATE; in mpi_smp_completion()
3124 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3125 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3126 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; in mpi_smp_completion()
3130 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3131 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_smp_completion()
3135 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3136 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3137 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_smp_completion()
3141 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3142 ts->stat = SAS_QUEUE_FULL; in mpi_smp_completion()
3146 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3147 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3148 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_smp_completion()
3152 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3153 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_smp_completion()
3157 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3158 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3159 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_smp_completion()
3164 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3165 ts->stat = SAS_OPEN_REJECT; in mpi_smp_completion()
3166 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; in mpi_smp_completion()
3169 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status); in mpi_smp_completion()
3170 ts->resp = SAS_TASK_COMPLETE; in mpi_smp_completion()
3171 ts->stat = SAS_DEV_NO_RESPONSE; in mpi_smp_completion()
3175 spin_lock_irqsave(&t->task_state_lock, flags); in mpi_smp_completion()
3176 t->task_state_flags &= ~SAS_TASK_STATE_PENDING; in mpi_smp_completion()
3177 t->task_state_flags |= SAS_TASK_STATE_DONE; in mpi_smp_completion()
3178 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) { in mpi_smp_completion()
3179 spin_unlock_irqrestore(&t->task_state_lock, flags); in mpi_smp_completion()
3181 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n", in mpi_smp_completion()
3182 t, status, ts->resp, ts->stat); in mpi_smp_completion()
3185 spin_unlock_irqrestore(&t->task_state_lock, flags); in mpi_smp_completion()
3188 t->task_done(t); in mpi_smp_completion()
3193 * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW.
3199 * @param0: parameter 0.
3208 memset((u8 *)&payload, 0, sizeof(payload)); in pm80xx_hw_event_ack_req()
3210 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) | in pm80xx_hw_event_ack_req()
3211 ((phyId & 0xFF) << 24) | (port_id & 0xFF)); in pm80xx_hw_event_ack_req()
3216 sizeof(payload), 0); in pm80xx_hw_event_ack_req()
3226 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); in hw_event_port_recover()
3227 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16); in hw_event_port_recover()
3229 le32_to_cpu(pPayload->lr_status_evt_portid); in hw_event_port_recover()
3230 u8 deviceType = pPayload->sas_identify.dev_type; in hw_event_port_recover()
3231 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); in hw_event_port_recover()
3232 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; in hw_event_port_recover()
3233 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); in hw_event_port_recover()
3234 struct pm8001_port *port = &pm8001_ha->port[port_id]; in hw_event_port_recover()
3241 port->wide_port_phymap |= (1U << phy_id); in hw_event_port_recover()
3243 phy->sas_phy.oob_mode = SAS_OOB_MODE; in hw_event_port_recover()
3244 phy->phy_state = PHY_STATE_LINK_UP_SPCV; in hw_event_port_recover()
3245 phy->phy_attached = 1; in hw_event_port_recover()
3249 * hw_event_sas_phy_up - FW tells me a SAS phy up event.
3259 le32_to_cpu(pPayload->lr_status_evt_portid); in hw_event_sas_phy_up()
3260 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); in hw_event_sas_phy_up()
3263 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); in hw_event_sas_phy_up()
3264 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); in hw_event_sas_phy_up()
3266 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); in hw_event_sas_phy_up()
3267 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); in hw_event_sas_phy_up()
3269 struct pm8001_port *port = &pm8001_ha->port[port_id]; in hw_event_sas_phy_up()
3270 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; in hw_event_sas_phy_up()
3272 u8 deviceType = pPayload->sas_identify.dev_type; in hw_event_sas_phy_up()
3273 phy->port = port; in hw_event_sas_phy_up()
3274 port->port_id = port_id; in hw_event_sas_phy_up()
3275 port->port_state = portstate; in hw_event_sas_phy_up()
3276 port->wide_port_phymap |= (1U << phy_id); in hw_event_sas_phy_up()
3277 phy->phy_state = PHY_STATE_LINK_UP_SPCV; in hw_event_sas_phy_up()
3290 port->port_attached = 1; in hw_event_sas_phy_up()
3295 port->port_attached = 1; in hw_event_sas_phy_up()
3300 port->port_attached = 1; in hw_event_sas_phy_up()
3308 phy->phy_type |= PORT_TYPE_SAS; in hw_event_sas_phy_up()
3309 phy->identify.device_type = deviceType; in hw_event_sas_phy_up()
3310 phy->phy_attached = 1; in hw_event_sas_phy_up()
3311 if (phy->identify.device_type == SAS_END_DEVICE) in hw_event_sas_phy_up()
3312 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP; in hw_event_sas_phy_up()
3313 else if (phy->identify.device_type != SAS_PHY_UNUSED) in hw_event_sas_phy_up()
3314 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP; in hw_event_sas_phy_up()
3315 phy->sas_phy.oob_mode = SAS_OOB_MODE; in hw_event_sas_phy_up()
3316 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); in hw_event_sas_phy_up()
3317 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); in hw_event_sas_phy_up()
3318 memcpy(phy->frame_rcvd, &pPayload->sas_identify, in hw_event_sas_phy_up()
3319 sizeof(struct sas_identify_frame)-4); in hw_event_sas_phy_up()
3320 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4; in hw_event_sas_phy_up()
3321 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); in hw_event_sas_phy_up()
3322 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); in hw_event_sas_phy_up()
3323 if (pm8001_ha->flags == PM8001F_RUN_TIME) in hw_event_sas_phy_up()
3329 * hw_event_sata_phy_up - FW tells me a SATA phy up event.
3338 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); in hw_event_sata_phy_up()
3340 le32_to_cpu(pPayload->lr_status_evt_portid); in hw_event_sata_phy_up()
3342 (u8)((lr_status_evt_portid & 0xF0000000) >> 28); in hw_event_sata_phy_up()
3343 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); in hw_event_sata_phy_up()
3345 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); in hw_event_sata_phy_up()
3347 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); in hw_event_sata_phy_up()
3349 struct pm8001_port *port = &pm8001_ha->port[port_id]; in hw_event_sata_phy_up()
3350 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; in hw_event_sata_phy_up()
3353 "port id %d, phy id %d link_rate %d portstate 0x%x\n", in hw_event_sata_phy_up()
3356 phy->port = port; in hw_event_sata_phy_up()
3357 port->port_id = port_id; in hw_event_sata_phy_up()
3358 port->port_state = portstate; in hw_event_sata_phy_up()
3359 phy->phy_state = PHY_STATE_LINK_UP_SPCV; in hw_event_sata_phy_up()
3360 port->port_attached = 1; in hw_event_sata_phy_up()
3362 phy->phy_type |= PORT_TYPE_SATA; in hw_event_sata_phy_up()
3363 phy->phy_attached = 1; in hw_event_sata_phy_up()
3364 phy->sas_phy.oob_mode = SATA_OOB_MODE; in hw_event_sata_phy_up()
3365 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC); in hw_event_sata_phy_up()
3366 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags); in hw_event_sata_phy_up()
3367 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4), in hw_event_sata_phy_up()
3369 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); in hw_event_sata_phy_up()
3370 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; in hw_event_sata_phy_up()
3371 phy->identify.device_type = SAS_SATA_DEV; in hw_event_sata_phy_up()
3372 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr); in hw_event_sata_phy_up()
3373 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags); in hw_event_sata_phy_up()
3378 * hw_event_phy_down - we should notify the libsas the phy is down.
3389 le32_to_cpu(pPayload->lr_status_evt_portid); in hw_event_phy_down()
3390 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); in hw_event_phy_down()
3391 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); in hw_event_phy_down()
3393 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); in hw_event_phy_down()
3394 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F); in hw_event_phy_down()
3396 struct pm8001_port *port = &pm8001_ha->port[port_id]; in hw_event_phy_down()
3397 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; in hw_event_phy_down()
3398 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA); in hw_event_phy_down()
3399 port->port_state = portstate; in hw_event_phy_down()
3400 phy->identify.device_type = 0; in hw_event_phy_down()
3401 phy->phy_attached = 0; in hw_event_phy_down()
3411 phy->phy_type = 0; in hw_event_phy_down()
3412 port->port_attached = 0; in hw_event_phy_down()
3413 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, in hw_event_phy_down()
3414 port_id, phy_id, 0, 0); in hw_event_phy_down()
3416 sas_phy_disconnected(&phy->sas_phy); in hw_event_phy_down()
3425 port->port_attached = 0; in hw_event_phy_down()
3432 port->port_attached = 0; in hw_event_phy_down()
3433 phy->phy_type = 0; in hw_event_phy_down()
3434 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, in hw_event_phy_down()
3435 port_id, phy_id, 0, 0); in hw_event_phy_down()
3437 sas_phy_disconnected(&phy->sas_phy); in hw_event_phy_down()
3440 port->port_attached = 0; in hw_event_phy_down()
3442 " Phy Down and(default) = 0x%x\n", in hw_event_phy_down()
3448 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL, in hw_event_phy_down()
3457 le32_to_cpu(pPayload->status); in mpi_phy_start_resp()
3459 le32_to_cpu(pPayload->phyid) & 0xFF; in mpi_phy_start_resp()
3460 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; in mpi_phy_start_resp()
3463 "phy start resp status:0x%x, phyid:0x%x\n", in mpi_phy_start_resp()
3465 if (status == 0) in mpi_phy_start_resp()
3466 phy->phy_state = PHY_LINK_DOWN; in mpi_phy_start_resp()
3468 if (pm8001_ha->flags == PM8001F_RUN_TIME && in mpi_phy_start_resp()
3469 phy->enable_completion != NULL) { in mpi_phy_start_resp()
3470 complete(phy->enable_completion); in mpi_phy_start_resp()
3471 phy->enable_completion = NULL; in mpi_phy_start_resp()
3473 return 0; in mpi_phy_start_resp()
3478 * mpi_thermal_hw_event - a thermal hw event has come.
3487 u32 thermal_event = le32_to_cpu(pPayload->thermal_event); in mpi_thermal_hw_event()
3488 u32 rht_lht = le32_to_cpu(pPayload->rht_lht); in mpi_thermal_hw_event()
3490 if (thermal_event & 0x40) { in mpi_thermal_hw_event()
3495 ((rht_lht & 0xFF00) >> 8)); in mpi_thermal_hw_event()
3497 if (thermal_event & 0x10) { in mpi_thermal_hw_event()
3502 ((rht_lht & 0xFF000000) >> 24)); in mpi_thermal_hw_event()
3504 return 0; in mpi_thermal_hw_event()
3508 * mpi_hw_event - The hw event has come.
3518 le32_to_cpu(pPayload->lr_status_evt_portid); in mpi_hw_event()
3519 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate); in mpi_hw_event()
3520 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF); in mpi_hw_event()
3522 (u8)((phyid_npip_portstate & 0xFF0000) >> 16); in mpi_hw_event()
3524 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8); in mpi_hw_event()
3526 (u8)((lr_status_evt_portid & 0x0F000000) >> 24); in mpi_hw_event()
3527 struct sas_ha_struct *sas_ha = pm8001_ha->sas; in mpi_hw_event()
3528 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id]; in mpi_hw_event()
3529 struct pm8001_port *port = &pm8001_ha->port[port_id]; in mpi_hw_event()
3530 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id]; in mpi_hw_event()
3532 "portid:%d phyid:%d event:0x%x status:0x%x\n", in mpi_hw_event()
3547 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD, in mpi_hw_event()
3553 if (pm8001_ha->reset_in_progress) { in mpi_hw_event()
3555 return 0; in mpi_hw_event()
3557 phy->phy_attached = 0; in mpi_hw_event()
3558 phy->phy_state = PHY_LINK_DISABLE; in mpi_hw_event()
3563 phy->phy_attached = 0; in mpi_hw_event()
3571 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE, in mpi_hw_event()
3572 port_id, phy_id, 1, 0); in mpi_hw_event()
3573 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); in mpi_hw_event()
3574 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE; in mpi_hw_event()
3575 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); in mpi_hw_event()
3581 sas_phy_disconnected(&phy->sas_phy); in mpi_hw_event()
3582 phy->phy_attached = 0; in mpi_hw_event()
3583 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC); in mpi_hw_event()
3587 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); in mpi_hw_event()
3588 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP; in mpi_hw_event()
3589 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); in mpi_hw_event()
3596 pm80xx_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3597 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0); in mpi_hw_event()
3602 pm80xx_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3604 port_id, phy_id, 0, 0); in mpi_hw_event()
3609 pm80xx_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3611 port_id, phy_id, 0, 0); in mpi_hw_event()
3616 pm80xx_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3618 port_id, phy_id, 0, 0); in mpi_hw_event()
3625 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags); in mpi_hw_event()
3626 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES; in mpi_hw_event()
3627 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags); in mpi_hw_event()
3633 pm80xx_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3635 port_id, phy_id, 0, 0); in mpi_hw_event()
3644 phy->phy_attached = 0; in mpi_hw_event()
3651 pm80xx_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3653 port_id, phy_id, 0, 0); in mpi_hw_event()
3655 phy->phy_attached = 0; in mpi_hw_event()
3661 if (!pm8001_ha->phy[phy_id].reset_completion) { in mpi_hw_event()
3662 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN, in mpi_hw_event()
3663 port_id, phy_id, 0, 0); in mpi_hw_event()
3666 phy->phy_attached = 0; in mpi_hw_event()
3669 if (pm8001_ha->phy[phy_id].reset_completion) { in mpi_hw_event()
3670 pm8001_ha->phy[phy_id].port_reset_status = in mpi_hw_event()
3672 complete(pm8001_ha->phy[phy_id].reset_completion); in mpi_hw_event()
3673 pm8001_ha->phy[phy_id].reset_completion = NULL; in mpi_hw_event()
3679 pm80xx_hw_event_ack_req(pm8001_ha, 0, in mpi_hw_event()
3681 port_id, phy_id, 0, 0); in mpi_hw_event()
3682 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { in mpi_hw_event()
3683 if (port->wide_port_phymap & (1 << i)) { in mpi_hw_event()
3684 phy = &pm8001_ha->phy[i]; in mpi_hw_event()
3685 sas_notify_phy_event(&phy->sas_phy, in mpi_hw_event()
3687 port->wide_port_phymap &= ~(1 << i); in mpi_hw_event()
3697 if (pm8001_ha->phy[phy_id].reset_completion) { in mpi_hw_event()
3698 pm8001_ha->phy[phy_id].port_reset_status = in mpi_hw_event()
3700 complete(pm8001_ha->phy[phy_id].reset_completion); in mpi_hw_event()
3701 pm8001_ha->phy[phy_id].reset_completion = NULL; in mpi_hw_event()
3708 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n", in mpi_hw_event()
3712 return 0; in mpi_hw_event()
3716 * mpi_phy_stop_resp - SPCv specific
3725 le32_to_cpu(pPayload->status); in mpi_phy_stop_resp()
3727 le32_to_cpu(pPayload->phyid) & 0xFF; in mpi_phy_stop_resp()
3728 struct pm8001_phy *phy = &pm8001_ha->phy[phyid]; in mpi_phy_stop_resp()
3729 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n", in mpi_phy_stop_resp()
3733 phy->phy_state = PHY_LINK_DISABLE; in mpi_phy_stop_resp()
3734 phy->sas_phy.phy->negotiated_linkrate = SAS_PHY_DISABLED; in mpi_phy_stop_resp()
3735 phy->sas_phy.linkrate = SAS_PHY_DISABLED; in mpi_phy_stop_resp()
3738 return 0; in mpi_phy_stop_resp()
3742 * mpi_set_controller_config_resp - SPCv specific
3751 u32 status = le32_to_cpu(pPayload->status); in mpi_set_controller_config_resp()
3752 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd); in mpi_set_controller_config_resp()
3755 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n", in mpi_set_controller_config_resp()
3758 return 0; in mpi_set_controller_config_resp()
3762 * mpi_get_controller_config_resp - SPCv specific
3771 return 0; in mpi_get_controller_config_resp()
3775 * mpi_get_phy_profile_resp - SPCv specific
3784 return 0; in mpi_get_phy_profile_resp()
3788 * mpi_flash_op_ext_resp - SPCv specific
3796 return 0; in mpi_flash_op_ext_resp()
3800 * mpi_set_phy_profile_resp - SPCv specific
3809 int rc = 0; in mpi_set_phy_profile_resp()
3812 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid); in mpi_set_phy_profile_resp()
3813 u32 status = le32_to_cpu(pPayload->status); in mpi_set_phy_profile_resp()
3815 tag = le32_to_cpu(pPayload->tag); in mpi_set_phy_profile_resp()
3816 page_code = (u8)((ppc_phyid & 0xFF00) >> 8); in mpi_set_phy_profile_resp()
3820 "PhyProfile command failed with status 0x%08X\n", in mpi_set_phy_profile_resp()
3822 rc = -1; in mpi_set_phy_profile_resp()
3825 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n", in mpi_set_phy_profile_resp()
3827 rc = -1; in mpi_set_phy_profile_resp()
3835 * mpi_kek_management_resp - SPCv specific
3844 u32 status = le32_to_cpu(pPayload->status); in mpi_kek_management_resp()
3845 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop); in mpi_kek_management_resp()
3846 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr); in mpi_kek_management_resp()
3849 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n", in mpi_kek_management_resp()
3852 return 0; in mpi_kek_management_resp()
3856 * mpi_dek_management_resp - SPCv specific
3865 return 0; in mpi_dek_management_resp()
3869 * ssp_coalesced_comp_resp - SPCv specific
3878 return 0; in ssp_coalesced_comp_resp()
3882 * process_one_iomb - process one outbound Queue memory block
3891 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF); in process_one_iomb()
4064 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc); in process_one_iomb()
4071 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n", in print_scratchpad_registers()
4072 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)); in print_scratchpad_registers()
4073 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n", in print_scratchpad_registers()
4074 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)); in print_scratchpad_registers()
4075 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n", in print_scratchpad_registers()
4076 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)); in print_scratchpad_registers()
4077 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n", in print_scratchpad_registers()
4078 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)); in print_scratchpad_registers()
4079 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n", in print_scratchpad_registers()
4080 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)); in print_scratchpad_registers()
4081 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n", in print_scratchpad_registers()
4082 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)); in print_scratchpad_registers()
4083 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n", in print_scratchpad_registers()
4084 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)); in print_scratchpad_registers()
4085 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n", in print_scratchpad_registers()
4086 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)); in print_scratchpad_registers()
4087 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n", in print_scratchpad_registers()
4088 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)); in print_scratchpad_registers()
4089 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n", in print_scratchpad_registers()
4090 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)); in print_scratchpad_registers()
4091 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n", in print_scratchpad_registers()
4092 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_0)); in print_scratchpad_registers()
4093 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n", in print_scratchpad_registers()
4094 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_1)); in print_scratchpad_registers()
4107 * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl. in process_oq()
4110 if (vec == (pm8001_ha->max_q_num - 1)) { in process_oq()
4113 if (pm8001_ha->chip_id == chip_8008 || in process_oq()
4114 pm8001_ha->chip_id == chip_8009) in process_oq()
4119 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1); in process_oq()
4121 pm8001_ha->controller_fatal_error = true; in process_oq()
4123 "Firmware Fatal error! Regval:0x%x\n", in process_oq()
4129 /*read scratchpad rsvd 0 register*/ in process_oq()
4130 regval = pm8001_cr32(pm8001_ha, 0, in process_oq()
4137 pm8001_cw32(pm8001_ha, 0, in process_oq()
4139 0x00000000); in process_oq()
4146 circularQ = &pm8001_ha->outbnd_q_tbl[vec]; in process_oq()
4147 spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags); in process_oq()
4149 /* spurious interrupt during setup if kexec-ing and in process_oq()
4150 * driver doing a doorbell access w/ the pre-kexec oq in process_oq()
4153 if (!circularQ->pi_virt) in process_oq()
4159 (void *)(pMsg1 - 4)); in process_oq()
4166 circularQ->producer_index = in process_oq()
4167 cpu_to_le32(pm8001_read_32(circularQ->pi_virt)); in process_oq()
4168 if (le32_to_cpu(circularQ->producer_index) == in process_oq()
4169 circularQ->consumer_idx) in process_oq()
4174 spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags); in process_oq()
4189 psmp_cmd->tag = hTag; in build_smp_cmd()
4190 psmp_cmd->device_id = cpu_to_le32(deviceID); in build_smp_cmd()
4192 length = length - 4; /* subtract crc */ in build_smp_cmd()
4193 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16); in build_smp_cmd()
4195 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1)); in build_smp_cmd()
4200 * pm80xx_chip_smp_req - send an SMP task to FW
4208 struct sas_task *task = ccb->task; in pm80xx_chip_smp_req()
4209 struct domain_device *dev = task->dev; in pm80xx_chip_smp_req()
4210 struct pm8001_device *pm8001_dev = dev->lldd_dev; in pm80xx_chip_smp_req()
4219 memset(&smp_cmd, 0, sizeof(smp_cmd)); in pm80xx_chip_smp_req()
4221 * DMA-map SMP request, response buffers in pm80xx_chip_smp_req()
4223 sg_req = &task->smp_task.smp_req; in pm80xx_chip_smp_req()
4224 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE); in pm80xx_chip_smp_req()
4226 return -ENOMEM; in pm80xx_chip_smp_req()
4229 sg_resp = &task->smp_task.smp_resp; in pm80xx_chip_smp_req()
4230 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE); in pm80xx_chip_smp_req()
4232 rc = -ENOMEM; in pm80xx_chip_smp_req()
4237 if ((req_len & 0x3) || (resp_len & 0x3)) { in pm80xx_chip_smp_req()
4238 rc = -EINVAL; in pm80xx_chip_smp_req()
4243 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag); in pm80xx_chip_smp_req()
4245 length = sg_req->length; in pm80xx_chip_smp_req()
4246 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length); in pm80xx_chip_smp_req()
4247 if (!(length - 8)) in pm80xx_chip_smp_req()
4248 pm8001_ha->smp_exp_mode = SMP_DIRECT; in pm80xx_chip_smp_req()
4250 pm8001_ha->smp_exp_mode = SMP_INDIRECT; in pm80xx_chip_smp_req()
4253 smp_req = &task->smp_task.smp_req; in pm80xx_chip_smp_req()
4255 payload = to + smp_req->offset; in pm80xx_chip_smp_req()
4258 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) { in pm80xx_chip_smp_req()
4262 for (i = 0; i < 4; i++) in pm80xx_chip_smp_req()
4267 (&task->smp_task.smp_req) + 4); in pm80xx_chip_smp_req()
4270 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8); in pm80xx_chip_smp_req()
4273 (&task->smp_task.smp_resp)); in pm80xx_chip_smp_req()
4276 (&task->smp_task.smp_resp)-4); in pm80xx_chip_smp_req()
4280 (&task->smp_task.smp_req)); in pm80xx_chip_smp_req()
4282 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4); in pm80xx_chip_smp_req()
4285 (&task->smp_task.smp_resp)); in pm80xx_chip_smp_req()
4288 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4); in pm80xx_chip_smp_req()
4290 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) { in pm80xx_chip_smp_req()
4292 for (i = 0; i < length; i++) in pm80xx_chip_smp_req()
4308 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, in pm80xx_chip_smp_req()
4309 &smp_cmd, pm8001_ha->smp_exp_mode, length); in pm80xx_chip_smp_req()
4310 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &smp_cmd, in pm80xx_chip_smp_req()
4311 sizeof(smp_cmd), 0); in pm80xx_chip_smp_req()
4314 return 0; in pm80xx_chip_smp_req()
4317 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1, in pm80xx_chip_smp_req()
4320 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1, in pm80xx_chip_smp_req()
4327 u8 cmd = task->ssp_task.cmd->cmnd[0]; in check_enc_sas_cmd()
4332 return 0; in check_enc_sas_cmd()
4337 int ret = 0; in check_enc_sat_cmd()
4338 switch (task->ata_task.fis.command) { in check_enc_sat_cmd()
4352 ret = 0; in check_enc_sat_cmd()
4363 if (task->uldd_task) { in pm80xx_chip_get_q_index()
4366 if (dev_is_sata(task->dev)) { in pm80xx_chip_get_q_index()
4367 qc = task->uldd_task; in pm80xx_chip_get_q_index()
4368 scmd = qc->scsicmd; in pm80xx_chip_get_q_index()
4370 scmd = task->uldd_task; in pm80xx_chip_get_q_index()
4375 return 0; in pm80xx_chip_get_q_index()
4382 * pm80xx_chip_ssp_io_req - send an SSP task to FW
4389 struct sas_task *task = ccb->task; in pm80xx_chip_ssp_io_req()
4390 struct domain_device *dev = task->dev; in pm80xx_chip_ssp_io_req()
4391 struct pm8001_device *pm8001_dev = dev->lldd_dev; in pm80xx_chip_ssp_io_req()
4393 u32 tag = ccb->ccb_tag; in pm80xx_chip_ssp_io_req()
4399 memset(&ssp_cmd, 0, sizeof(ssp_cmd)); in pm80xx_chip_ssp_io_req()
4400 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8); in pm80xx_chip_ssp_io_req()
4402 /* data address domain added for spcv; set to 0 by host, in pm80xx_chip_ssp_io_req()
4404 * 0 for SAS 1.1 and SAS 2.0 compatible TLR in pm80xx_chip_ssp_io_req()
4407 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0); in pm80xx_chip_ssp_io_req()
4408 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len); in pm80xx_chip_ssp_io_req()
4409 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id); in pm80xx_chip_ssp_io_req()
4411 if (task->ssp_task.enable_first_burst) in pm80xx_chip_ssp_io_req()
4412 ssp_cmd.ssp_iu.efb_prio_attr = 0x80; in pm80xx_chip_ssp_io_req()
4413 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3); in pm80xx_chip_ssp_io_req()
4414 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7); in pm80xx_chip_ssp_io_req()
4415 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd, in pm80xx_chip_ssp_io_req()
4416 task->ssp_task.cmd->cmd_len); in pm80xx_chip_ssp_io_req()
4420 if (pm8001_ha->chip->encrypt && in pm80xx_chip_ssp_io_req()
4421 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) { in pm80xx_chip_ssp_io_req()
4423 "Encryption enabled.Sending Encrypt SAS command 0x%x\n", in pm80xx_chip_ssp_io_req()
4424 task->ssp_task.cmd->cmnd[0]); in pm80xx_chip_ssp_io_req()
4426 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/ in pm80xx_chip_ssp_io_req()
4428 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0); in pm80xx_chip_ssp_io_req()
4431 if (task->num_scatter > 1) { in pm80xx_chip_ssp_io_req()
4432 pm8001_chip_make_sg(task->scatter, in pm80xx_chip_ssp_io_req()
4433 ccb->n_elem, ccb->buf_prd); in pm80xx_chip_ssp_io_req()
4434 phys_addr = ccb->ccb_dma_handle; in pm80xx_chip_ssp_io_req()
4440 } else if (task->num_scatter == 1) { in pm80xx_chip_ssp_io_req()
4441 u64 dma_addr = sg_dma_address(task->scatter); in pm80xx_chip_ssp_io_req()
4447 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); in pm80xx_chip_ssp_io_req()
4448 ssp_cmd.enc_esgl = 0; in pm80xx_chip_ssp_io_req()
4451 end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1; in pm80xx_chip_ssp_io_req()
4457 …"The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x h… in pm80xx_chip_ssp_io_req()
4461 pm8001_chip_make_sg(task->scatter, 1, in pm80xx_chip_ssp_io_req()
4462 ccb->buf_prd); in pm80xx_chip_ssp_io_req()
4463 phys_addr = ccb->ccb_dma_handle; in pm80xx_chip_ssp_io_req()
4470 } else if (task->num_scatter == 0) { in pm80xx_chip_ssp_io_req()
4471 ssp_cmd.enc_addr_low = 0; in pm80xx_chip_ssp_io_req()
4472 ssp_cmd.enc_addr_high = 0; in pm80xx_chip_ssp_io_req()
4473 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len); in pm80xx_chip_ssp_io_req()
4474 ssp_cmd.enc_esgl = 0; in pm80xx_chip_ssp_io_req()
4477 /* XTS mode. All other fields are 0 */ in pm80xx_chip_ssp_io_req()
4478 ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4); in pm80xx_chip_ssp_io_req()
4481 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) | in pm80xx_chip_ssp_io_req()
4482 (task->ssp_task.cmd->cmnd[3] << 16) | in pm80xx_chip_ssp_io_req()
4483 (task->ssp_task.cmd->cmnd[4] << 8) | in pm80xx_chip_ssp_io_req()
4484 (task->ssp_task.cmd->cmnd[5])); in pm80xx_chip_ssp_io_req()
4487 "Sending Normal SAS command 0x%x inb q %x\n", in pm80xx_chip_ssp_io_req()
4488 task->ssp_task.cmd->cmnd[0], q_index); in pm80xx_chip_ssp_io_req()
4490 if (task->num_scatter > 1) { in pm80xx_chip_ssp_io_req()
4491 pm8001_chip_make_sg(task->scatter, ccb->n_elem, in pm80xx_chip_ssp_io_req()
4492 ccb->buf_prd); in pm80xx_chip_ssp_io_req()
4493 phys_addr = ccb->ccb_dma_handle; in pm80xx_chip_ssp_io_req()
4499 } else if (task->num_scatter == 1) { in pm80xx_chip_ssp_io_req()
4500 u64 dma_addr = sg_dma_address(task->scatter); in pm80xx_chip_ssp_io_req()
4505 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); in pm80xx_chip_ssp_io_req()
4506 ssp_cmd.esgl = 0; in pm80xx_chip_ssp_io_req()
4509 end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1; in pm80xx_chip_ssp_io_req()
4514 …"The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x h… in pm80xx_chip_ssp_io_req()
4518 pm8001_chip_make_sg(task->scatter, 1, in pm80xx_chip_ssp_io_req()
4519 ccb->buf_prd); in pm80xx_chip_ssp_io_req()
4520 phys_addr = ccb->ccb_dma_handle; in pm80xx_chip_ssp_io_req()
4527 } else if (task->num_scatter == 0) { in pm80xx_chip_ssp_io_req()
4528 ssp_cmd.addr_low = 0; in pm80xx_chip_ssp_io_req()
4529 ssp_cmd.addr_high = 0; in pm80xx_chip_ssp_io_req()
4530 ssp_cmd.len = cpu_to_le32(task->total_xfer_len); in pm80xx_chip_ssp_io_req()
4531 ssp_cmd.esgl = 0; in pm80xx_chip_ssp_io_req()
4542 struct sas_task *task = ccb->task; in pm80xx_chip_sata_req()
4543 struct domain_device *dev = task->dev; in pm80xx_chip_sata_req()
4544 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev; in pm80xx_chip_sata_req()
4545 struct ata_queued_cmd *qc = task->uldd_task; in pm80xx_chip_sata_req()
4546 u32 tag = ccb->ccb_tag, q_index; in pm80xx_chip_sata_req()
4548 u32 hdr_tag, ncg_tag = 0; in pm80xx_chip_sata_req()
4551 u32 ATAP = 0x0; in pm80xx_chip_sata_req()
4555 memset(&sata_cmd, 0, sizeof(sata_cmd)); in pm80xx_chip_sata_req()
4559 if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) { in pm80xx_chip_sata_req()
4560 ATAP = 0x04; /* no data*/ in pm80xx_chip_sata_req()
4562 } else if (likely(!task->ata_task.device_control_reg_update)) { in pm80xx_chip_sata_req()
4563 if (task->ata_task.use_ncq && in pm80xx_chip_sata_req()
4564 dev->sata_dev.class != ATA_DEV_ATAPI) { in pm80xx_chip_sata_req()
4565 ATAP = 0x07; /* FPDMA */ in pm80xx_chip_sata_req()
4567 } else if (task->ata_task.dma_xfer) { in pm80xx_chip_sata_req()
4568 ATAP = 0x06; /* DMA */ in pm80xx_chip_sata_req()
4571 ATAP = 0x05; /* PIO*/ in pm80xx_chip_sata_req()
4575 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) { in pm80xx_chip_sata_req()
4576 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); in pm80xx_chip_sata_req()
4579 dir = data_dir_flags[task->data_dir] << 8; in pm80xx_chip_sata_req()
4581 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id); in pm80xx_chip_sata_req()
4582 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len); in pm80xx_chip_sata_req()
4584 sata_cmd.sata_fis = task->ata_task.fis; in pm80xx_chip_sata_req()
4585 if (likely(!task->ata_task.device_control_reg_update)) in pm80xx_chip_sata_req()
4586 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */ in pm80xx_chip_sata_req()
4587 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */ in pm80xx_chip_sata_req()
4590 if (pm8001_ha->chip->encrypt && in pm80xx_chip_sata_req()
4591 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) { in pm80xx_chip_sata_req()
4593 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n", in pm80xx_chip_sata_req()
4599 cpu_to_le32(((ncg_tag & 0xff)<<16)| in pm80xx_chip_sata_req()
4600 ((ATAP & 0x3f) << 10) | 0x20 | dir); in pm80xx_chip_sata_req()
4601 /* dad (bit 0-1) is 0 */ in pm80xx_chip_sata_req()
4603 if (task->num_scatter > 1) { in pm80xx_chip_sata_req()
4604 pm8001_chip_make_sg(task->scatter, in pm80xx_chip_sata_req()
4605 ccb->n_elem, ccb->buf_prd); in pm80xx_chip_sata_req()
4606 phys_addr = ccb->ccb_dma_handle; in pm80xx_chip_sata_req()
4612 } else if (task->num_scatter == 1) { in pm80xx_chip_sata_req()
4613 u64 dma_addr = sg_dma_address(task->scatter); in pm80xx_chip_sata_req()
4619 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); in pm80xx_chip_sata_req()
4620 sata_cmd.enc_esgl = 0; in pm80xx_chip_sata_req()
4623 end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1; in pm80xx_chip_sata_req()
4628 …"The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x h… in pm80xx_chip_sata_req()
4632 pm8001_chip_make_sg(task->scatter, 1, in pm80xx_chip_sata_req()
4633 ccb->buf_prd); in pm80xx_chip_sata_req()
4634 phys_addr = ccb->ccb_dma_handle; in pm80xx_chip_sata_req()
4642 } else if (task->num_scatter == 0) { in pm80xx_chip_sata_req()
4643 sata_cmd.enc_addr_low = 0; in pm80xx_chip_sata_req()
4644 sata_cmd.enc_addr_high = 0; in pm80xx_chip_sata_req()
4645 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len); in pm80xx_chip_sata_req()
4646 sata_cmd.enc_esgl = 0; in pm80xx_chip_sata_req()
4648 /* XTS mode. All other fields are 0 */ in pm80xx_chip_sata_req()
4649 sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4); in pm80xx_chip_sata_req()
4662 "Sending Normal SATA command 0x%x inb %x\n", in pm80xx_chip_sata_req()
4664 /* dad (bit 0-1) is 0 */ in pm80xx_chip_sata_req()
4666 cpu_to_le32(((ncg_tag & 0xff)<<16) | in pm80xx_chip_sata_req()
4667 ((ATAP & 0x3f) << 10) | dir); in pm80xx_chip_sata_req()
4670 if (task->num_scatter > 1) { in pm80xx_chip_sata_req()
4671 pm8001_chip_make_sg(task->scatter, in pm80xx_chip_sata_req()
4672 ccb->n_elem, ccb->buf_prd); in pm80xx_chip_sata_req()
4673 phys_addr = ccb->ccb_dma_handle; in pm80xx_chip_sata_req()
4677 } else if (task->num_scatter == 1) { in pm80xx_chip_sata_req()
4678 u64 dma_addr = sg_dma_address(task->scatter); in pm80xx_chip_sata_req()
4682 sata_cmd.len = cpu_to_le32(task->total_xfer_len); in pm80xx_chip_sata_req()
4683 sata_cmd.esgl = 0; in pm80xx_chip_sata_req()
4686 end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1; in pm80xx_chip_sata_req()
4691 …"The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x ha… in pm80xx_chip_sata_req()
4695 pm8001_chip_make_sg(task->scatter, 1, in pm80xx_chip_sata_req()
4696 ccb->buf_prd); in pm80xx_chip_sata_req()
4697 phys_addr = ccb->ccb_dma_handle; in pm80xx_chip_sata_req()
4702 } else if (task->num_scatter == 0) { in pm80xx_chip_sata_req()
4703 sata_cmd.addr_low = 0; in pm80xx_chip_sata_req()
4704 sata_cmd.addr_high = 0; in pm80xx_chip_sata_req()
4705 sata_cmd.len = cpu_to_le32(task->total_xfer_len); in pm80xx_chip_sata_req()
4706 sata_cmd.esgl = 0; in pm80xx_chip_sata_req()
4710 sata_cmd.atapi_scsi_cdb[0] = in pm80xx_chip_sata_req()
4711 cpu_to_le32(((task->ata_task.atapi_packet[0]) | in pm80xx_chip_sata_req()
4712 (task->ata_task.atapi_packet[1] << 8) | in pm80xx_chip_sata_req()
4713 (task->ata_task.atapi_packet[2] << 16) | in pm80xx_chip_sata_req()
4714 (task->ata_task.atapi_packet[3] << 24))); in pm80xx_chip_sata_req()
4716 cpu_to_le32(((task->ata_task.atapi_packet[4]) | in pm80xx_chip_sata_req()
4717 (task->ata_task.atapi_packet[5] << 8) | in pm80xx_chip_sata_req()
4718 (task->ata_task.atapi_packet[6] << 16) | in pm80xx_chip_sata_req()
4719 (task->ata_task.atapi_packet[7] << 24))); in pm80xx_chip_sata_req()
4721 cpu_to_le32(((task->ata_task.atapi_packet[8]) | in pm80xx_chip_sata_req()
4722 (task->ata_task.atapi_packet[9] << 8) | in pm80xx_chip_sata_req()
4723 (task->ata_task.atapi_packet[10] << 16) | in pm80xx_chip_sata_req()
4724 (task->ata_task.atapi_packet[11] << 24))); in pm80xx_chip_sata_req()
4726 cpu_to_le32(((task->ata_task.atapi_packet[12]) | in pm80xx_chip_sata_req()
4727 (task->ata_task.atapi_packet[13] << 8) | in pm80xx_chip_sata_req()
4728 (task->ata_task.atapi_packet[14] << 16) | in pm80xx_chip_sata_req()
4729 (task->ata_task.atapi_packet[15] << 24))); in pm80xx_chip_sata_req()
4733 if (sata_cmd.sata_fis.command == 0x2f) { in pm80xx_chip_sata_req()
4734 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) || in pm80xx_chip_sata_req()
4735 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) || in pm80xx_chip_sata_req()
4736 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) { in pm80xx_chip_sata_req()
4739 pm8001_ha_dev->id &= 0xDFFFFFFF; in pm80xx_chip_sata_req()
4740 ts = &task->task_status; in pm80xx_chip_sata_req()
4742 spin_lock_irqsave(&task->task_state_lock, flags); in pm80xx_chip_sata_req()
4743 ts->resp = SAS_TASK_COMPLETE; in pm80xx_chip_sata_req()
4744 ts->stat = SAS_SAM_STAT_GOOD; in pm80xx_chip_sata_req()
4745 task->task_state_flags &= ~SAS_TASK_STATE_PENDING; in pm80xx_chip_sata_req()
4746 task->task_state_flags |= SAS_TASK_STATE_DONE; in pm80xx_chip_sata_req()
4747 if (unlikely((task->task_state_flags & in pm80xx_chip_sata_req()
4749 spin_unlock_irqrestore(&task->task_state_lock, in pm80xx_chip_sata_req()
4752 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n", in pm80xx_chip_sata_req()
4753 task, ts->resp, in pm80xx_chip_sata_req()
4754 ts->stat); in pm80xx_chip_sata_req()
4756 return 0; in pm80xx_chip_sata_req()
4758 spin_unlock_irqrestore(&task->task_state_lock, in pm80xx_chip_sata_req()
4761 atomic_dec(&pm8001_ha_dev->running_req); in pm80xx_chip_sata_req()
4762 return 0; in pm80xx_chip_sata_req()
4766 trace_pm80xx_request_issue(pm8001_ha->id, in pm80xx_chip_sata_req()
4767 ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS, in pm80xx_chip_sata_req()
4768 ccb->ccb_tag, opc, in pm80xx_chip_sata_req()
4769 qc ? qc->tf.command : 0, // ata opcode in pm80xx_chip_sata_req()
4770 ccb->device ? atomic_read(&ccb->device->running_req) : 0); in pm80xx_chip_sata_req()
4776 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4784 u32 tag = 0x01; in pm80xx_chip_phy_start_req()
4787 memset(&payload, 0, sizeof(payload)); in pm80xx_chip_phy_start_req()
4793 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id); in pm80xx_chip_phy_start_req()
4806 &pm8001_ha->sas_addr, SAS_ADDR_SIZE); in pm80xx_chip_phy_start_req()
4809 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, in pm80xx_chip_phy_start_req()
4810 sizeof(payload), 0); in pm80xx_chip_phy_start_req()
4814 * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4822 u32 tag = 0x01; in pm80xx_chip_phy_stop_req()
4825 memset(&payload, 0, sizeof(payload)); in pm80xx_chip_phy_stop_req()
4829 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload, in pm80xx_chip_phy_stop_req()
4830 sizeof(payload), 0); in pm80xx_chip_phy_stop_req()
4841 u32 stp_sspsmp_sata = 0x4; in pm80xx_chip_reg_dev_req()
4845 u8 retryFlag = 0x1; in pm80xx_chip_reg_dev_req()
4846 u16 firstBurstSize = 0; in pm80xx_chip_reg_dev_req()
4848 struct domain_device *dev = pm8001_dev->sas_device; in pm80xx_chip_reg_dev_req()
4849 struct domain_device *parent_dev = dev->parent; in pm80xx_chip_reg_dev_req()
4850 struct pm8001_port *port = dev->port->lldd_port; in pm80xx_chip_reg_dev_req()
4852 memset(&payload, 0, sizeof(payload)); in pm80xx_chip_reg_dev_req()
4855 return -SAS_QUEUE_FULL; in pm80xx_chip_reg_dev_req()
4857 payload.tag = cpu_to_le32(ccb->ccb_tag); in pm80xx_chip_reg_dev_req()
4860 stp_sspsmp_sata = 0x02; /*direct attached sata */ in pm80xx_chip_reg_dev_req()
4862 if (pm8001_dev->dev_type == SAS_SATA_DEV) in pm80xx_chip_reg_dev_req()
4863 stp_sspsmp_sata = 0x00; /* stp*/ in pm80xx_chip_reg_dev_req()
4864 else if (pm8001_dev->dev_type == SAS_END_DEVICE || in pm80xx_chip_reg_dev_req()
4865 dev_is_expander(pm8001_dev->dev_type)) in pm80xx_chip_reg_dev_req()
4866 stp_sspsmp_sata = 0x01; /*ssp or smp*/ in pm80xx_chip_reg_dev_req()
4868 if (parent_dev && dev_is_expander(parent_dev->dev_type)) in pm80xx_chip_reg_dev_req()
4869 phy_id = parent_dev->ex_dev.ex_phy->phy_id; in pm80xx_chip_reg_dev_req()
4871 phy_id = pm8001_dev->attached_phy; in pm80xx_chip_reg_dev_req()
4875 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ? in pm80xx_chip_reg_dev_req()
4876 pm8001_dev->sas_device->linkrate : dev->port->linkrate; in pm80xx_chip_reg_dev_req()
4879 cpu_to_le32(((port->port_id) & 0xFF) | in pm80xx_chip_reg_dev_req()
4880 ((phy_id & 0xFF) << 8)); in pm80xx_chip_reg_dev_req()
4882 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) | in pm80xx_chip_reg_dev_req()
4883 ((linkrate & 0x0F) << 24) | in pm80xx_chip_reg_dev_req()
4884 ((stp_sspsmp_sata & 0x03) << 28)); in pm80xx_chip_reg_dev_req()
4886 cpu_to_le32(ITNT | (firstBurstSize * 0x10000)); in pm80xx_chip_reg_dev_req()
4888 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr, in pm80xx_chip_reg_dev_req()
4891 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, in pm80xx_chip_reg_dev_req()
4892 sizeof(payload), 0); in pm80xx_chip_reg_dev_req()
4900 * pm80xx_chip_phy_ctl_req - support the local phy operation
4913 memset(&payload, 0, sizeof(payload)); in pm80xx_chip_phy_ctl_req()
4920 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF)); in pm80xx_chip_phy_ctl_req()
4922 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, in pm80xx_chip_phy_ctl_req()
4923 sizeof(payload), 0); in pm80xx_chip_phy_ctl_req()
4937 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR); in pm80xx_chip_is_our_interrupt()
4940 return 0; in pm80xx_chip_is_our_interrupt()
4945 * pm80xx_chip_isr - PM8001 isr handler.
4954 "irq vec %d, ODMR:0x%x\n", in pm80xx_chip_isr()
4955 vec, pm8001_cr32(pm8001_ha, 0, 0x30)); in pm80xx_chip_isr()
4965 u32 tag, i, j = 0; in mpi_set_phy_profile_req()
4970 memset(&payload, 0, sizeof(payload)); in mpi_set_phy_profile_req()
4979 cpu_to_le32(((operation & 0xF) << 8) | (phyid & 0xFF)); in mpi_set_phy_profile_req()
4983 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) { in mpi_set_phy_profile_req()
4987 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, in mpi_set_phy_profile_req()
4988 sizeof(payload), 0); in mpi_set_phy_profile_req()
4998 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { in pm8001_set_phy_profile()
5013 memset(&payload, 0, sizeof(payload)); in pm8001_set_phy_profile_single()
5025 cpu_to_le32(((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8) in pm8001_set_phy_profile_single()
5026 | (phy & 0xFF)); in pm8001_set_phy_profile_single()
5028 for (i = 0; i < length; i++) in pm8001_set_phy_profile_single()
5031 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload, in pm8001_set_phy_profile_single()
5032 sizeof(payload), 0); in pm8001_set_phy_profile_single()