393 	u32 regVal;  in pm8001_bar4_shift()  local
402 		regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);  in pm8001_bar4_shift()
403 	} while ((regVal != shiftValue) && time_before(jiffies, start));  in pm8001_bar4_shift()
405 	if (regVal != shiftValue) {  in pm8001_bar4_shift()
408 			   regVal);  in pm8001_bar4_shift()
766 	u32 regVal, regVal1, regVal2;  in soft_reset_ready_check()  local
772 	regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)  in soft_reset_ready_check()
774 	if (regVal == SCRATCH_PAD2_FWRDY_RST) {  in soft_reset_ready_check()
792 		regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &  in soft_reset_ready_check()
794 		if (regVal != SCRATCH_PAD2_FWRDY_RST) {  in soft_reset_ready_check()
821 	u32	regVal, toggleVal;  in pm8001_chip_soft_rst()  local
843 	regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);  in pm8001_chip_soft_rst()
845 		   regVal);  in pm8001_chip_soft_rst()
854 	regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);  in pm8001_chip_soft_rst()
856 		   regVal);  in pm8001_chip_soft_rst()
859 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);  in pm8001_chip_soft_rst()
861 		   regVal);  in pm8001_chip_soft_rst()
864 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);  in pm8001_chip_soft_rst()
866 		   regVal);  in pm8001_chip_soft_rst()
867 	pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);  in pm8001_chip_soft_rst()
869 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);  in pm8001_chip_soft_rst()
871 		   regVal);  in pm8001_chip_soft_rst()
874 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);  in pm8001_chip_soft_rst()
875 	pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);  in pm8001_chip_soft_rst()
876 	pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);  in pm8001_chip_soft_rst()
879 	regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)  in pm8001_chip_soft_rst()
881 	toggleVal = regVal ^ SCRATCH_PAD1_RST;  in pm8001_chip_soft_rst()
900 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);  in pm8001_chip_soft_rst()
909 	regVal &= ~(0x00003b00);  in pm8001_chip_soft_rst()
911 	pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);  in pm8001_chip_soft_rst()
955 	regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);  in pm8001_chip_soft_rst()
957 		   regVal);  in pm8001_chip_soft_rst()
959 	regVal &= 0xFFFFFFFC;  in pm8001_chip_soft_rst()
960 	pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);  in pm8001_chip_soft_rst()
970 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);  in pm8001_chip_soft_rst()
972 		   regVal);  in pm8001_chip_soft_rst()
973 	regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);  in pm8001_chip_soft_rst()
974 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);  in pm8001_chip_soft_rst()
977 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);  in pm8001_chip_soft_rst()
979 		   regVal);  in pm8001_chip_soft_rst()
980 	regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);  in pm8001_chip_soft_rst()
981 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);  in pm8001_chip_soft_rst()
987 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);  in pm8001_chip_soft_rst()
990 		   regVal);  in pm8001_chip_soft_rst()
991 	regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);  in pm8001_chip_soft_rst()
992 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);  in pm8001_chip_soft_rst()
1008 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);  in pm8001_chip_soft_rst()
1017 	regVal |= (GSM_CONFIG_RESET_VALUE);  in pm8001_chip_soft_rst()
1018 	pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);  in pm8001_chip_soft_rst()
1023 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);  in pm8001_chip_soft_rst()
1027 		   regVal);  in pm8001_chip_soft_rst()
1032 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);  in pm8001_chip_soft_rst()
1038 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);  in pm8001_chip_soft_rst()
1052 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);  in pm8001_chip_soft_rst()
1053 	regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);  in pm8001_chip_soft_rst()
1054 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);  in pm8001_chip_soft_rst()
1065 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &  in pm8001_chip_soft_rst()
1067 		} while ((regVal != toggleVal) && (--max_wait_count));  in pm8001_chip_soft_rst()
1070 			regVal = pm8001_cr32(pm8001_ha, 0,  in pm8001_chip_soft_rst()
1073 				   toggleVal, regVal);  in pm8001_chip_soft_rst()
1098 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);  in pm8001_chip_soft_rst()
1102 				   regVal);  in pm8001_chip_soft_rst()
1103 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);  in pm8001_chip_soft_rst()
1107 				   regVal);  in pm8001_chip_soft_rst()
1130 	u32 regVal;  in pm8001_hw_chip_rst()  local
1134 	regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);  in pm8001_hw_chip_rst()
1135 	regVal &= ~(SPC_REG_RESET_DEVICE);  in pm8001_hw_chip_rst()
1136 	pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);  in pm8001_hw_chip_rst()
1142 	regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);  in pm8001_hw_chip_rst()
1143 	regVal |= SPC_REG_RESET_DEVICE;  in pm8001_hw_chip_rst()
1144 	pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);  in pm8001_hw_chip_rst()