Lines Matching +full:1 +full:w
33 MODEL_KME = 1,
65 # define TRUE 1
70 #define ASSERT 1
81 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
82 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
84 # define IRQSTATUS_LATCHED_IO BIT(1)
112 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
113 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
115 # define CB_IO_MODE BIT(1)
130 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
132 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
136 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
137 #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
139 #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
144 #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
146 # define SREQSMPLRATE_RATE1 BIT(1)
152 #define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
154 # define BUSCTL_RST BIT(1)
162 #define CLR_COUNTER 0x12 /* BASE+12, B, W */
164 # define SREQ_COUNTER_CLR BIT(1)
178 # define BUSMON_IO BIT(1)
186 #define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
188 #define PARITY_CONTROL 0x16 /* BASE+16, B, W */
190 # define PARITY_ERROR_CLEAR BIT(1)
193 # define PARITY_ERROR_NORMAL BIT(1)
194 # define PARITY_ERROR_LSB BIT(1)
199 #define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
201 # define AUTO_COMMAND_PHASE BIT(1)
210 #define SET_ARBIT 0x1a /* BASE+1a, B, W */
212 # define ARBIT_CLEAR BIT(1)
214 #define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
216 # define ARBIT_WIN BIT(1)
221 #define SYNC_REG 0x1c /* BASE+1c, B, R/W */
223 #define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
225 #define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
226 #define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
229 #define SCAM_CONTROL 0x24 /* BASE+24, B, W */
232 # define SCAM_IO BIT(1)
238 #define SCAM_DATA 0x26 /* BASE+26, B, R/W */
240 # define SD1 BIT(1)
248 #define SACK_CNT 0x28 /* BASE+28, DW, R/W */
249 #define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
251 #define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
252 #define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
253 #define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
255 #define BM_CNT 0x38 /* BASE+38, DW, R/W */
259 #define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
262 #define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
264 # define DATA_IN_PHASE BIT(1)
281 #define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
282 # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
285 #define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
288 #define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
289 #define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
290 #define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
291 #define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
298 #define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
300 # define CLOCK_4 BIT(1) /* MCLK/4 */
303 #define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
305 # define SENSE BIT(1) /* Read Only */
307 #define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
308 #define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
312 #define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
314 # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
327 # define OLD_IO BIT(1)
331 #define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
332 #define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
334 #define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
336 # define IO_ACCESS_ENB BIT(1)
339 #define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
341 #define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
344 # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
352 #define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
355 # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
364 #define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
366 # define BM_CYCLE1 BIT(1)
375 #define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
378 #define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */
380 # define ACKCNT_UP BIT(1)
385 #define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
386 #define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
387 #define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
388 #define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
389 #define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
393 # define ENA BIT(1)
396 #define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
397 #define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
398 #define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
399 #define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
400 #define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
401 #define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
402 #define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
403 #define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
404 #define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
405 #define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
406 #define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
407 #define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
408 #define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
409 #define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
446 nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */
474 #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
485 #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
520 #define SDTR_TARGET BIT(1) /* sending SDTR from target */
611 (25.6us/1unit) */