Lines Matching +full:rx +full:- +full:max +full:- +full:burst +full:- +full:prd
1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
38 MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */
43 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
48 MVS_MAX_PHYS = 8, /* max. possible phys */
49 MVS_MAX_PORTS = 8, /* max. possible ports */
52 MVS_MAX_DEVICES = 1024, /* max supported device */
78 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
115 RX_EN = (1U << 16), /* Enable RX */
116 RX_RING_SZ_MASK = 0xfff, /* RX ring size, bits 11:0 */
125 CINT_PRD_BC = (1U << 28), /* PRD BC err for read cmd */
134 /* shl for ports 1-3 */
161 /* RX (completion) ring bits */
172 MCH_PRD_LEN_SHIFT = 16, /* 16-bit PRD table len */
189 MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
190 MCH_FBURST = (1U << 11), /* first burst (SSP) */
203 CCTL_ENDIAN_DATA = (1U << 3), /* PRD data */
208 /* MVS_Px_SER_CTLSTAT (per-phy control) */
215 /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
219 PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */
223 PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */
228 PHYEV_COMWAKE = (1U << 7), /* COMWAKE rx'd */
230 PHYEV_HARD_RST = (1U << 5), /* hard reset rx'd */
242 PCS_RSP_RX_EN = (1U << 7), /* raw response rx */
244 PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
245 PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */
246 PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
280 PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */
281 PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */
282 PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */
283 PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */
297 PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */
298 PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */
299 PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */
300 PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */
327 CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */
329 CMD_OOB_BURST = 0x114, /* OOB burst control register */
427 DMA_TERM = (1U << 26), /* DMA terminate primitive rx'd */
428 SYNC_ERR = (1U << 25), /* SYNC rx'd during frame xmit */
436 NAK = (1U << 14), /* NAK rx'd */