251 	mw32(MVS_PCS, tmp);  in mvs_94xx_enable_xmt()
324 	mw32(MVS_HST_CHIP_CONFIG, tmp);  in mvs_94xx_sgpio_init()
326 	mw32(MVS_SGPIO_CTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
329 	mw32(MVS_SGPIO_CFG1 + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
338 	mw32(MVS_SGPIO_CFG2 + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
343 	mw32(MVS_SGPIO_CFG0 + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
351 	mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
354 	mw32(MVS_SGPIO_DSRC + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
375 		mw32(MVS_PHY_CTL, tmp);  in mvs_94xx_init()
392 		mw32(MVS_PHY_CTL, tmp);  in mvs_94xx_init()
395 		mw32(MVS_PHY_CTL, tmp);  in mvs_94xx_init()
400 	mw32(MVS_PORTS_IMP, 0xFF);  in mvs_94xx_init()
403 		mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET);  in mvs_94xx_init()
404 		mw32(MVS_PA_VSR_PORT, 0x00018080);  in mvs_94xx_init()
406 	mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2);  in mvs_94xx_init()
409 		mw32(MVS_PA_VSR_PORT, 0x0084d4fe);  in mvs_94xx_init()
412 		mw32(MVS_PA_VSR_PORT, 0x0084fffe);  in mvs_94xx_init()
415 		mw32(MVS_PA_VSR_ADDR, CMD_APP_MEM_CTL);  in mvs_94xx_init()
416 		mw32(MVS_PA_VSR_PORT, 0x08001006);  in mvs_94xx_init()
417 		mw32(MVS_PA_VSR_ADDR, CMD_HOST_RD_DATA);  in mvs_94xx_init()
418 		mw32(MVS_PA_VSR_PORT, 0x0000705f);  in mvs_94xx_init()
422 	mw32(MVS_PCS, 0);		/* MVS_PCS */  in mvs_94xx_init()
423 	mw32(MVS_STP_REG_SET_0, 0);  in mvs_94xx_init()
424 	mw32(MVS_STP_REG_SET_1, 0);  in mvs_94xx_init()
440 	mw32(MVS_PA_VSR_ADDR, VSR_PHY_ACT_LED);  in mvs_94xx_init()
444 	mw32(MVS_PA_VSR_PORT, tmp);  in mvs_94xx_init()
446 	mw32(MVS_CMD_LIST_LO, mvi->slot_dma);  in mvs_94xx_init()
447 	mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);  in mvs_94xx_init()
449 	mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);  in mvs_94xx_init()
450 	mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);  in mvs_94xx_init()
452 	mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);  in mvs_94xx_init()
453 	mw32(MVS_TX_LO, mvi->tx_dma);  in mvs_94xx_init()
454 	mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);  in mvs_94xx_init()
456 	mw32(MVS_RX_CFG, MVS_RX_RING_SZ);  in mvs_94xx_init()
457 	mw32(MVS_RX_LO, mvi->rx_dma);  in mvs_94xx_init()
458 	mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);  in mvs_94xx_init()
512 	mw32(MVS_PCS, tmp);  in mvs_94xx_init()
519 		mw32(MVS_INT_COAL, 0x1ff | COAL_EN);  in mvs_94xx_init()
521 		mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN);  in mvs_94xx_init()
525 	mw32(MVS_INT_COAL_TMOUT, tmp);  in mvs_94xx_init()
528 	mw32(MVS_TX_CFG, 0);  in mvs_94xx_init()
529 	mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);  in mvs_94xx_init()
530 	mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);  in mvs_94xx_init()
532 	mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN |  in mvs_94xx_init()
539 	mw32(MVS_INT_MASK, tmp);  in mvs_94xx_init()
563 	mw32(MVS_INT_MASK_SRS_0, 0xFFFF);  in mvs_94xx_init()
599 	mw32(MVS_GBL_INT_STAT, tmp);  in mvs_94xx_interrupt_enable()
604 	mw32(MVS_GBL_CTL, tmp);  in mvs_94xx_interrupt_enable()
615 	mw32(MVS_GBL_INT_STAT, tmp);  in mvs_94xx_interrupt_disable()
620 	mw32(MVS_GBL_CTL, tmp);  in mvs_94xx_interrupt_disable()
676 			mw32(MVS_INT_STAT_SRS_0, tmp);  in mvs_94xx_clear_srs_irq()
681 			mw32(MVS_INT_STAT_SRS_1, tmp);  in mvs_94xx_clear_srs_irq()
692 				mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32));  in mvs_94xx_clear_srs_irq()
694 				mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));  in mvs_94xx_clear_srs_irq()
707 	mw32(MVS_INT_STAT, tmp | CINT_CI_STOP);  in mvs_94xx_issue_stop()
709 	mw32(MVS_PCS, tmp);  in mvs_94xx_issue_stop()
737 	mw32(MVS_NON_NCQ_ERR_0, err_0);  in mvs_94xx_non_spec_ncq_error()
738 	mw32(MVS_NON_NCQ_ERR_1, err_1);  in mvs_94xx_non_spec_ncq_error()
916 	mw32(MVS_STP_REG_SET_0, 0);  in mvs_94xx_clear_active_cmds()
917 	mw32(MVS_STP_REG_SET_0, tmp);  in mvs_94xx_clear_active_cmds()
919 	mw32(MVS_STP_REG_SET_1, 0);  in mvs_94xx_clear_active_cmds()
920 	mw32(MVS_STP_REG_SET_1, tmp);  in mvs_94xx_clear_active_cmds()
934 	mw32(SPI_RD_DATA_REG_94XX, data);  in mvs_94xx_spi_write_data()
954 		mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL));  in mvs_94xx_spi_buildcmd()
966 	mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX);  in mvs_94xx_spi_issuecmd()
1027 		mw32(MVS_INT_COAL, 0);  in mvs_94xx_tune_interrupt()
1028 		mw32(MVS_INT_COAL_TMOUT, 0x10000);  in mvs_94xx_tune_interrupt()
1031 			mw32(MVS_INT_COAL, 0x1ff|COAL_EN);  in mvs_94xx_tune_interrupt()
1033 			mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN);  in mvs_94xx_tune_interrupt()
1036 		mw32(MVS_INT_COAL_TMOUT, tmp);  in mvs_94xx_tune_interrupt()
1120 			mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_gpio_write()