Lines Matching refs:mw32
38 mw32(MVS_PCS, tmp); in mvs_64xx_enable_xmt()
55 mw32(MVS_GBL_PORT_TYPE, 0); in mvs_64xx_phy_hacks()
98 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_stp_reset()
100 mw32(MVS_PHY_CTL, reg); in mvs_64xx_stp_reset()
132 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_clear_srs_irq()
139 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); in mvs_64xx_clear_srs_irq()
151 mw32(MVS_GBL_CTL, 0); in mvs_64xx_chip_reset()
170 mw32(MVS_GBL_CTL, 0); in mvs_64xx_chip_reset()
212 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_phy_disable()
234 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_phy_enable()
255 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_init()
288 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_init()
291 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_init()
296 mw32(MVS_PCS, 0); /* MVS_PCS */ in mvs_64xx_init()
306 mw32(MVS_GBL_PORT_TYPE, MODE_AUTO_DET_EN); in mvs_64xx_init()
308 mw32(MVS_CMD_LIST_LO, mvi->slot_dma); in mvs_64xx_init()
309 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16); in mvs_64xx_init()
311 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma); in mvs_64xx_init()
312 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16); in mvs_64xx_init()
314 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ); in mvs_64xx_init()
315 mw32(MVS_TX_LO, mvi->tx_dma); in mvs_64xx_init()
316 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16); in mvs_64xx_init()
318 mw32(MVS_RX_CFG, MVS_RX_RING_SZ); in mvs_64xx_init()
319 mw32(MVS_RX_LO, mvi->rx_dma); in mvs_64xx_init()
320 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16); in mvs_64xx_init()
373 mw32(MVS_PCS, tmp); in mvs_64xx_init()
380 mw32(MVS_INT_COAL, 0x1ff | COAL_EN); in mvs_64xx_init()
382 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN); in mvs_64xx_init()
385 mw32(MVS_INT_COAL_TMOUT, tmp); in mvs_64xx_init()
388 mw32(MVS_TX_CFG, 0); in mvs_64xx_init()
389 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN); in mvs_64xx_init()
390 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN); in mvs_64xx_init()
392 mw32(MVS_PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN | in mvs_64xx_init()
399 mw32(MVS_INT_MASK, tmp); in mvs_64xx_init()
402 mw32(MVS_INT_MASK_SRS_0, 0xFFFF); in mvs_64xx_init()
426 mw32(MVS_GBL_CTL, tmp | INT_EN); in mvs_64xx_interrupt_enable()
435 mw32(MVS_GBL_CTL, tmp & ~INT_EN); in mvs_64xx_interrupt_disable()
488 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_issue_stop()
490 mw32(MVS_INT_STAT, CINT_CI_STOP); in mvs_64xx_issue_stop()
492 mw32(MVS_PCS, tmp); in mvs_64xx_issue_stop()
506 mw32(MVS_PCS, tmp & ~offs); in mvs_64xx_free_reg_set()
509 mw32(MVS_CTL, tmp & ~offs); in mvs_64xx_free_reg_set()
514 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_free_reg_set()
539 mw32(MVS_PCS, tmp | offs); in mvs_64xx_assign_reg_set()
541 mw32(MVS_CTL, tmp | offs); in mvs_64xx_assign_reg_set()
544 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_assign_reg_set()
648 mw32(MVS_PCS, tmp & 0xFFFF); in mvs_64xx_clear_active_cmds()
649 mw32(MVS_PCS, tmp); in mvs_64xx_clear_active_cmds()
651 mw32(MVS_CTL, tmp & 0xFFFF); in mvs_64xx_clear_active_cmds()
652 mw32(MVS_CTL, tmp); in mvs_64xx_clear_active_cmds()
748 mw32(MVS_INT_COAL, 0); in mvs_64xx_tune_interrupt()
749 mw32(MVS_INT_COAL_TMOUT, 0x10000); in mvs_64xx_tune_interrupt()
752 mw32(MVS_INT_COAL, 0x1ff|COAL_EN); in mvs_64xx_tune_interrupt()
754 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN); in mvs_64xx_tune_interrupt()
757 mw32(MVS_INT_COAL_TMOUT, tmp); in mvs_64xx_tune_interrupt()