2053 			  (unsigned long)ha->mem_ptr);  in ips_host_info()
2253 			writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_get_bios_version()
2257 			if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)  in ips_get_bios_version()
2260 			writel(1, ha->mem_ptr + IPS_REG_FLAP);  in ips_get_bios_version()
2264 			if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)  in ips_get_bios_version()
2268 			writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);  in ips_get_bios_version()
2272 			major = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_get_bios_version()
2275 			writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);  in ips_get_bios_version()
2278 			minor = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_get_bios_version()
2281 			writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);  in ips_get_bios_version()
2284 			subminor = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_get_bios_version()
4259 		if (ha->mem_ptr) {  in ips_free()
4262 			ha->mem_ptr = NULL;  in ips_free()
4505 	isr = readb(ha->mem_ptr + IPS_REG_HISR);  in ips_isinit_copperhead_memio()
4506 	scpr = readb(ha->mem_ptr + IPS_REG_SCPR);  in ips_isinit_copperhead_memio()
4534 	post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);  in ips_isinit_morpheus()
4535 	bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_isinit_morpheus()
4664 	writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);  in ips_enable_int_copperhead_memio()
4665 	readb(ha->mem_ptr + IPS_REG_HISR);	/*Ensure PCI Posting Completes*/  in ips_enable_int_copperhead_memio()
4683 	Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);  in ips_enable_int_morpheus()
4685 	writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);  in ips_enable_int_morpheus()
4686 	readl(ha->mem_ptr + IPS_REG_I960_OIMR);	/*Ensure PCI Posting Completes*/  in ips_enable_int_morpheus()
4803 			Isr = readb(ha->mem_ptr + IPS_REG_HISR);  in ips_init_copperhead_memio()
4815 		PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);  in ips_init_copperhead_memio()
4816 		writeb(Isr, ha->mem_ptr + IPS_REG_HISR);  in ips_init_copperhead_memio()
4829 			Isr = readb(ha->mem_ptr + IPS_REG_HISR);  in ips_init_copperhead_memio()
4841 		readb(ha->mem_ptr + IPS_REG_ISPR);  in ips_init_copperhead_memio()
4842 		writeb(Isr, ha->mem_ptr + IPS_REG_HISR);  in ips_init_copperhead_memio()
4846 		Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);  in ips_init_copperhead_memio()
4860 	writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);  in ips_init_copperhead_memio()
4863 	writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);  in ips_init_copperhead_memio()
4867 		writel(0, ha->mem_ptr + IPS_REG_NDAE);  in ips_init_copperhead_memio()
4870 	writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);  in ips_init_copperhead_memio()
4898 		Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_init_morpheus()
4915 	Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);  in ips_init_morpheus()
4923 		writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_init_morpheus()
4926 			Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);  in ips_init_morpheus()
4943 	writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_init_morpheus()
4954 		Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_init_morpheus()
4971 	Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);  in ips_init_morpheus()
4975 	writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_init_morpheus()
4978 	Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);  in ips_init_morpheus()
4980 	writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);  in ips_init_morpheus()
5062 		writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);  in ips_reset_copperhead_memio()
5067 		writeb(0, ha->mem_ptr + IPS_REG_SCPR);  in ips_reset_copperhead_memio()
5108 		writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);  in ips_reset_morpheus()
5179 	writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);  in ips_statinit_memio()
5181 	       ha->mem_ptr + IPS_REG_SQER);  in ips_statinit_memio()
5182 	writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);  in ips_statinit_memio()
5183 	writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);  in ips_statinit_memio()
5238 	writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);  in ips_statupd_copperhead_memio()
5259 	val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);  in ips_statupd_morpheus()
5349 	while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {  in ips_issue_copperhead_memio()
5365 	writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);  in ips_issue_copperhead_memio()
5366 	writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);  in ips_issue_copperhead_memio()
5430 	writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);  in ips_issue_i2o_memio()
5484 	Isr = readb(ha->mem_ptr + IPS_REG_HISR);  in ips_isintr_copperhead_memio()
5495 		writeb(Isr, ha->mem_ptr + IPS_REG_HISR);  in ips_isintr_copperhead_memio()
5517 	Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);  in ips_isintr_morpheus()
6137 	writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_erase_bios_memio()
6141 	writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6146 	writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6151 	writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6156 	writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6164 			writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_erase_bios_memio()
6168 		status = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6182 		writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6190 				writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_erase_bios_memio()
6194 			status = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6218 	writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6223 	writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);  in ips_erase_bios_memio()
6343 		writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);  in ips_program_bios_memio()
6347 		writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6351 		writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6359 				writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_program_bios_memio()
6363 			status = readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6374 			writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_program_bios_memio()
6378 			writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6388 			writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_program_bios_memio()
6392 			writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6401 	writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_program_bios_memio()
6405 	writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);  in ips_program_bios_memio()
6479 	writel(0, ha->mem_ptr + IPS_REG_FLAP);  in ips_verify_bios_memio()
6483 	if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)  in ips_verify_bios_memio()
6486 	writel(1, ha->mem_ptr + IPS_REG_FLAP);  in ips_verify_bios_memio()
6489 	if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)  in ips_verify_bios_memio()
6495 		writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);  in ips_verify_bios_memio()
6500 		    (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);  in ips_verify_bios_memio()
6844 	char __iomem *mem_ptr;  in ips_init_phase1()  local
6888 		mem_ptr = ioremap_ptr + offs;  in ips_init_phase1()
6891 		mem_ptr = NULL;  in ips_init_phase1()
6911 	ha->mem_ptr = mem_ptr;  in ips_init_phase1()
7013 		IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);  in ips_init_phase1()